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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ilu_peu / vera / include / ilupeuScenarioDefines.vri
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ilupeuScenarioDefines.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef ILUPEU_SCENARIO_DEFINE
36#define ILUPEU_SCENARIO_DEFINE
37
38/* These are already defined in lpr_a.csr_define.vri
39`define FIRE_PLC_TLU_CTB_LPR_A_CSRBUS_EXT_ADDR_WIDTH 13
40`define FIRE_PLC_TLU_CTB_LPR_A_CSRBUS_EXT_ADDR_RANGE 12:0
41
42//-------------------------------------------------------
43//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB
44//-------------------------------------------------------
45
46`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ADDR 20'b11011100000000000000
47`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ADDR 30'b000000011011100000000000000000
48`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_NAME "fire_plc_tlu_ctb_lpr_csr_a_ahb"
49`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_WIDTH 64
50`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DEPTH 8192
51`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_SLC 63:0
52`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_INT_SLC 63:0
53`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_POSITION 0
54`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_ahb"
55`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_LOW_ADDR_WIDTH 13
56`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_SEL_RANGE 12:0
57`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ADDR_RANGE 19:13
58`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
59`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
60`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
61`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
62`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
63`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
64`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
65`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
66`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
67`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
68`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
69`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_INTERNAL_REG 0
70`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_EXTERNAL_DECODE_REG 0
71`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ALIASED_FROM 0
72`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_ZERO_TIME_OMNI 0
73`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_JTAG_RD 1
74`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_JTAG_WR 1
75`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_SBUS_RD 1
76`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_SBUS_WR 1
77`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_RAP_RD 1
78`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_HW_ACC_RAP_WR 1
79`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_NUM_FIELDS 1
80`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_FID 0
81`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_SLC 31:0
82`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_WIDTH 32
83`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_INT_SLC 31:0
84`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_POSITION 0
85`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
86`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
87`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_POR_VALUE 32'b00000000000000000000000000000000
88`define FIRE_PLC_TLU_CTB_LPR_CSR_A_AHB_DATA_FIELD_NAME "data"
89
90
91
92*/
93
94//-------------------------------------------------------
95//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID
96//-------------------------------------------------------
97
98`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ADDR 20'b11011100010000000000
99`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_ADDR 30'b000000011011100010000000000000
100`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_id"
101`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_WIDTH 64
102`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_DEPTH 1
103`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_SLC 63:0
104`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_INT_SLC 63:0
105`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_POSITION 0
106`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_id"
107`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LOW_ADDR_WIDTH 0
108`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_ADDR_RANGE 19:0
109`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_READ_MASK 64'b0000000000000000000000000000000000000000111111111111111111111111
110`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000111111111111111111111111
111`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
112`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
113`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
114`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
115`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
116`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_RMASK 64'b0000000000000000000000000000000000000000111111111111111111111111
117`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111000000000000000000000000
118`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
119`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_POR_VALUE 64'b0000000000000000000000000000000000000000011001100000000000000001
120`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_INTERNAL_REG 0
121`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_EXTERNAL_DECODE_REG 0
122`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_ALIASED_FROM 0
123`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_ZERO_TIME_OMNI 0
124`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_JTAG_RD 1
125`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_JTAG_WR 1
126`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_SBUS_RD 1
127`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_SBUS_WR 1
128`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_RAP_RD 1
129`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_HW_ACC_RAP_WR 1
130`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_NUM_FIELDS 6
131`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_FID 0
132`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_SLC 23:20
133`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_WIDTH 4
134`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_INT_SLC 3:0
135`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_POSITION 20
136`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_FMASK 64'b0000000000000000000000000000000000000000111100000000000000000000
137`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
138`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_POR_VALUE 4'b0110
139`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LTBWDTH_FIELD_NAME "ltbwdth"
140`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_FID 1
141`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_SLC 19:16
142`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_WIDTH 4
143`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_INT_SLC 3:0
144`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_POSITION 16
145`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_FMASK 64'b0000000000000000000000000000000000000000000011110000000000000000
146`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
147`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_POR_VALUE 4'b0110
148`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PTLWDTH_FIELD_NAME "ptlwdth"
149`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_FID 2
150`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_SLC 15:12
151`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_WIDTH 4
152`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_INT_SLC 3:0
153`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_POSITION 12
154`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_FMASK 64'b0000000000000000000000000000000000000000000000001111000000000000
155`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
156`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_POR_VALUE 4'b0000
157`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_TRID_FIELD_NAME "trid"
158`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_FID 3
159`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_SLC 11:8
160`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_WIDTH 4
161`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_INT_SLC 3:0
162`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_POSITION 8
163`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_FMASK 64'b0000000000000000000000000000000000000000000000000000111100000000
164`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
165`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_POR_VALUE 4'b0000
166`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_LNKID_FIELD_NAME "lnkid"
167`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_FID 4
168`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_SLC 7:4
169`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_WIDTH 4
170`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_INT_SLC 3:0
171`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_POSITION 4
172`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_FMASK 64'b0000000000000000000000000000000000000000000000000000000011110000
173`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
174`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_POR_VALUE 4'b0000
175`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_PHYID_FIELD_NAME "phyid"
176`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_FID 5
177`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_SLC 3:0
178`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_WIDTH 4
179`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_INT_SLC 3:0
180`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_POSITION 0
181`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001111
182`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
183`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_POR_VALUE 4'b0001
184`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ID_GBID_FIELD_NAME "gbid"
185
186//-------------------------------------------------------
187//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST
188//-------------------------------------------------------
189
190`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ADDR 20'b11011100010000000001
191`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_ADDR 30'b000000011011100010000000001000
192`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rst"
193`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_WIDTH 64
194`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_DEPTH 1
195`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_SLC 63:0
196`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_INT_SLC 63:0
197`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_POSITION 0
198`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rst"
199`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_LOW_ADDR_WIDTH 0
200`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_ADDR_RANGE 19:0
201`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_READ_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
202`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
203`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_WRITE_MASK 64'b0000000000000000000000000000000010000000000000000000111111111111
204`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
205`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
206`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
207`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
208`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RMASK 64'b0000000000000000000000000000000010000000000000000000111111111111
209`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111111000000000000
210`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_LD_MASK 64'b0000000000000000000000000000000010000000000000000000111111111111
211`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
212`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_INTERNAL_REG 0
213`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_EXTERNAL_DECODE_REG 0
214`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_ALIASED_FROM 0
215`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_ZERO_TIME_OMNI 0
216`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_JTAG_RD 1
217`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_JTAG_WR 1
218`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_SBUS_RD 1
219`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_SBUS_WR 1
220`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_RAP_RD 1
221`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_HW_ACC_RAP_WR 1
222`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_NUM_FIELDS 11
223`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_FID 0
224`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_SLC 31:31
225`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_WIDTH 1
226`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_INT_SLC 0:0
227`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_POSITION 31
228`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
229`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_HW_LD_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
230`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_POR_VALUE 1'b0
231`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTWE_FIELD_NAME "rstwe"
232`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_FID 1
233`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_SLC 11:9
234`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_WIDTH 3
235`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_INT_SLC 2:0
236`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_POSITION 9
237`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_FMASK 64'b0000000000000000000000000000000000000000000000000000111000000000
238`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111000000000
239`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_POR_VALUE 3'b000
240`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTUNUSED_FIELD_NAME "rstunused"
241`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_FID 2
242`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_SLC 8:8
243`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_WIDTH 1
244`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_INT_SLC 0:0
245`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_POSITION 8
246`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
247`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
248`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_POR_VALUE 1'b0
249`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTERROR_FIELD_NAME "rsterror"
250`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_FID 3
251`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_SLC 7:7
252`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_WIDTH 1
253`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_INT_SLC 0:0
254`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_POSITION 7
255`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
256`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
257`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_POR_VALUE 1'b0
258`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXLINK_FIELD_NAME "rsttxlink"
259`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_FID 4
260`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_SLC 6:6
261`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_WIDTH 1
262`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_INT_SLC 0:0
263`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_POSITION 6
264`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
265`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
266`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_POR_VALUE 1'b0
267`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXLINK_FIELD_NAME "rstrxlink"
268`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_FID 5
269`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_SLC 5:5
270`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_WIDTH 1
271`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_INT_SLC 0:0
272`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_POSITION 5
273`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
274`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
275`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_POR_VALUE 1'b0
276`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTSMLINK_FIELD_NAME "rstsmlink"
277`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_FID 6
278`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_SLC 4:4
279`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_WIDTH 1
280`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_INT_SLC 0:0
281`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_POSITION 4
282`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
283`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
284`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_POR_VALUE 1'b0
285`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTLTSSM_FIELD_NAME "rstltssm"
286`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_FID 7
287`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_SLC 3:3
288`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_WIDTH 1
289`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_INT_SLC 0:0
290`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_POSITION 3
291`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
292`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
293`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_POR_VALUE 1'b0
294`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPHY_FIELD_NAME "rsttxphy"
295`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_FID 8
296`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_SLC 2:2
297`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_WIDTH 1
298`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_INT_SLC 0:0
299`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_POSITION 2
300`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
301`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
302`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_POR_VALUE 1'b0
303`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPHY_FIELD_NAME "rstrxphy"
304`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_FID 9
305`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_SLC 1:1
306`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_WIDTH 1
307`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_INT_SLC 0:0
308`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_POSITION 1
309`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
310`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
311`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_POR_VALUE 1'b0
312`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTTXPCS_FIELD_NAME "rsttxpcs"
313`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_FID 10
314`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_SLC 0:0
315`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_WIDTH 1
316`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_INT_SLC 0:0
317`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_POSITION 0
318`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
319`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
320`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_POR_VALUE 1'b0
321`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RST_RSTRXPCS_FIELD_NAME "rstrxpcs"
322
323//-------------------------------------------------------
324//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT
325//-------------------------------------------------------
326
327`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ADDR 20'b11011100010000000010
328`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_ADDR 30'b000000011011100010000000010000
329`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dbg_stat"
330`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_WIDTH 64
331`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEPTH 1
332`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_SLC 63:0
333`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_INT_SLC 63:0
334`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_POSITION 0
335`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dbg_stat"
336`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_LOW_ADDR_WIDTH 0
337`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_ADDR_RANGE 19:0
338`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
339`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
340`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
341`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
342`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
343`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
344`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
345`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
346`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
347`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
348`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
349`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_INTERNAL_REG 0
350`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_EXTERNAL_DECODE_REG 0
351`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_ALIASED_FROM 0
352`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_ZERO_TIME_OMNI 0
353`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_JTAG_RD 1
354`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_JTAG_WR 1
355`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_SBUS_RD 1
356`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_SBUS_WR 1
357`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_RAP_RD 1
358`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_HW_ACC_RAP_WR 1
359`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_NUM_FIELDS 2
360`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_FID 0
361`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_SLC 15:8
362`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_WIDTH 8
363`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_INT_SLC 7:0
364`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_POSITION 8
365`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_FMASK 64'b0000000000000000000000000000000000000000000000001111111100000000
366`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
367`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_POR_VALUE 8'b00000000
368`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGB_FIELD_NAME "debugb"
369`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_FID 1
370`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_SLC 7:0
371`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_WIDTH 8
372`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_INT_SLC 7:0
373`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_POSITION 0
374`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
375`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
376`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_POR_VALUE 8'b00000000
377`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_STAT_DEBUGA_FIELD_NAME "debuga"
378
379//-------------------------------------------------------
380//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG
381//-------------------------------------------------------
382
383`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ADDR 20'b11011100010000000011
384`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_ADDR 30'b000000011011100010000000011000
385`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dbg_config"
386`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_WIDTH 64
387`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DEPTH 1
388`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_SLC 63:0
389`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_INT_SLC 63:0
390`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_POSITION 0
391`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dbg_config"
392`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_LOW_ADDR_WIDTH 0
393`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_ADDR_RANGE 19:0
394`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
395`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
396`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
397`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
398`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
399`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
400`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
401`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
402`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
403`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
404`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
405`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_INTERNAL_REG 0
406`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_EXTERNAL_DECODE_REG 0
407`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_ALIASED_FROM 0
408`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_ZERO_TIME_OMNI 0
409`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_JTAG_RD 1
410`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_JTAG_WR 1
411`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_SBUS_RD 1
412`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_SBUS_WR 1
413`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_RAP_RD 1
414`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_HW_ACC_RAP_WR 1
415`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_NUM_FIELDS 4
416`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_FID 0
417`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_SLC 31:24
418`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_WIDTH 8
419`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_INT_SLC 7:0
420`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_POSITION 24
421`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_FMASK 64'b0000000000000000000000000000000011111111000000000000000000000000
422`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
423`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_POR_VALUE 8'b00000000
424`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_BLK_SEL_FIELD_NAME "dbugb_blk_sel"
425`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_FID 1
426`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_SLC 23:16
427`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_WIDTH 8
428`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_INT_SLC 7:0
429`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_POSITION 16
430`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_FMASK 64'b0000000000000000000000000000000000000000111111110000000000000000
431`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
432`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_POR_VALUE 8'b00000000
433`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGB_SIG_SEL_FIELD_NAME "dbugb_sig_sel"
434`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_FID 2
435`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_SLC 15:8
436`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_WIDTH 8
437`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_INT_SLC 7:0
438`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_POSITION 8
439`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_FMASK 64'b0000000000000000000000000000000000000000000000001111111100000000
440`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
441`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_POR_VALUE 8'b00000000
442`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_BLK_SEL_FIELD_NAME "dbuga_blk_sel"
443`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_FID 3
444`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_SLC 7:0
445`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_WIDTH 8
446`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_INT_SLC 7:0
447`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_POSITION 0
448`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
449`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
450`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_POR_VALUE 8'b00000000
451`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DBG_CONFIG_DBUGA_SIG_SEL_FIELD_NAME "dbuga_sig_sel"
452
453//-------------------------------------------------------
454//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL
455//-------------------------------------------------------
456
457`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ADDR 20'b11011100010000000100
458`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_ADDR 30'b000000011011100010000000100000
459`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_cntl"
460`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WIDTH 64
461`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DEPTH 1
462`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_SLC 63:0
463`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_INT_SLC 63:0
464`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_POSITION 0
465`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_cntl"
466`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LOW_ADDR_WIDTH 0
467`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_ADDR_RANGE 19:0
468`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_READ_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
469`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
470`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WRITE_MASK 64'b0000000000000000000000000000000010000000000000000000001011111000
471`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
472`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000110100000111
473`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
474`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
475`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RMASK 64'b0000000000000000000000000000000010000000000000000000111111111111
476`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111111000000000000
477`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
478`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
479`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_INTERNAL_REG 0
480`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_EXTERNAL_DECODE_REG 0
481`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_ALIASED_FROM 0
482`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_ZERO_TIME_OMNI 0
483`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_JTAG_RD 1
484`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_JTAG_WR 1
485`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_SBUS_RD 1
486`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_SBUS_WR 1
487`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_RAP_RD 1
488`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HW_ACC_RAP_WR 1
489`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_NUM_FIELDS 10
490`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_FID 0
491`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_SLC 31:31
492`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_WIDTH 1
493`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_INT_SLC 0:0
494`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_POSITION 31
495`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
496`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
497`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_POR_VALUE 1'b0
498`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_WR_ENABLE_FIELD_NAME "wr_enable"
499`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_FID 1
500`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_SLC 11:11
501`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_WIDTH 1
502`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_INT_SLC 0:0
503`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_POSITION 11
504`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
505`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000100000000000
506`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_POR_VALUE 1'b0
507`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_RCOVER_TO_CONFIG_FIELD_NAME "rcover_to_config"
508`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_FID 2
509`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_SLC 10:10
510`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_WIDTH 1
511`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_INT_SLC 0:0
512`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_POSITION 10
513`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
514`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
515`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_POR_VALUE 1'b0
516`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LO_TO_RECOVER_FIELD_NAME "lo_to_recover"
517`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_FID 3
518`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_SLC 9:9
519`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_WIDTH 1
520`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_INT_SLC 0:0
521`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_POSITION 9
522`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
523`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
524`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_POR_VALUE 1'b0
525`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_0_FIELD_NAME "unused_0"
526`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_FID 4
527`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_SLC 8:8
528`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_WIDTH 1
529`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_INT_SLC 0:0
530`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_POSITION 8
531`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
532`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
533`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_POR_VALUE 1'b0
534`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_GO_TO_DETECT_FIELD_NAME "go_to_detect"
535`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_FID 5
536`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_SLC 7:4
537`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_WIDTH 4
538`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_INT_SLC 3:0
539`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_POSITION 4
540`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_FMASK 64'b0000000000000000000000000000000000000000000000000000000011110000
541`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000011110000
542`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_POR_VALUE 4'b0000
543`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_UNUSED_1_FIELD_NAME "unused_1"
544`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_FID 6
545`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_SLC 3:3
546`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_WIDTH 1
547`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_INT_SLC 0:0
548`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_POSITION 3
549`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
550`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
551`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_POR_VALUE 1'b0
552`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_DISABLE_SCRAMBLING_FIELD_NAME "disable_scrambling"
553`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_FID 7
554`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_SLC 2:2
555`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_WIDTH 1
556`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_INT_SLC 0:0
557`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_POSITION 2
558`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
559`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
560`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_POR_VALUE 1'b0
561`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_LOOPBK_REQ_FIELD_NAME "link_loopbk_req"
562`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_FID 8
563`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_SLC 1:1
564`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_WIDTH 1
565`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_INT_SLC 0:0
566`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_POSITION 1
567`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
568`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
569`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_POR_VALUE 1'b0
570`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_FIELD_NAME "link_disable_req"
571`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_FID 9
572`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_SLC 0:0
573`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_WIDTH 1
574`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_INT_SLC 0:0
575`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_POSITION 0
576`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
577`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
578`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_POR_VALUE 1'b0
579`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_FIELD_NAME "hot_reset"
580
581//-------------------------------------------------------
582//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS
583//-------------------------------------------------------
584
585`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ADDR 20'b11011100010000000101
586`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_ADDR 30'b000000011011100010000000101000
587`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_status"
588`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_WIDTH 64
589`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_DEPTH 1
590`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLC 63:0
591`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_INT_SLC 63:0
592`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_POSITION 0
593`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_status"
594`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LOW_ADDR_WIDTH 0
595`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_ADDR_RANGE 19:0
596`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_READ_MASK 64'b0000000000000000000000000000000000000000000000000001111111111111
597`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000001111111111111
598`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
599`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
600`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
601`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
602`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
603`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_RMASK 64'b0000000000000000000000000000000000000000000000000001111111111111
604`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111110000000000000
605`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001111111111111
606`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000010000001
607`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_INTERNAL_REG 0
608`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_EXTERNAL_DECODE_REG 0
609`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_ALIASED_FROM 0
610`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_ZERO_TIME_OMNI 0
611`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_JTAG_RD 1
612`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_JTAG_WR 1
613`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_SBUS_RD 1
614`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_SBUS_WR 1
615`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_RAP_RD 1
616`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_HW_ACC_RAP_WR 1
617`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NUM_FIELDS 5
618`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_FID 0
619`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_SLC 12:12
620`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_WIDTH 1
621`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_INT_SLC 0:0
622`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_POSITION 12
623`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
624`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001000000000000
625`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_POR_VALUE 1'b0
626`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_SLOT_CLK_CONFG_PIN_FIELD_NAME "slot_clk_confg_pin"
627`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_FID 1
628`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_SLC 11:11
629`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_WIDTH 1
630`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_INT_SLC 0:0
631`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_POSITION 11
632`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
633`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000100000000000
634`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_POR_VALUE 1'b0
635`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_FIELD_NAME "link_training"
636`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_FID 2
637`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_SLC 10:10
638`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_WIDTH 1
639`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_INT_SLC 0:0
640`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_POSITION 10
641`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
642`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
643`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_POR_VALUE 1'b0
644`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_TRAINING_ERR_FIELD_NAME "link_training_err"
645`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_FID 3
646`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_SLC 9:4
647`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_WIDTH 6
648`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_INT_SLC 5:0
649`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_POSITION 4
650`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_FMASK 64'b0000000000000000000000000000000000000000000000000000001111110000
651`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001111110000
652`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_POR_VALUE 6'b001000
653`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_NEGOTIATED_WIDTH_FIELD_NAME "negotiated_width"
654`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_FID 4
655`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_SLC 3:0
656`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_WIDTH 4
657`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_INT_SLC 3:0
658`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_POSITION 0
659`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001111
660`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111
661`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_POR_VALUE 4'b0001
662`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_STATUS_LINK_SPEED_FIELD_NAME "link_speed"
663
664//-------------------------------------------------------
665//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS
666//-------------------------------------------------------
667
668`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ADDR 20'b11011100010000001000
669`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_ADDR 30'b000000011011100010000001000000
670`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_interrupt_status"
671`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_WIDTH 64
672`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_DEPTH 1
673`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_SLC 63:0
674`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_SLC 63:0
675`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_POSITION 0
676`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_interrupt_status"
677`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_LOW_ADDR_WIDTH 0
678`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_ADDR_RANGE 19:0
679`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_READ_MASK 64'b0000000000000000000000000000000010000000000000000000000011111111
680`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_READ_ONLY_MASK 64'b0000000000000000000000000000000010000000000000000000000011111111
681`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
682`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
683`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
684`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
685`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
686`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_RMASK 64'b0000000000000000000000000000000010000000000000000000000011111111
687`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111111111100000000
688`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_LD_MASK 64'b0000000000000000000000000000000010000000000000000000000011111111
689`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
690`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERNAL_REG 0
691`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_EXTERNAL_DECODE_REG 0
692`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_ALIASED_FROM 0
693`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_ZERO_TIME_OMNI 0
694`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_JTAG_RD 1
695`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_JTAG_WR 1
696`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_SBUS_RD 1
697`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_SBUS_WR 1
698`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_RAP_RD 1
699`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_HW_ACC_RAP_WR 1
700`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_NUM_FIELDS 9
701`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_FID 0
702`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_SLC 31:31
703`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_WIDTH 1
704`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_INT_SLC 0:0
705`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_POSITION 31
706`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
707`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_HW_LD_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
708`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_POR_VALUE 1'b0
709`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INTERRUPT_FIELD_NAME "interrupt"
710`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_FID 1
711`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_SLC 7:7
712`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_WIDTH 1
713`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_INT_SLC 0:0
714`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_POSITION 7
715`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
716`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
717`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_POR_VALUE 1'b0
718`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_2_OVFLW_FIELD_NAME "int_perf_cntr_2_ovflw"
719`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_FID 2
720`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_SLC 6:6
721`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_WIDTH 1
722`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_INT_SLC 0:0
723`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_POSITION 6
724`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
725`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
726`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_POR_VALUE 1'b0
727`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PERF_CNTR_1_OVFLW_FIELD_NAME "int_perf_cntr_1_ovflw"
728`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_FID 3
729`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_SLC 5:5
730`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_WIDTH 1
731`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_INT_SLC 0:0
732`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_POSITION 5
733`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
734`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
735`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_POR_VALUE 1'b0
736`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LINK_LAYER_FIELD_NAME "int_link_layer"
737`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_FID 4
738`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_SLC 4:4
739`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_WIDTH 1
740`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_INT_SLC 0:0
741`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_POSITION 4
742`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
743`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
744`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_POR_VALUE 1'b0
745`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_ERROR_FIELD_NAME "int_phy_error"
746`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_FID 5
747`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_SLC 3:3
748`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_WIDTH 1
749`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_INT_SLC 0:0
750`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_POSITION 3
751`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
752`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
753`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_POR_VALUE 1'b0
754`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_LTSSM_FIELD_NAME "int_ltssm"
755`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_FID 6
756`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_SLC 2:2
757`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_WIDTH 1
758`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_INT_SLC 0:0
759`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_POSITION 2
760`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
761`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
762`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_POR_VALUE 1'b0
763`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_TX_FIELD_NAME "int_phy_tx"
764`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_FID 7
765`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_SLC 1:1
766`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_WIDTH 1
767`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_INT_SLC 0:0
768`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_POSITION 1
769`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
770`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
771`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_POR_VALUE 1'b0
772`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_RX_FIELD_NAME "int_phy_rx"
773`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_FID 8
774`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_SLC 0:0
775`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_WIDTH 1
776`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_INT_SLC 0:0
777`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_POSITION 0
778`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
779`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
780`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_POR_VALUE 1'b0
781`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_STATUS_INT_PHY_GB_FIELD_NAME "int_phy_gb"
782
783//-------------------------------------------------------
784//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK
785//-------------------------------------------------------
786
787`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ADDR 20'b11011100010000001001
788`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_ADDR 30'b000000011011100010000001001000
789`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_interrupt_mask"
790`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_WIDTH 64
791`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_DEPTH 1
792`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_SLC 63:0
793`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_INT_SLC 63:0
794`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_POSITION 0
795`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_interrupt_mask"
796`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_LOW_ADDR_WIDTH 0
797`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_ADDR_RANGE 19:0
798`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_READ_MASK 64'b0000000000000000000000000000000010000000000000000000000011111111
799`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
800`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_WRITE_MASK 64'b0000000000000000000000000000000010000000000000000000000011111111
801`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
802`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
803`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
804`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
805`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_RMASK 64'b0000000000000000000000000000000010000000000000000000000011111111
806`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111111111100000000
807`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
808`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
809`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_INTERNAL_REG 0
810`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_EXTERNAL_DECODE_REG 0
811`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_ALIASED_FROM 0
812`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_ZERO_TIME_OMNI 0
813`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_JTAG_RD 1
814`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_JTAG_WR 1
815`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_SBUS_RD 1
816`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_SBUS_WR 1
817`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_RAP_RD 1
818`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_HW_ACC_RAP_WR 1
819`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_NUM_FIELDS 9
820`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_FID 0
821`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_SLC 31:31
822`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_WIDTH 1
823`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_INT_SLC 0:0
824`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_POSITION 31
825`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
826`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
827`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_POR_VALUE 1'b0
828`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_INTERRUPT_EN_FIELD_NAME "msk_interrupt_en"
829`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_FID 1
830`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_SLC 7:7
831`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_WIDTH 1
832`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_INT_SLC 0:0
833`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_POSITION 7
834`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
835`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
836`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_POR_VALUE 1'b0
837`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_2_OVFLW_FIELD_NAME "msk_perf_cntr_2_ovflw"
838`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_FID 2
839`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_SLC 6:6
840`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_WIDTH 1
841`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_INT_SLC 0:0
842`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_POSITION 6
843`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
844`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
845`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_POR_VALUE 1'b0
846`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PERF_CNTR_1_OVFLW_FIELD_NAME "msk_perf_cntr_1_ovflw"
847`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_FID 3
848`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_SLC 5:5
849`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_WIDTH 1
850`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_INT_SLC 0:0
851`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_POSITION 5
852`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
853`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
854`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_POR_VALUE 1'b0
855`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LINK_LAYER_FIELD_NAME "msk_link_layer"
856`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_FID 4
857`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_SLC 4:4
858`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_WIDTH 1
859`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_INT_SLC 0:0
860`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_POSITION 4
861`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
862`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
863`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_POR_VALUE 1'b0
864`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_ERROR_FIELD_NAME "msk_phy_error"
865`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_FID 5
866`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_SLC 3:3
867`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_WIDTH 1
868`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_INT_SLC 0:0
869`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_POSITION 3
870`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
871`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
872`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_POR_VALUE 1'b0
873`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_LTSSM_FIELD_NAME "msk_ltssm"
874`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_FID 6
875`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_SLC 2:2
876`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_WIDTH 1
877`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_INT_SLC 0:0
878`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_POSITION 2
879`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
880`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
881`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_POR_VALUE 1'b0
882`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_TX_FIELD_NAME "msk_phy_tx"
883`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_FID 7
884`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_SLC 1:1
885`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_WIDTH 1
886`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_INT_SLC 0:0
887`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_POSITION 1
888`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
889`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
890`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_POR_VALUE 1'b0
891`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_RX_FIELD_NAME "msk_phy_rx"
892`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_FID 8
893`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_SLC 0:0
894`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_WIDTH 1
895`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_INT_SLC 0:0
896`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_POSITION 0
897`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
898`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
899`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_POR_VALUE 1'b0
900`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_INTERRUPT_MASK_MSK_PHY_GB_FIELD_NAME "msk_phy_gb"
901
902//-------------------------------------------------------
903//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL
904//-------------------------------------------------------
905
906`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ADDR 20'b11011100010000100000
907`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_ADDR 30'b000000011011100010000100000000
908`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1_sel"
909`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_WIDTH 64
910`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_DEPTH 1
911`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_SLC 63:0
912`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_INT_SLC 63:0
913`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_POSITION 0
914`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1_sel"
915`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_LOW_ADDR_WIDTH 0
916`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_ADDR_RANGE 19:0
917`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
918`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
919`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
920`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
921`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
922`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
923`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
924`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
925`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
926`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
927`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
928`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_INTERNAL_REG 0
929`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_EXTERNAL_DECODE_REG 0
930`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_ALIASED_FROM 0
931`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_ZERO_TIME_OMNI 0
932`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_JTAG_RD 1
933`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_JTAG_WR 1
934`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_SBUS_RD 1
935`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_SBUS_WR 1
936`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_RAP_RD 1
937`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_HW_ACC_RAP_WR 1
938`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_NUM_FIELDS 2
939`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_FID 0
940`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_SLC 31:16
941`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_WIDTH 16
942`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_INT_SLC 15:0
943`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_POSITION 16
944`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
945`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
946`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_POR_VALUE 16'b0000000000000000
947`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR2_SELECT_FIELD_NAME "perf_cntr2_select"
948`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_FID 1
949`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_SLC 15:0
950`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_WIDTH 16
951`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_INT_SLC 15:0
952`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_POSITION 0
953`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
954`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
955`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_POR_VALUE 16'b0000000000000000
956`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SEL_PERF_CNTR1_SELECT_FIELD_NAME "perf_cntr1_select"
957
958//-------------------------------------------------------
959//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL
960//-------------------------------------------------------
961
962`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ADDR 20'b11011100010000100010
963`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_ADDR 30'b000000011011100010000100010000
964`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr_ctl"
965`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_WIDTH 64
966`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_DEPTH 1
967`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SLC 63:0
968`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_INT_SLC 63:0
969`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_POSITION 0
970`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr_ctl"
971`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_LOW_ADDR_WIDTH 0
972`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_ADDR_RANGE 19:0
973`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000001101111
974`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
975`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
976`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
977`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000001100000
978`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111
979`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
980`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RMASK 64'b0000000000000000000000000000000000000000000000000000000001101111
981`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111110010000
982`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001101111
983`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
984`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_INTERNAL_REG 0
985`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_EXTERNAL_DECODE_REG 0
986`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_ALIASED_FROM 0
987`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_ZERO_TIME_OMNI 0
988`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_JTAG_RD 1
989`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_JTAG_WR 1
990`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_SBUS_RD 1
991`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_SBUS_WR 1
992`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_RAP_RD 1
993`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_HW_ACC_RAP_WR 1
994`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_NUM_FIELDS 6
995`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_FID 0
996`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_SLC 6:6
997`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_WIDTH 1
998`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_INT_SLC 0:0
999`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_POSITION 6
1000`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
1001`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
1002`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_POR_VALUE 1'b0
1003`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR2_OVERFLOW_FIELD_NAME "set_perf_cntr2_overflow"
1004`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_FID 1
1005`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_SLC 5:5
1006`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_WIDTH 1
1007`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_INT_SLC 0:0
1008`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_POSITION 5
1009`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
1010`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
1011`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_POR_VALUE 1'b0
1012`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_SET_PERF_CNTR1_OVERFLOW_FIELD_NAME "set_perf_cntr1_overflow"
1013`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_FID 2
1014`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_SLC 3:3
1015`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_WIDTH 1
1016`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_INT_SLC 0:0
1017`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_POSITION 3
1018`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
1019`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
1020`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_POR_VALUE 1'b0
1021`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_OVERFLOW_FIELD_NAME "rst_perf_cntr2_overflow"
1022`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_FID 3
1023`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_SLC 2:2
1024`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_WIDTH 1
1025`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_INT_SLC 0:0
1026`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_POSITION 2
1027`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1028`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1029`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_POR_VALUE 1'b0
1030`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR2_FIELD_NAME "rst_perf_cntr2"
1031`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_FID 4
1032`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_SLC 1:1
1033`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_WIDTH 1
1034`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_INT_SLC 0:0
1035`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_POSITION 1
1036`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1037`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1038`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_POR_VALUE 1'b0
1039`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_OVERFLOW_FIELD_NAME "rst_perf_cntr1_overflow"
1040`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_FID 5
1041`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_SLC 0:0
1042`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_WIDTH 1
1043`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_INT_SLC 0:0
1044`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_POSITION 0
1045`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1046`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1047`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_POR_VALUE 1'b0
1048`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR_CTL_RST_PERF_CNTR1_FIELD_NAME "rst_perf_cntr1"
1049
1050//-------------------------------------------------------
1051//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1
1052//-------------------------------------------------------
1053
1054`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ADDR 20'b11011100010000100100
1055`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_ADDR 30'b000000011011100010000100100000
1056`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1"
1057`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_WIDTH 64
1058`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_DEPTH 1
1059`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SLC 63:0
1060`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_INT_SLC 63:0
1061`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_POSITION 0
1062`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1"
1063`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_LOW_ADDR_WIDTH 0
1064`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_ADDR_RANGE 19:0
1065`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1066`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_READ_ONLY_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1067`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1068`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1069`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1070`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1071`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1072`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1073`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
1074`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1075`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1076`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_INTERNAL_REG 0
1077`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_EXTERNAL_DECODE_REG 0
1078`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_ALIASED_FROM 0
1079`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_ZERO_TIME_OMNI 0
1080`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_JTAG_RD 1
1081`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_JTAG_WR 1
1082`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_SBUS_RD 1
1083`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_SBUS_WR 1
1084`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_RAP_RD 1
1085`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_HW_ACC_RAP_WR 1
1086`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_NUM_FIELDS 1
1087`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_FID 0
1088`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_SLC 31:0
1089`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_WIDTH 32
1090`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_INT_SLC 31:0
1091`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_POSITION 0
1092`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1093`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1094`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_POR_VALUE 32'b00000000000000000000000000000000
1095`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_PERF_CNTR1_FIELD_NAME "perf_cntr1"
1096
1097//-------------------------------------------------------
1098//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST
1099//-------------------------------------------------------
1100
1101`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ADDR 20'b11011100010000100101
1102`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_ADDR 30'b000000011011100010000100101000
1103`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1_test"
1104`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_WIDTH 64
1105`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_DEPTH 1
1106`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_SLC 63:0
1107`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_INT_SLC 63:0
1108`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_POSITION 0
1109`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr1_test"
1110`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_LOW_ADDR_WIDTH 0
1111`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_ADDR_RANGE 19:0
1112`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1113`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1114`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1115`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1116`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1117`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1118`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1119`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1120`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
1121`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1122`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1123`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_INTERNAL_REG 0
1124`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_EXTERNAL_DECODE_REG 0
1125`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_ALIASED_FROM 0
1126`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_ZERO_TIME_OMNI 0
1127`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_JTAG_RD 1
1128`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_JTAG_WR 1
1129`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_SBUS_RD 1
1130`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_SBUS_WR 1
1131`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_RAP_RD 1
1132`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_HW_ACC_RAP_WR 1
1133`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_NUM_FIELDS 1
1134`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_FID 0
1135`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_SLC 31:0
1136`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_WIDTH 32
1137`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_INT_SLC 31:0
1138`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_POSITION 0
1139`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1140`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1141`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_POR_VALUE 32'b00000000000000000000000000000000
1142`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR1_TEST_PERF_CNTR1_TEST_FIELD_NAME "perf_cntr1_test"
1143
1144//-------------------------------------------------------
1145//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2
1146//-------------------------------------------------------
1147
1148`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ADDR 20'b11011100010000100110
1149`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_ADDR 30'b000000011011100010000100110000
1150`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr2"
1151`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_WIDTH 64
1152`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_DEPTH 1
1153`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_SLC 63:0
1154`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_INT_SLC 63:0
1155`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_POSITION 0
1156`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr2"
1157`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_LOW_ADDR_WIDTH 0
1158`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_ADDR_RANGE 19:0
1159`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1160`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_READ_ONLY_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1161`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1162`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1163`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1164`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1165`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1166`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1167`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
1168`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1169`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1170`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_INTERNAL_REG 0
1171`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_EXTERNAL_DECODE_REG 0
1172`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_ALIASED_FROM 0
1173`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_ZERO_TIME_OMNI 0
1174`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_JTAG_RD 1
1175`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_JTAG_WR 1
1176`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_SBUS_RD 1
1177`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_SBUS_WR 1
1178`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_RAP_RD 1
1179`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_HW_ACC_RAP_WR 1
1180`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_NUM_FIELDS 1
1181`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_FID 0
1182`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_SLC 31:0
1183`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_WIDTH 32
1184`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_INT_SLC 31:0
1185`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_POSITION 0
1186`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1187`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1188`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_POR_VALUE 32'b00000000000000000000000000000000
1189`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_PERF_CNTR2_FIELD_NAME "perf_cntr2"
1190
1191//-------------------------------------------------------
1192//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST
1193//-------------------------------------------------------
1194
1195`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ADDR 20'b11011100010000100111
1196`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_ADDR 30'b000000011011100010000100111000
1197`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr2_test"
1198`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_WIDTH 64
1199`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_DEPTH 1
1200`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_SLC 63:0
1201`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_INT_SLC 63:0
1202`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_POSITION 0
1203`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_link_perf_cntr2_test"
1204`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_LOW_ADDR_WIDTH 0
1205`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_ADDR_RANGE 19:0
1206`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1207`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1208`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1209`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1210`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1211`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1212`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1213`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1214`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
1215`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1216`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1217`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_INTERNAL_REG 0
1218`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_EXTERNAL_DECODE_REG 0
1219`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_ALIASED_FROM 0
1220`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_ZERO_TIME_OMNI 0
1221`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_JTAG_RD 1
1222`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_JTAG_WR 1
1223`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_SBUS_RD 1
1224`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_SBUS_WR 1
1225`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_RAP_RD 1
1226`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_HW_ACC_RAP_WR 1
1227`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_NUM_FIELDS 1
1228`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_FID 0
1229`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_SLC 31:0
1230`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_WIDTH 32
1231`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_INT_SLC 31:0
1232`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_POSITION 0
1233`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1234`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
1235`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_POR_VALUE 32'b00000000000000000000000000000000
1236`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LINK_PERF_CNTR2_TEST_PERF_CNTR2_TEST_FIELD_NAME "perf_cntr2_test"
1237
1238//-------------------------------------------------------
1239//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG
1240//-------------------------------------------------------
1241
1242`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ADDR 20'b11011100010001000000
1243`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_ADDR 30'b000000011011100010001000000000
1244`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_config"
1245`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_WIDTH 64
1246`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_DEPTH 1
1247`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_SLC 63:0
1248`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_INT_SLC 63:0
1249`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_POSITION 0
1250`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_config"
1251`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_LOW_ADDR_WIDTH 0
1252`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_ADDR_RANGE 19:0
1253`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000111101110
1254`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1255`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000111101110
1256`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1257`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1258`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1259`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1260`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RMASK 64'b0000000000000000000000000000000000000000000000000000000111101110
1261`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111000010001
1262`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1263`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000100000000
1264`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_INTERNAL_REG 0
1265`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_EXTERNAL_DECODE_REG 0
1266`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_ALIASED_FROM 0
1267`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_ZERO_TIME_OMNI 0
1268`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_JTAG_RD 1
1269`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_JTAG_WR 1
1270`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_SBUS_RD 1
1271`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_SBUS_WR 1
1272`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_RAP_RD 1
1273`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_HW_ACC_RAP_WR 1
1274`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_NUM_FIELDS 5
1275`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_FID 0
1276`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_SLC 8:8
1277`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_WIDTH 1
1278`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_INT_SLC 0:0
1279`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_POSITION 8
1280`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
1281`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1282`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_POR_VALUE 1'b1
1283`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_VC0_EN_FIELD_NAME "vc0_en"
1284`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_FID 1
1285`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_SLC 7:5
1286`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_WIDTH 3
1287`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_INT_SLC 2:0
1288`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_POSITION 5
1289`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_FMASK 64'b0000000000000000000000000000000000000000000000000000000011100000
1290`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1291`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_POR_VALUE 3'b000
1292`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_MAX_PAYLOAD_FIELD_NAME "max_payload"
1293`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_FID 2
1294`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_SLC 3:3
1295`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_WIDTH 1
1296`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_INT_SLC 0:0
1297`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_POSITION 3
1298`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
1299`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1300`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_POR_VALUE 1'b0
1301`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_TLP_XMIT_FC_EN_FIELD_NAME "tlp_xmit_fc_en"
1302`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_FID 3
1303`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_SLC 2:2
1304`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_WIDTH 1
1305`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_INT_SLC 0:0
1306`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_POSITION 2
1307`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1308`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1309`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_POR_VALUE 1'b0
1310`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_FREQ_ACK_ENABLE_FIELD_NAME "freq_ack_enable"
1311`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_FID 4
1312`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_SLC 1:1
1313`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_WIDTH 1
1314`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_INT_SLC 0:0
1315`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_POSITION 1
1316`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1317`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1318`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_POR_VALUE 1'b0
1319`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_CONFIG_RETRY_DISABLE_FIELD_NAME "retry_disable"
1320
1321//-------------------------------------------------------
1322//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT
1323//-------------------------------------------------------
1324
1325`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ADDR 20'b11011100010001000001
1326`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_ADDR 30'b000000011011100010001000001000
1327`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_stat"
1328`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_WIDTH 64
1329`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DEPTH 1
1330`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_SLC 63:0
1331`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INT_SLC 63:0
1332`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_POSITION 0
1333`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_stat"
1334`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LOW_ADDR_WIDTH 0
1335`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_ADDR_RANGE 19:0
1336`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000111111
1337`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1338`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000001100111111
1339`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000001100000000
1340`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1341`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1342`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1343`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_RMASK 64'b0000000000000000000000000000000000000000000000000000001100111111
1344`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111110011000000
1345`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001100111111
1346`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000001
1347`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INTERNAL_REG 0
1348`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_EXTERNAL_DECODE_REG 0
1349`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_ALIASED_FROM 0
1350`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_ZERO_TIME_OMNI 0
1351`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_JTAG_RD 1
1352`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_JTAG_WR 1
1353`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_SBUS_RD 1
1354`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_SBUS_WR 1
1355`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_RAP_RD 1
1356`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_HW_ACC_RAP_WR 1
1357`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_NUM_FIELDS 5
1358`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_FID 0
1359`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_SLC 9:9
1360`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_WIDTH 1
1361`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_INT_SLC 0:0
1362`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_POSITION 9
1363`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
1364`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
1365`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_POR_VALUE 1'b0
1366`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_WE_FIELD_NAME "init_fc_sm_we"
1367`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_FID 1
1368`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_SLC 8:8
1369`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_WIDTH 1
1370`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_INT_SLC 0:0
1371`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_POSITION 8
1372`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
1373`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
1374`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_POR_VALUE 1'b0
1375`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_ST_DLUP_WE_FIELD_NAME "lnk_st_dlup_we"
1376`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_FID 2
1377`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_SLC 5:4
1378`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_WIDTH 2
1379`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_INT_SLC 1:0
1380`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_POSITION 4
1381`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000110000
1382`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000110000
1383`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_POR_VALUE 2'b00
1384`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_INIT_FC_SM_STS_FIELD_NAME "init_fc_sm_sts"
1385`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_FID 3
1386`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_SLC 3:3
1387`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_WIDTH 1
1388`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_INT_SLC 0:0
1389`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_POSITION 3
1390`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
1391`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
1392`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_POR_VALUE 1'b0
1393`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_DLUP_STS_FIELD_NAME "dlup_sts"
1394`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_FID 4
1395`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_SLC 2:0
1396`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_WIDTH 3
1397`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_INT_SLC 2:0
1398`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_POSITION 0
1399`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000111
1400`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000111
1401`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_POR_VALUE 3'b001
1402`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_STAT_LNK_STATE_MACH_STS_FIELD_NAME "lnk_state_mach_sts"
1403
1404//-------------------------------------------------------
1405//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT
1406//-------------------------------------------------------
1407
1408`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ADDR 20'b11011100010001000010
1409`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_ADDR 30'b000000011011100010001000010000
1410`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_int"
1411`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_WIDTH 64
1412`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_DEPTH 1
1413`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_SLC 63:0
1414`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SLC 63:0
1415`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_POSITION 0
1416`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_int"
1417`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_LOW_ADDR_WIDTH 0
1418`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_ADDR_RANGE 19:0
1419`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_READ_MASK 64'b0000000000000000000000000000000010000000011101110000001111110111
1420`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_READ_ONLY_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
1421`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1422`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1423`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1424`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_CLEAR_MASK 64'b0000000000000000000000000000000000000000011101110000001111110111
1425`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1426`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_RMASK 64'b0000000000000000000000000000000010000000011101110000001111110111
1427`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111100010001111110000001000
1428`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000011101110000001111110111
1429`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1430`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INTERNAL_REG 0
1431`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_EXTERNAL_DECODE_REG 0
1432`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_ALIASED_FROM 0
1433`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_ZERO_TIME_OMNI 0
1434`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_JTAG_RD 1
1435`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_JTAG_WR 1
1436`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_SBUS_RD 1
1437`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_SBUS_WR 1
1438`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_RAP_RD 1
1439`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_HW_ACC_RAP_WR 1
1440`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_NUM_FIELDS 16
1441`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_FID 0
1442`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_SLC 31:31
1443`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_WIDTH 1
1444`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_INT_SLC 0:0
1445`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_POSITION 31
1446`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
1447`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1448`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_POR_VALUE 1'b0
1449`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_LINK_ERR_ACT_FIELD_NAME "int_link_err_act"
1450`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_FID 1
1451`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_SLC 22:22
1452`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_WIDTH 1
1453`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_INT_SLC 0:0
1454`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_POSITION 22
1455`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_FMASK 64'b0000000000000000000000000000000000000000010000000000000000000000
1456`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000010000000000000000000000
1457`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_POR_VALUE 1'b0
1458`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_UNSPRTD_DLLP_FIELD_NAME "int_unsprtd_dllp"
1459`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_FID 2
1460`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_SLC 21:21
1461`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_WIDTH 1
1462`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_INT_SLC 0:0
1463`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_POSITION 21
1464`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_FMASK 64'b0000000000000000000000000000000000000000001000000000000000000000
1465`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000001000000000000000000000
1466`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_POR_VALUE 1'b0
1467`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLLP_RCV_ERR_FIELD_NAME "int_dllp_rcv_err"
1468`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_FID 3
1469`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_SLC 20:20
1470`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_WIDTH 1
1471`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_INT_SLC 0:0
1472`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_POSITION 20
1473`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_FMASK 64'b0000000000000000000000000000000000000000000100000000000000000000
1474`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000100000000000000000000
1475`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_POR_VALUE 1'b0
1476`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_DLLP_FIELD_NAME "int_bad_dllp"
1477`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_FID 4
1478`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_SLC 18:18
1479`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_WIDTH 1
1480`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_INT_SLC 0:0
1481`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_POSITION 18
1482`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_FMASK 64'b0000000000000000000000000000000000000000000001000000000000000000
1483`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000001000000000000000000
1484`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_POR_VALUE 1'b0
1485`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_TLP_RCV_ERR_FIELD_NAME "int_tlp_rcv_err"
1486`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_FID 5
1487`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_SLC 17:17
1488`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_WIDTH 1
1489`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_INT_SLC 0:0
1490`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_POSITION 17
1491`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_FMASK 64'b0000000000000000000000000000000000000000000000100000000000000000
1492`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000100000000000000000
1493`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_POR_VALUE 1'b0
1494`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_SRC_ERR_TLP_FIELD_NAME "int_src_err_tlp"
1495`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_FID 6
1496`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_SLC 16:16
1497`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_WIDTH 1
1498`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_INT_SLC 0:0
1499`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_POSITION 16
1500`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_FMASK 64'b0000000000000000000000000000000000000000000000010000000000000000
1501`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000010000000000000000
1502`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_POR_VALUE 1'b0
1503`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_BAD_TLP_FIELD_NAME "int_bad_tlp"
1504`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_FID 7
1505`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_SLC 9:9
1506`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_WIDTH 1
1507`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_INT_SLC 0:0
1508`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_POSITION 9
1509`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
1510`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
1511`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_POR_VALUE 1'b0
1512`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_UDF_ERR_FIELD_NAME "int_rtry_buf_udf_err"
1513`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_FID 8
1514`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_SLC 8:8
1515`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_WIDTH 1
1516`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_INT_SLC 0:0
1517`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_POSITION 8
1518`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
1519`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
1520`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_POR_VALUE 1'b0
1521`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_OVF_ERR_FIELD_NAME "int_rtry_buf_ovf_err"
1522`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_FID 9
1523`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_SLC 7:7
1524`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_WIDTH 1
1525`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_INT_SLC 0:0
1526`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_POSITION 7
1527`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
1528`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
1529`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_POR_VALUE 1'b0
1530`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TLP_MIN_ERR_FIELD_NAME "int_eg_tlp_min_err"
1531`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_FID 10
1532`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_SLC 6:6
1533`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_WIDTH 1
1534`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_INT_SLC 0:0
1535`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_POSITION 6
1536`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
1537`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
1538`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_POR_VALUE 1'b0
1539`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EG_TRNC_FRM_ERR_FIELD_NAME "int_eg_trnc_frm_err"
1540`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_FID 11
1541`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_SLC 5:5
1542`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_WIDTH 1
1543`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_INT_SLC 0:0
1544`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_POSITION 5
1545`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
1546`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
1547`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_POR_VALUE 1'b0
1548`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RTRY_BUF_PE_FIELD_NAME "int_rtry_buf_pe"
1549`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_FID 12
1550`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_SLC 4:4
1551`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_WIDTH 1
1552`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_INT_SLC 0:0
1553`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_POSITION 4
1554`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
1555`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
1556`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_POR_VALUE 1'b0
1557`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_EGRESS_PE_FIELD_NAME "int_egress_pe"
1558`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_FID 13
1559`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_SLC 2:2
1560`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_WIDTH 1
1561`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_INT_SLC 0:0
1562`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_POSITION 2
1563`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1564`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1565`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_POR_VALUE 1'b0
1566`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_TMR_TO_FIELD_NAME "int_rplay_tmr_to"
1567`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_FID 14
1568`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_SLC 1:1
1569`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_WIDTH 1
1570`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_INT_SLC 0:0
1571`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_POSITION 1
1572`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1573`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1574`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_POR_VALUE 1'b0
1575`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_RPLAY_NUM_RO_FIELD_NAME "int_rplay_num_ro"
1576`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_FID 15
1577`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_SLC 0:0
1578`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_WIDTH 1
1579`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_INT_SLC 0:0
1580`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_POSITION 0
1581`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1582`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1583`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_POR_VALUE 1'b0
1584`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_INT_INT_DLNK_PES_FIELD_NAME "int_dlnk_pes"
1585
1586//-------------------------------------------------------
1587//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST
1588//-------------------------------------------------------
1589
1590`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ADDR 20'b11011100010001000011
1591`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_ADDR 30'b000000011011100010001000011000
1592`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_tst"
1593`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_WIDTH 64
1594`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_DEPTH 1
1595`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_SLC 63:0
1596`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_INT_SLC 63:0
1597`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_POSITION 0
1598`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_tst"
1599`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_LOW_ADDR_WIDTH 0
1600`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_ADDR_RANGE 19:0
1601`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_READ_MASK 64'b0000000000000000000000000000000000000000011101110000001111110111
1602`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1603`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1604`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1605`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_SET_MASK 64'b0000000000000000000000000000000000000000011101110000001111110111
1606`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1607`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1608`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_RMASK 64'b0000000000000000000000000000000000000000011101110000001111110111
1609`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111100010001111110000001000
1610`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_LD_MASK 64'b0000000000000000000000000000000000000000011101110000001111110111
1611`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1612`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_INTERNAL_REG 0
1613`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_EXTERNAL_DECODE_REG 0
1614`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_ALIASED_FROM 0
1615`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_ZERO_TIME_OMNI 0
1616`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_JTAG_RD 1
1617`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_JTAG_WR 1
1618`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_SBUS_RD 1
1619`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_SBUS_WR 1
1620`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_RAP_RD 1
1621`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_HW_ACC_RAP_WR 1
1622`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_NUM_FIELDS 15
1623`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_FID 0
1624`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_SLC 22:22
1625`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_WIDTH 1
1626`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_INT_SLC 0:0
1627`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_POSITION 22
1628`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_FMASK 64'b0000000000000000000000000000000000000000010000000000000000000000
1629`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000010000000000000000000000
1630`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_POR_VALUE 1'b0
1631`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_UNSPRTD_DLLP_FIELD_NAME "tst_unsprtd_dllp"
1632`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_FID 1
1633`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_SLC 21:21
1634`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_WIDTH 1
1635`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_INT_SLC 0:0
1636`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_POSITION 21
1637`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_FMASK 64'b0000000000000000000000000000000000000000001000000000000000000000
1638`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000001000000000000000000000
1639`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_POR_VALUE 1'b0
1640`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLLP_RCV_ERR_FIELD_NAME "tst_dllp_rcv_err"
1641`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_FID 2
1642`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_SLC 20:20
1643`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_WIDTH 1
1644`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_INT_SLC 0:0
1645`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_POSITION 20
1646`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_FMASK 64'b0000000000000000000000000000000000000000000100000000000000000000
1647`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000100000000000000000000
1648`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_POR_VALUE 1'b0
1649`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_DLLP_FIELD_NAME "tst_bad_dllp"
1650`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_FID 3
1651`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_SLC 18:18
1652`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_WIDTH 1
1653`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_INT_SLC 0:0
1654`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_POSITION 18
1655`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_FMASK 64'b0000000000000000000000000000000000000000000001000000000000000000
1656`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000001000000000000000000
1657`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_POR_VALUE 1'b0
1658`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_TLP_RCV_ERR_FIELD_NAME "tst_tlp_rcv_err"
1659`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_FID 4
1660`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_SLC 17:17
1661`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_WIDTH 1
1662`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_INT_SLC 0:0
1663`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_POSITION 17
1664`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_FMASK 64'b0000000000000000000000000000000000000000000000100000000000000000
1665`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000100000000000000000
1666`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_POR_VALUE 1'b0
1667`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_SRC_ERR_TLP_FIELD_NAME "tst_src_err_tlp"
1668`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_FID 5
1669`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_SLC 16:16
1670`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_WIDTH 1
1671`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_INT_SLC 0:0
1672`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_POSITION 16
1673`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_FMASK 64'b0000000000000000000000000000000000000000000000010000000000000000
1674`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000010000000000000000
1675`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_POR_VALUE 1'b0
1676`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_BAD_TLP_FIELD_NAME "tst_bad_tlp"
1677`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_FID 6
1678`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_SLC 9:9
1679`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_WIDTH 1
1680`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_INT_SLC 0:0
1681`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_POSITION 9
1682`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
1683`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
1684`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_POR_VALUE 1'b0
1685`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_UDF_ERR_FIELD_NAME "tst_rtry_buf_udf_err"
1686`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_FID 7
1687`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_SLC 8:8
1688`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_WIDTH 1
1689`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_INT_SLC 0:0
1690`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_POSITION 8
1691`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
1692`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
1693`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_POR_VALUE 1'b0
1694`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_OVF_FIELD_NAME "tst_rtry_buf_ovf"
1695`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_FID 8
1696`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_SLC 7:7
1697`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_WIDTH 1
1698`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_INT_SLC 0:0
1699`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_POSITION 7
1700`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
1701`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
1702`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_POR_VALUE 1'b0
1703`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TLP_MIN_ERR_FIELD_NAME "tst_eg_tlp_min_err"
1704`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_FID 9
1705`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_SLC 6:6
1706`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_WIDTH 1
1707`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_INT_SLC 0:0
1708`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_POSITION 6
1709`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
1710`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
1711`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_POR_VALUE 1'b0
1712`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EG_TRNC_FRM_ERR_FIELD_NAME "tst_eg_trnc_frm_err"
1713`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_FID 10
1714`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_SLC 5:5
1715`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_WIDTH 1
1716`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_INT_SLC 0:0
1717`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_POSITION 5
1718`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
1719`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
1720`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_POR_VALUE 1'b0
1721`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RTRY_BUF_PE_FIELD_NAME "tst_rtry_buf_pe"
1722`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_FID 11
1723`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_SLC 4:4
1724`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_WIDTH 1
1725`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_INT_SLC 0:0
1726`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_POSITION 4
1727`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
1728`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
1729`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_POR_VALUE 1'b0
1730`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_EGRESS_PE_FIELD_NAME "tst_egress_pe"
1731`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_FID 12
1732`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_SLC 2:2
1733`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_WIDTH 1
1734`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_INT_SLC 0:0
1735`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_POSITION 2
1736`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1737`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1738`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_POR_VALUE 1'b0
1739`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_TMR_TO_FIELD_NAME "tst_rplay_tmr_to"
1740`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_FID 13
1741`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_SLC 1:1
1742`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_WIDTH 1
1743`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_INT_SLC 0:0
1744`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_POSITION 1
1745`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1746`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1747`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_POR_VALUE 1'b0
1748`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_RPLAY_NUM_RO_FIELD_NAME "tst_rplay_num_ro"
1749`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_FID 14
1750`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_SLC 0:0
1751`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_WIDTH 1
1752`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_INT_SLC 0:0
1753`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_POSITION 0
1754`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1755`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1756`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_POR_VALUE 1'b0
1757`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_TST_TST_DLNK_PES_FIELD_NAME "tst_dlnk_pes"
1758
1759//-------------------------------------------------------
1760//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK
1761//-------------------------------------------------------
1762
1763`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ADDR 20'b11011100010001000100
1764`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_ADDR 30'b000000011011100010001000100000
1765`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_msk"
1766`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_WIDTH 64
1767`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_DEPTH 1
1768`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_SLC 63:0
1769`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_INT_SLC 63:0
1770`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_POSITION 0
1771`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ll_err_msk"
1772`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_LOW_ADDR_WIDTH 0
1773`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_ADDR_RANGE 19:0
1774`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_READ_MASK 64'b0000000000000000000000000000000010000000011101110000001111110111
1775`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1776`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_WRITE_MASK 64'b0000000000000000000000000000000010000000011101110000001111110111
1777`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1778`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1779`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1780`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1781`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_RMASK 64'b0000000000000000000000000000000010000000011101110000001111110111
1782`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111100010001111110000001000
1783`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1784`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1785`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_INTERNAL_REG 0
1786`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_EXTERNAL_DECODE_REG 0
1787`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_ALIASED_FROM 0
1788`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_ZERO_TIME_OMNI 0
1789`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_JTAG_RD 1
1790`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_JTAG_WR 1
1791`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_SBUS_RD 1
1792`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_SBUS_WR 1
1793`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_RAP_RD 1
1794`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_HW_ACC_RAP_WR 1
1795`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_NUM_FIELDS 16
1796`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_FID 0
1797`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_SLC 31:31
1798`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_WIDTH 1
1799`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_INT_SLC 0:0
1800`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_POSITION 31
1801`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
1802`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1803`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_POR_VALUE 1'b0
1804`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_LINK_ERR_ACT_FIELD_NAME "msk_link_err_act"
1805`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_FID 1
1806`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_SLC 22:22
1807`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_WIDTH 1
1808`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_INT_SLC 0:0
1809`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_POSITION 22
1810`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_FMASK 64'b0000000000000000000000000000000000000000010000000000000000000000
1811`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1812`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_POR_VALUE 1'b0
1813`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_UNSPRTD_DLLP_FIELD_NAME "msk_unsprtd_dllp"
1814`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_FID 2
1815`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_SLC 21:21
1816`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_WIDTH 1
1817`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_INT_SLC 0:0
1818`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_POSITION 21
1819`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_FMASK 64'b0000000000000000000000000000000000000000001000000000000000000000
1820`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1821`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_POR_VALUE 1'b0
1822`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLLP_RCV_ERR_FIELD_NAME "msk_dllp_rcv_err"
1823`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_FID 3
1824`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_SLC 20:20
1825`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_WIDTH 1
1826`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_INT_SLC 0:0
1827`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_POSITION 20
1828`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_FMASK 64'b0000000000000000000000000000000000000000000100000000000000000000
1829`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1830`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_POR_VALUE 1'b0
1831`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_DLLP_FIELD_NAME "msk_bad_dllp"
1832`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_FID 4
1833`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_SLC 18:18
1834`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_WIDTH 1
1835`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_INT_SLC 0:0
1836`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_POSITION 18
1837`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_FMASK 64'b0000000000000000000000000000000000000000000001000000000000000000
1838`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1839`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_POR_VALUE 1'b0
1840`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_TLP_RCV_ERR_FIELD_NAME "msk_tlp_rcv_err"
1841`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_FID 5
1842`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_SLC 17:17
1843`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_WIDTH 1
1844`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_INT_SLC 0:0
1845`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_POSITION 17
1846`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_FMASK 64'b0000000000000000000000000000000000000000000000100000000000000000
1847`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1848`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_POR_VALUE 1'b0
1849`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_SRC_ERR_TLP_FIELD_NAME "msk_src_err_tlp"
1850`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_FID 6
1851`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_SLC 16:16
1852`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_WIDTH 1
1853`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_INT_SLC 0:0
1854`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_POSITION 16
1855`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_FMASK 64'b0000000000000000000000000000000000000000000000010000000000000000
1856`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1857`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_POR_VALUE 1'b0
1858`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_BAD_TLP_FIELD_NAME "msk_bad_tlp"
1859`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_FID 7
1860`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_SLC 9:9
1861`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_WIDTH 1
1862`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_INT_SLC 0:0
1863`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_POSITION 9
1864`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
1865`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1866`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_POR_VALUE 1'b0
1867`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_UNF_OVF_FIELD_NAME "msk_rtry_unf_ovf"
1868`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_FID 8
1869`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_SLC 8:8
1870`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_WIDTH 1
1871`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_INT_SLC 0:0
1872`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_POSITION 8
1873`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
1874`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1875`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_POR_VALUE 1'b0
1876`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_OVF_FIELD_NAME "msk_rtry_buf_ovf"
1877`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_FID 9
1878`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_SLC 7:7
1879`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_WIDTH 1
1880`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_INT_SLC 0:0
1881`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_POSITION 7
1882`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
1883`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1884`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_POR_VALUE 1'b0
1885`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TLP_MIN_ERR_FIELD_NAME "msk_eg_tlp_min_err"
1886`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_FID 10
1887`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_SLC 6:6
1888`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_WIDTH 1
1889`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_INT_SLC 0:0
1890`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_POSITION 6
1891`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
1892`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1893`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_POR_VALUE 1'b0
1894`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EG_TRNC_FRM_ERR_FIELD_NAME "msk_eg_trnc_frm_err"
1895`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_FID 11
1896`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_SLC 5:5
1897`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_WIDTH 1
1898`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_INT_SLC 0:0
1899`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_POSITION 5
1900`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
1901`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1902`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_POR_VALUE 1'b0
1903`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RTRY_BUF_PE_FIELD_NAME "msk_rtry_buf_pe"
1904`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_FID 12
1905`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_SLC 4:4
1906`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_WIDTH 1
1907`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_INT_SLC 0:0
1908`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_POSITION 4
1909`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
1910`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1911`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_POR_VALUE 1'b0
1912`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_EGRESS_PE_FIELD_NAME "msk_egress_pe"
1913`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_FID 13
1914`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_SLC 2:2
1915`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_WIDTH 1
1916`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_INT_SLC 0:0
1917`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_POSITION 2
1918`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1919`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1920`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_POR_VALUE 1'b0
1921`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_TMR_TO_FIELD_NAME "msk_rplay_tmr_to"
1922`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_FID 14
1923`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_SLC 1:1
1924`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_WIDTH 1
1925`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_INT_SLC 0:0
1926`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_POSITION 1
1927`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1928`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1929`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_POR_VALUE 1'b0
1930`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_RPLAY_NUM_RO_FIELD_NAME "msk_rplay_num_ro"
1931`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_FID 15
1932`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_SLC 0:0
1933`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_WIDTH 1
1934`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_INT_SLC 0:0
1935`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_POSITION 0
1936`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1937`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1938`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_POR_VALUE 1'b0
1939`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LL_ERR_MSK_MSK_DLNK_PES_FIELD_NAME "msk_dlnk_pes"
1940
1941//-------------------------------------------------------
1942//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL
1943//-------------------------------------------------------
1944
1945`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ADDR 20'b11011100010001001000
1946`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_ADDR 30'b000000011011100010001001000000
1947`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_fc_up_cntl"
1948`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_WIDTH 64
1949`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_DEPTH 1
1950`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_SLC 63:0
1951`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_INT_SLC 63:0
1952`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_POSITION 0
1953`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_fc_up_cntl"
1954`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_LOW_ADDR_WIDTH 0
1955`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_ADDR_RANGE 19:0
1956`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000111
1957`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1958`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000111
1959`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1960`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1961`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1962`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1963`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000111
1964`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111000
1965`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1966`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000011
1967`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_INTERNAL_REG 0
1968`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_EXTERNAL_DECODE_REG 0
1969`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_ALIASED_FROM 0
1970`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_ZERO_TIME_OMNI 0
1971`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_JTAG_RD 1
1972`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_JTAG_WR 1
1973`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_SBUS_RD 1
1974`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_SBUS_WR 1
1975`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_RAP_RD 1
1976`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_HW_ACC_RAP_WR 1
1977`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_NUM_FIELDS 3
1978`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_FID 0
1979`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_SLC 2:2
1980`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_WIDTH 1
1981`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_INT_SLC 0:0
1982`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_POSITION 2
1983`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1984`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1985`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_POR_VALUE 1'b0
1986`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_C_EN_FIELD_NAME "fc0_u_c_en"
1987`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_FID 1
1988`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_SLC 1:1
1989`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_WIDTH 1
1990`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_INT_SLC 0:0
1991`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_POSITION 1
1992`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1993`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1994`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_POR_VALUE 1'b1
1995`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_NP_EN_FIELD_NAME "fc0_u_np_en"
1996`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_FID 2
1997`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_SLC 0:0
1998`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_WIDTH 1
1999`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_INT_SLC 0:0
2000`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_POSITION 0
2001`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
2002`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2003`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_POR_VALUE 1'b1
2004`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_CNTL_FC0_U_P_EN_FIELD_NAME "fc0_u_p_en"
2005
2006//-------------------------------------------------------
2007//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL
2008//-------------------------------------------------------
2009
2010`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ADDR 20'b11011100010001001100
2011`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_ADDR 30'b000000011011100010001001100000
2012`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_fc_up_to_val"
2013`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_WIDTH 64
2014`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_DEPTH 1
2015`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_SLC 63:0
2016`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_INT_SLC 63:0
2017`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_POSITION 0
2018`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_fc_up_to_val"
2019`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_LOW_ADDR_WIDTH 0
2020`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_ADDR_RANGE 19:0
2021`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_READ_MASK 64'b0000000000000000000000000000000000000000000000000111111111111111
2022`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2023`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000111111111111111
2024`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2025`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2026`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2027`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2028`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_RMASK 64'b0000000000000000000000000000000000000000000000000111111111111111
2029`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111000000000000000
2030`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2031`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000001110101001100
2032`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_INTERNAL_REG 0
2033`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_EXTERNAL_DECODE_REG 0
2034`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_ALIASED_FROM 0
2035`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_ZERO_TIME_OMNI 0
2036`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_JTAG_RD 1
2037`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_JTAG_WR 1
2038`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_SBUS_RD 1
2039`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_SBUS_WR 1
2040`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_RAP_RD 1
2041`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_HW_ACC_RAP_WR 1
2042`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_NUM_FIELDS 1
2043`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_FID 0
2044`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_SLC 14:0
2045`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_WIDTH 15
2046`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_INT_SLC 14:0
2047`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_POSITION 0
2048`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_FMASK 64'b0000000000000000000000000000000000000000000000000111111111111111
2049`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2050`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_POR_VALUE 15'b001110101001100
2051`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_FC_UP_TO_VAL_FC_UPDATE_TO_FIELD_NAME "fc_update_to"
2052
2053//-------------------------------------------------------
2054//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0
2055//-------------------------------------------------------
2056
2057`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ADDR 20'b11011100010001001101
2058`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_ADDR 30'b000000011011100010001001101000
2059`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_vco_fc_cntl_up_tmr0"
2060`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_WIDTH 64
2061`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_DEPTH 1
2062`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_SLC 63:0
2063`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_INT_SLC 63:0
2064`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_POSITION 0
2065`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_vco_fc_cntl_up_tmr0"
2066`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_LOW_ADDR_WIDTH 0
2067`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_ADDR_RANGE 19:0
2068`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_READ_MASK 64'b0000000000000000000000000000000001111111111111110111111111111111
2069`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_READ_ONLY_MASK 64'b0000000000000000000000000000000001111111111111110111111111111111
2070`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2071`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2072`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2073`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2074`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2075`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_RMASK 64'b0000000000000000000000000000000001111111111111110111111111111111
2076`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_RESERVED_BIT_MASK 64'b1111111111111111111111111111111110000000000000001000000000000000
2077`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2078`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
2079`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_INTERNAL_REG 0
2080`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_EXTERNAL_DECODE_REG 0
2081`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_ALIASED_FROM 0
2082`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_ZERO_TIME_OMNI 0
2083`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_JTAG_RD 1
2084`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_JTAG_WR 1
2085`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_SBUS_RD 1
2086`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_SBUS_WR 1
2087`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_RAP_RD 1
2088`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_HW_ACC_RAP_WR 1
2089`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_NUM_FIELDS 2
2090`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_FID 0
2091`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_SLC 30:16
2092`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_WIDTH 15
2093`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_INT_SLC 14:0
2094`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_POSITION 16
2095`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_FMASK 64'b0000000000000000000000000000000001111111111111110000000000000000
2096`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2097`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_POR_VALUE 15'b000000000000000
2098`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_NP_FIELD_NAME "vc0_fc_up_tmr_np"
2099`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_FID 1
2100`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_SLC 14:0
2101`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_WIDTH 15
2102`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_INT_SLC 14:0
2103`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_POSITION 0
2104`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_FMASK 64'b0000000000000000000000000000000000000000000000000111111111111111
2105`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2106`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_POR_VALUE 15'b000000000000000
2107`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR0_VC0_FC_UP_TMR_P_FIELD_NAME "vc0_fc_up_tmr_p"
2108
2109//-------------------------------------------------------
2110//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1
2111//-------------------------------------------------------
2112
2113`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ADDR 20'b11011100010001001110
2114`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_ADDR 30'b000000011011100010001001110000
2115`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_vco_fc_cntl_up_tmr1"
2116`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_WIDTH 64
2117`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_DEPTH 1
2118`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_SLC 63:0
2119`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_INT_SLC 63:0
2120`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_POSITION 0
2121`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_vco_fc_cntl_up_tmr1"
2122`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_LOW_ADDR_WIDTH 0
2123`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_ADDR_RANGE 19:0
2124`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_READ_MASK 64'b0000000000000000000000000000000000000000000000000111111111111111
2125`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000111111111111111
2126`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2127`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2128`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2129`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2130`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2131`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_RMASK 64'b0000000000000000000000000000000000000000000000000111111111111111
2132`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111000000000000000
2133`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2134`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
2135`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_INTERNAL_REG 0
2136`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_EXTERNAL_DECODE_REG 0
2137`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_ALIASED_FROM 0
2138`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_ZERO_TIME_OMNI 0
2139`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_JTAG_RD 1
2140`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_JTAG_WR 1
2141`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_SBUS_RD 1
2142`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_SBUS_WR 1
2143`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_RAP_RD 1
2144`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_HW_ACC_RAP_WR 1
2145`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_NUM_FIELDS 1
2146`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_FID 0
2147`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_SLC 14:0
2148`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_WIDTH 15
2149`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_INT_SLC 14:0
2150`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_POSITION 0
2151`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_FMASK 64'b0000000000000000000000000000000000000000000000000111111111111111
2152`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2153`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_POR_VALUE 15'b000000000000000
2154`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_VCO_FC_CNTL_UP_TMR1_VC0_FC_UP_TMR_CPL_FIELD_NAME "vc0_fc_up_tmr_cpl"
2155
2156//-------------------------------------------------------
2157//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY
2158//-------------------------------------------------------
2159
2160`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ADDR 20'b11011100010010000000
2161`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ADDR 30'b000000011011100010010000000000
2162`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_acknak_latency"
2163`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_WIDTH 64
2164`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_DEPTH 1
2165`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_SLC 63:0
2166`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_INT_SLC 63:0
2167`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_POSITION 0
2168`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_acknak_latency"
2169`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_LOW_ADDR_WIDTH 0
2170`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ADDR_RANGE 19:0
2171`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2172`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2173`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_WRITE_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2174`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2175`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2176`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2177`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2178`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2179`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
2180`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2181`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000110000
2182`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_INTERNAL_REG 0
2183`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_EXTERNAL_DECODE_REG 0
2184`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ALIASED_FROM 0
2185`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ZERO_TIME_OMNI 0
2186`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_JTAG_RD 1
2187`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_JTAG_WR 1
2188`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_SBUS_RD 1
2189`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_SBUS_WR 1
2190`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_RAP_RD 1
2191`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_HW_ACC_RAP_WR 1
2192`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_NUM_FIELDS 1
2193`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_FID 0
2194`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_SLC 15:0
2195`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_WIDTH 16
2196`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_INT_SLC 15:0
2197`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_POSITION 0
2198`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2199`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2200`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_POR_VALUE 16'b0000000000110000
2201`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_ACK_NAK_THR_FIELD_NAME "ack_nak_thr"
2202
2203//-------------------------------------------------------
2204//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR
2205//-------------------------------------------------------
2206
2207`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ADDR 20'b11011100010010000001
2208`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ADDR 30'b000000011011100010010000001000
2209`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_acknak_latency_tmr"
2210`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_WIDTH 64
2211`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_DEPTH 1
2212`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_SLC 63:0
2213`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_INT_SLC 63:0
2214`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_POSITION 0
2215`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_acknak_latency_tmr"
2216`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_LOW_ADDR_WIDTH 0
2217`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ADDR_RANGE 19:0
2218`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2219`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2220`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2221`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2222`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2223`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2224`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2225`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2226`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
2227`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2228`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
2229`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_INTERNAL_REG 0
2230`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_EXTERNAL_DECODE_REG 0
2231`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ALIASED_FROM 0
2232`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ZERO_TIME_OMNI 0
2233`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_JTAG_RD 1
2234`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_JTAG_WR 1
2235`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_SBUS_RD 1
2236`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_SBUS_WR 1
2237`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_RAP_RD 1
2238`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_HW_ACC_RAP_WR 1
2239`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_NUM_FIELDS 1
2240`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_FID 0
2241`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_SLC 15:0
2242`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_WIDTH 16
2243`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_INT_SLC 15:0
2244`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_POSITION 0
2245`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2246`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2247`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_POR_VALUE 16'b0000000000000000
2248`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACKNAK_LATENCY_TMR_ACK_NAK_TMR_FIELD_NAME "ack_nak_tmr"
2249
2250//-------------------------------------------------------
2251//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD
2252//-------------------------------------------------------
2253
2254`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ADDR 20'b11011100010010000010
2255`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_ADDR 30'b000000011011100010010000010000
2256`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_tmr_thhold"
2257`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_WIDTH 64
2258`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_DEPTH 1
2259`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_SLC 63:0
2260`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_INT_SLC 63:0
2261`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_POSITION 0
2262`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_tmr_thhold"
2263`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_LOW_ADDR_WIDTH 0
2264`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_ADDR_RANGE 19:0
2265`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_READ_MASK 64'b0000000000000000000000000000000000000000000011111111111111111111
2266`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2267`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_WRITE_MASK 64'b0000000000000000000000000000000000000000000011111111111111111111
2268`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2269`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2270`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2271`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2272`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RMASK 64'b0000000000000000000000000000000000000000000011111111111111111111
2273`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111100000000000000000000
2274`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2275`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000010010000
2276`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_INTERNAL_REG 0
2277`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_EXTERNAL_DECODE_REG 0
2278`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_ALIASED_FROM 0
2279`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_ZERO_TIME_OMNI 0
2280`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_JTAG_RD 1
2281`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_JTAG_WR 1
2282`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_SBUS_RD 1
2283`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_SBUS_WR 1
2284`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_RAP_RD 1
2285`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_HW_ACC_RAP_WR 1
2286`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_NUM_FIELDS 1
2287`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_FID 0
2288`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_SLC 19:0
2289`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_WIDTH 20
2290`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_INT_SLC 19:0
2291`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_POSITION 0
2292`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_FMASK 64'b0000000000000000000000000000000000000000000011111111111111111111
2293`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2294`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_POR_VALUE 20'b00000000000010010000
2295`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_THHOLD_RPLAY_TMR_THR_FIELD_NAME "rplay_tmr_thr"
2296
2297//-------------------------------------------------------
2298//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR
2299//-------------------------------------------------------
2300
2301`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ADDR 20'b11011100010010000011
2302`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_ADDR 30'b000000011011100010010000011000
2303`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_tmr"
2304`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_WIDTH 64
2305`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_DEPTH 1
2306`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_SLC 63:0
2307`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_INT_SLC 63:0
2308`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_POSITION 0
2309`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_tmr"
2310`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_LOW_ADDR_WIDTH 0
2311`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_ADDR_RANGE 19:0
2312`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_READ_MASK 64'b0000000000000000000000000000000000000000000011111111111111111111
2313`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000011111111111111111111
2314`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2315`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2316`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2317`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2318`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2319`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RMASK 64'b0000000000000000000000000000000000000000000011111111111111111111
2320`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111100000000000000000000
2321`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2322`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000010010000
2323`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_INTERNAL_REG 0
2324`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_EXTERNAL_DECODE_REG 0
2325`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_ALIASED_FROM 0
2326`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_ZERO_TIME_OMNI 0
2327`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_JTAG_RD 1
2328`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_JTAG_WR 1
2329`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_SBUS_RD 1
2330`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_SBUS_WR 1
2331`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_RAP_RD 1
2332`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_HW_ACC_RAP_WR 1
2333`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_NUM_FIELDS 1
2334`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_FID 0
2335`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_SLC 19:0
2336`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_WIDTH 20
2337`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_INT_SLC 19:0
2338`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_POSITION 0
2339`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_FMASK 64'b0000000000000000000000000000000000000000000011111111111111111111
2340`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2341`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_POR_VALUE 20'b00000000000010010000
2342`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_TMR_RPLAY_TMR_FIELD_NAME "rplay_tmr"
2343
2344//-------------------------------------------------------
2345//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT
2346//-------------------------------------------------------
2347
2348`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ADDR 20'b11011100010010000100
2349`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_ADDR 30'b000000011011100010010000100000
2350`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_num_stat"
2351`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WIDTH 64
2352`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_DEPTH 1
2353`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_SLC 63:0
2354`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_INT_SLC 63:0
2355`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_POSITION 0
2356`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rplay_num_stat"
2357`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_LOW_ADDR_WIDTH 0
2358`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_ADDR_RANGE 19:0
2359`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_READ_MASK 64'b0000000000000000000000000000000010000000000000000000000000000011
2360`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2361`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WRITE_MASK 64'b0000000000000000000000000000000010000000000000000000000000000011
2362`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2363`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2364`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2365`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2366`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RMASK 64'b0000000000000000000000000000000010000000000000000000000000000011
2367`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111111111111111100
2368`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
2369`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
2370`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_INTERNAL_REG 0
2371`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_EXTERNAL_DECODE_REG 0
2372`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_ALIASED_FROM 0
2373`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_ZERO_TIME_OMNI 0
2374`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_JTAG_RD 1
2375`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_JTAG_WR 1
2376`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_SBUS_RD 1
2377`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_SBUS_WR 1
2378`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_RAP_RD 1
2379`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_HW_ACC_RAP_WR 1
2380`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_NUM_FIELDS 2
2381`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_FID 0
2382`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_SLC 31:31
2383`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_WIDTH 1
2384`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_INT_SLC 0:0
2385`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_POSITION 31
2386`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
2387`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2388`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_POR_VALUE 1'b0
2389`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_WE_FIELD_NAME "we"
2390`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_FID 1
2391`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_SLC 1:0
2392`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_WIDTH 2
2393`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_INT_SLC 1:0
2394`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_POSITION 0
2395`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011
2396`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
2397`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_POR_VALUE 2'b00
2398`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RPLAY_NUM_STAT_RPLAY_NUM_CNTR_FIELD_NAME "rplay_num_cntr"
2399
2400//-------------------------------------------------------
2401//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR
2402//-------------------------------------------------------
2403
2404`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ADDR 20'b11011100010010000101
2405`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_ADDR 30'b000000011011100010010000101000
2406`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_buff_max_addr"
2407`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_WIDTH 64
2408`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_DEPTH 1
2409`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_SLC 63:0
2410`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_INT_SLC 63:0
2411`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_POSITION 0
2412`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_buff_max_addr"
2413`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_LOW_ADDR_WIDTH 0
2414`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_ADDR_RANGE 19:0
2415`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2416`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2417`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2418`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2419`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2420`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2421`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2422`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2423`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
2424`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2425`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000001010101111111
2426`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_INTERNAL_REG 0
2427`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_EXTERNAL_DECODE_REG 0
2428`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_ALIASED_FROM 0
2429`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_ZERO_TIME_OMNI 0
2430`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_JTAG_RD 1
2431`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_JTAG_WR 1
2432`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_SBUS_RD 1
2433`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_SBUS_WR 1
2434`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_RAP_RD 1
2435`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_HW_ACC_RAP_WR 1
2436`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_NUM_FIELDS 1
2437`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_FID 0
2438`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_SLC 15:0
2439`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_WIDTH 16
2440`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_INT_SLC 15:0
2441`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_POSITION 0
2442`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2443`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2444`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_POR_VALUE 16'b0001010101111111
2445`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_BUFF_MAX_ADDR_RTRY_BUFF_MAX_ADDR_FIELD_NAME "rtry_buff_max_addr"
2446
2447//-------------------------------------------------------
2448//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR
2449//-------------------------------------------------------
2450
2451`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ADDR 20'b11011100010010000110
2452`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_ADDR 30'b000000011011100010010000110000
2453`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_ptr"
2454`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_WIDTH 64
2455`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_DEPTH 1
2456`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_SLC 63:0
2457`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_INT_SLC 63:0
2458`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_POSITION 0
2459`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_ptr"
2460`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_LOW_ADDR_WIDTH 0
2461`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_ADDR_RANGE 19:0
2462`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
2463`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2464`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
2465`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2466`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2467`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2468`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2469`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
2470`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
2471`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
2472`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_POR_VALUE 64'b0000000000000000000000000000000011111111111111110000000000000000
2473`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_INTERNAL_REG 0
2474`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_EXTERNAL_DECODE_REG 0
2475`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_ALIASED_FROM 0
2476`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_ZERO_TIME_OMNI 0
2477`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_JTAG_RD 1
2478`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_JTAG_WR 1
2479`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_SBUS_RD 1
2480`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_SBUS_WR 1
2481`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_RAP_RD 1
2482`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_HW_ACC_RAP_WR 1
2483`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_NUM_FIELDS 2
2484`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_FID 0
2485`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_SLC 31:16
2486`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_WIDTH 16
2487`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_INT_SLC 15:0
2488`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_POSITION 16
2489`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
2490`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111110000000000000000
2491`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_POR_VALUE 16'b1111111111111111
2492`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_TLPTR_FIELD_NAME "rtry_fifo_tlptr"
2493`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_FID 1
2494`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_SLC 15:0
2495`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_WIDTH 16
2496`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_INT_SLC 15:0
2497`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_POSITION 0
2498`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2499`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2500`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_POR_VALUE 16'b0000000000000000
2501`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_PTR_RTRY_FIFO_HDPTR_FIELD_NAME "rtry_fifo_hdptr"
2502
2503//-------------------------------------------------------
2504//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR
2505//-------------------------------------------------------
2506
2507`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ADDR 20'b11011100010010000111
2508`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_ADDR 30'b000000011011100010010000111000
2509`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_rw_ptr"
2510`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_WIDTH 64
2511`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_DEPTH 1
2512`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_SLC 63:0
2513`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_INT_SLC 63:0
2514`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_POSITION 0
2515`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_rw_ptr"
2516`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_LOW_ADDR_WIDTH 0
2517`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_ADDR_RANGE 19:0
2518`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
2519`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_READ_ONLY_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
2520`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2521`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2522`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2523`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2524`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2525`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
2526`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
2527`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2528`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
2529`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_INTERNAL_REG 0
2530`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_EXTERNAL_DECODE_REG 0
2531`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_ALIASED_FROM 0
2532`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_ZERO_TIME_OMNI 0
2533`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_JTAG_RD 1
2534`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_JTAG_WR 1
2535`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_SBUS_RD 1
2536`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_SBUS_WR 1
2537`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_RAP_RD 1
2538`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_HW_ACC_RAP_WR 1
2539`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_NUM_FIELDS 2
2540`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_FID 0
2541`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_SLC 31:16
2542`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_WIDTH 16
2543`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_INT_SLC 15:0
2544`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_POSITION 16
2545`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
2546`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2547`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_POR_VALUE 16'b0000000000000000
2548`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_WRPTR_FIELD_NAME "rtry_bffr_wrptr"
2549`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_FID 1
2550`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_SLC 15:0
2551`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_WIDTH 16
2552`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_INT_SLC 15:0
2553`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_POSITION 0
2554`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2555`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2556`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_POR_VALUE 16'b0000000000000000
2557`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_RW_PTR_RTRY_BFFR_RDPTR_FIELD_NAME "rtry_bffr_rdptr"
2558
2559//-------------------------------------------------------
2560//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT
2561//-------------------------------------------------------
2562
2563`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ADDR 20'b11011100010010001000
2564`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_ADDR 30'b000000011011100010010001000000
2565`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_crdt"
2566`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_WIDTH 64
2567`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_DEPTH 1
2568`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_SLC 63:0
2569`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_INT_SLC 63:0
2570`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_POSITION 0
2571`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_fifo_crdt"
2572`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_LOW_ADDR_WIDTH 0
2573`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_ADDR_RANGE 19:0
2574`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2575`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2576`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2577`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2578`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2579`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2580`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2581`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2582`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
2583`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2584`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000001010110000000
2585`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_INTERNAL_REG 0
2586`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_EXTERNAL_DECODE_REG 0
2587`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_ALIASED_FROM 0
2588`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_ZERO_TIME_OMNI 0
2589`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_JTAG_RD 1
2590`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_JTAG_WR 1
2591`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_SBUS_RD 1
2592`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_SBUS_WR 1
2593`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_RAP_RD 1
2594`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_HW_ACC_RAP_WR 1
2595`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_NUM_FIELDS 1
2596`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_FID 0
2597`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_SLC 15:0
2598`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_WIDTH 16
2599`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_INT_SLC 15:0
2600`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_POSITION 0
2601`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
2602`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2603`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_POR_VALUE 16'b0001010110000000
2604`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_FIFO_CRDT_RTRY_FIFO_CRDT_FIELD_NAME "rtry_fifo_crdt"
2605
2606//-------------------------------------------------------
2607//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR
2608//-------------------------------------------------------
2609
2610`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ADDR 20'b11011100010010001001
2611`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ADDR 30'b000000011011100010010001001000
2612`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cntr"
2613`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WIDTH 64
2614`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_DEPTH 1
2615`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_SLC 63:0
2616`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_INT_SLC 63:0
2617`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_POSITION 0
2618`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cntr"
2619`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_LOW_ADDR_WIDTH 0
2620`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ADDR_RANGE 19:0
2621`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_READ_MASK 64'b0000000000000000000000000000000000001111111111110000111111111111
2622`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2623`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WRITE_MASK 64'b0000000000000000000000000000000011001111111111110000111111111111
2624`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000011000000000000000000000000000000
2625`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2626`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2627`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2628`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_RMASK 64'b0000000000000000000000000000000011001111111111110000111111111111
2629`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100110000000000001111000000000000
2630`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_LD_MASK 64'b0000000000000000000000000000000011001111111111110000111111111111
2631`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_POR_VALUE 64'b0000000000000000000000000000000000001111111111110000000000000000
2632`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_INTERNAL_REG 0
2633`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_EXTERNAL_DECODE_REG 0
2634`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ALIASED_FROM 0
2635`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ZERO_TIME_OMNI 0
2636`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_JTAG_RD 1
2637`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_JTAG_WR 1
2638`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_SBUS_RD 1
2639`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_SBUS_WR 1
2640`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_RAP_RD 1
2641`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_HW_ACC_RAP_WR 1
2642`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NUM_FIELDS 4
2643`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_FID 0
2644`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_SLC 31:31
2645`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_WIDTH 1
2646`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_INT_SLC 0:0
2647`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_POSITION 31
2648`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
2649`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_HW_LD_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
2650`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_POR_VALUE 1'b0
2651`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_WE_FIELD_NAME "we"
2652`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_FID 1
2653`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_SLC 30:30
2654`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_WIDTH 1
2655`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_INT_SLC 0:0
2656`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_POSITION 30
2657`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_FMASK 64'b0000000000000000000000000000000001000000000000000000000000000000
2658`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_HW_LD_MASK 64'b0000000000000000000000000000000001000000000000000000000000000000
2659`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_POR_VALUE 1'b0
2660`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_WE_FIELD_NAME "ack_seq_we"
2661`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_FID 2
2662`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_SLC 27:16
2663`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_WIDTH 12
2664`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_INT_SLC 11:0
2665`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_POSITION 16
2666`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_FMASK 64'b0000000000000000000000000000000000001111111111110000000000000000
2667`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_HW_LD_MASK 64'b0000000000000000000000000000000000001111111111110000000000000000
2668`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_POR_VALUE 12'b111111111111
2669`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_ACK_SEQ_CNTR_FIELD_NAME "ack_seq_cntr"
2670`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_FID 3
2671`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_SLC 11:0
2672`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_WIDTH 12
2673`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_INT_SLC 11:0
2674`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_POSITION 0
2675`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2676`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2677`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_POR_VALUE 12'b000000000000
2678`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNTR_NXT_TX_SEQ_CNTR_FIELD_NAME "nxt_tx_seq_cntr"
2679
2680//-------------------------------------------------------
2681//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM
2682//-------------------------------------------------------
2683
2684`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ADDR 20'b11011100010010001010
2685`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_ADDR 30'b000000011011100010010001010000
2686`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ack_snd_seq_num"
2687`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_WIDTH 64
2688`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_DEPTH 1
2689`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SLC 63:0
2690`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_INT_SLC 63:0
2691`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_POSITION 0
2692`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ack_snd_seq_num"
2693`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_LOW_ADDR_WIDTH 0
2694`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_ADDR_RANGE 19:0
2695`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_READ_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2696`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2697`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2698`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2699`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2700`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2701`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2702`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_RMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2703`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111000000000000
2704`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2705`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000111111111111
2706`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_INTERNAL_REG 0
2707`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_EXTERNAL_DECODE_REG 0
2708`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_ALIASED_FROM 0
2709`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_ZERO_TIME_OMNI 0
2710`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_JTAG_RD 1
2711`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_JTAG_WR 1
2712`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_SBUS_RD 1
2713`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_SBUS_WR 1
2714`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_RAP_RD 1
2715`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_HW_ACC_RAP_WR 1
2716`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_NUM_FIELDS 1
2717`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_FID 0
2718`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_SLC 11:0
2719`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_WIDTH 12
2720`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_INT_SLC 11:0
2721`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_POSITION 0
2722`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2723`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2724`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_POR_VALUE 12'b111111111111
2725`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_ACK_SND_SEQ_NUM_SEQ_NUM_FIELD_NAME "seq_num"
2726
2727//-------------------------------------------------------
2728//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR
2729//-------------------------------------------------------
2730
2731`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ADDR 20'b11011100010010001011
2732`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_ADDR 30'b000000011011100010010001011000
2733`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_fifo_max_addr"
2734`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_WIDTH 64
2735`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_DEPTH 1
2736`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SLC 63:0
2737`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_INT_SLC 63:0
2738`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_POSITION 0
2739`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_fifo_max_addr"
2740`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_LOW_ADDR_WIDTH 0
2741`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_ADDR_RANGE 19:0
2742`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_READ_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2743`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2744`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2745`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2746`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2747`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2748`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2749`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_RMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2750`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111000000000000
2751`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2752`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000101010111
2753`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_INTERNAL_REG 0
2754`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_EXTERNAL_DECODE_REG 0
2755`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_ALIASED_FROM 0
2756`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_ZERO_TIME_OMNI 0
2757`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_JTAG_RD 1
2758`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_JTAG_WR 1
2759`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_SBUS_RD 1
2760`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_SBUS_WR 1
2761`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_RAP_RD 1
2762`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_HW_ACC_RAP_WR 1
2763`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_NUM_FIELDS 1
2764`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_FID 0
2765`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_SLC 11:0
2766`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_WIDTH 12
2767`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_INT_SLC 11:0
2768`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_POSITION 0
2769`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2770`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2771`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_POR_VALUE 12'b000101010111
2772`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_FIELD_NAME "seq_cnt_max_addr"
2773
2774//-------------------------------------------------------
2775//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR
2776//-------------------------------------------------------
2777
2778`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ADDR 20'b11011100010010001100
2779`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_ADDR 30'b000000011011100010010001100000
2780`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_fifo_ptr"
2781`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_WIDTH 64
2782`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_DEPTH 1
2783`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SLC 63:0
2784`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_INT_SLC 63:0
2785`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_POSITION 0
2786`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_fifo_ptr"
2787`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_LOW_ADDR_WIDTH 0
2788`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_ADDR_RANGE 19:0
2789`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_READ_MASK 64'b0000000000000000000000000000000000001111111111110000111111111111
2790`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2791`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_WRITE_MASK 64'b0000000000000000000000000000000000001111111111110000111111111111
2792`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2793`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2794`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2795`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2796`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_RMASK 64'b0000000000000000000000000000000000001111111111110000111111111111
2797`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111110000000000001111000000000000
2798`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_LD_MASK 64'b0000000000000000000000000000000000001111111111110000111111111111
2799`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_POR_VALUE 64'b0000000000000000000000000000000000001111111111110000000000000000
2800`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_INTERNAL_REG 0
2801`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_EXTERNAL_DECODE_REG 0
2802`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_ALIASED_FROM 0
2803`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_ZERO_TIME_OMNI 0
2804`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_JTAG_RD 1
2805`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_JTAG_WR 1
2806`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_SBUS_RD 1
2807`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_SBUS_WR 1
2808`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_RAP_RD 1
2809`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_HW_ACC_RAP_WR 1
2810`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_NUM_FIELDS 2
2811`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_FID 0
2812`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_SLC 27:16
2813`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_WIDTH 12
2814`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_INT_SLC 11:0
2815`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_POSITION 16
2816`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_FMASK 64'b0000000000000000000000000000000000001111111111110000000000000000
2817`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_HW_LD_MASK 64'b0000000000000000000000000000000000001111111111110000000000000000
2818`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_POR_VALUE 12'b111111111111
2819`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_TLPTR_FIELD_NAME "seq_cnt_tlptr"
2820`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_FID 1
2821`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_SLC 11:0
2822`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_WIDTH 12
2823`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_INT_SLC 11:0
2824`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_POSITION 0
2825`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2826`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2827`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_POR_VALUE 12'b000000000000
2828`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_FIFO_PTR_SEQ_CNT_HDPTR_FIELD_NAME "seq_cnt_hdptr"
2829
2830//-------------------------------------------------------
2831//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR
2832//-------------------------------------------------------
2833
2834`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ADDR 20'b11011100010010001101
2835`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_ADDR 30'b000000011011100010010001101000
2836`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_rw_ptr"
2837`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_WIDTH 64
2838`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_DEPTH 1
2839`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SLC 63:0
2840`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_INT_SLC 63:0
2841`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_POSITION 0
2842`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_cnt_rw_ptr"
2843`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_LOW_ADDR_WIDTH 0
2844`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_ADDR_RANGE 19:0
2845`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_READ_MASK 64'b0000000000000000000000000000000000001111111111110000111111111111
2846`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_READ_ONLY_MASK 64'b0000000000000000000000000000000000001111111111110000111111111111
2847`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2848`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2849`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2850`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2851`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2852`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_RMASK 64'b0000000000000000000000000000000000001111111111110000111111111111
2853`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111110000000000001111000000000000
2854`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_LD_MASK 64'b0000000000000000000000000000000000001111111111110000111111111111
2855`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
2856`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_INTERNAL_REG 0
2857`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_EXTERNAL_DECODE_REG 0
2858`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_ALIASED_FROM 0
2859`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_ZERO_TIME_OMNI 0
2860`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_JTAG_RD 1
2861`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_JTAG_WR 1
2862`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_SBUS_RD 1
2863`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_SBUS_WR 1
2864`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_RAP_RD 1
2865`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_HW_ACC_RAP_WR 1
2866`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_NUM_FIELDS 2
2867`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_FID 0
2868`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_SLC 27:16
2869`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_WIDTH 12
2870`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_INT_SLC 11:0
2871`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_POSITION 16
2872`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_FMASK 64'b0000000000000000000000000000000000001111111111110000000000000000
2873`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_HW_LD_MASK 64'b0000000000000000000000000000000000001111111111110000000000000000
2874`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_POR_VALUE 12'b000000000000
2875`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_WRPTR_FIELD_NAME "seq_cnt_wrptr"
2876`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_FID 1
2877`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_SLC 11:0
2878`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_WIDTH 12
2879`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_INT_SLC 11:0
2880`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_POSITION 0
2881`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2882`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
2883`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_POR_VALUE 12'b000000000000
2884`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_CNT_RW_PTR_SEQ_CNT_RDPTR_FIELD_NAME "seq_cnt_rdptr"
2885
2886//-------------------------------------------------------
2887//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL
2888//-------------------------------------------------------
2889
2890`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ADDR 20'b11011100010010001110
2891`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_ADDR 30'b000000011011100010010001110000
2892`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_tst_cntl"
2893`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_WIDTH 64
2894`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DEPTH 1
2895`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_SLC 63:0
2896`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_INT_SLC 63:0
2897`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_POSITION 0
2898`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_tst_cntl"
2899`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_LOW_ADDR_WIDTH 0
2900`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_ADDR_RANGE 19:0
2901`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111
2902`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2903`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
2904`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2905`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000111
2906`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2907`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2908`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_RMASK 64'b0000000000000000000000000000000000000000000000000000000000001111
2909`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111110000
2910`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111
2911`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
2912`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_INTERNAL_REG 0
2913`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_EXTERNAL_DECODE_REG 0
2914`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_ALIASED_FROM 0
2915`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_ZERO_TIME_OMNI 0
2916`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_JTAG_RD 1
2917`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_JTAG_WR 1
2918`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_SBUS_RD 1
2919`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_SBUS_WR 1
2920`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_RAP_RD 1
2921`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_HW_ACC_RAP_WR 1
2922`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_NUM_FIELDS 4
2923`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_FID 0
2924`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_SLC 3:3
2925`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_WIDTH 1
2926`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_INT_SLC 0:0
2927`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_POSITION 3
2928`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
2929`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
2930`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_POR_VALUE 1'b0
2931`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_DIS_ACK_FIELD_NAME "dis_ack"
2932`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_FID 1
2933`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_SLC 2:2
2934`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_WIDTH 1
2935`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_INT_SLC 0:0
2936`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_POSITION 2
2937`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
2938`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
2939`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_POR_VALUE 1'b0
2940`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_NAK_FIELD_NAME "force_nak"
2941`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_FID 2
2942`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_SLC 1:1
2943`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_WIDTH 1
2944`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_INT_SLC 0:0
2945`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_POSITION 1
2946`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
2947`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
2948`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_POR_VALUE 1'b0
2949`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_BAD_TLP_CRC_FIELD_NAME "force_bad_tlp_crc"
2950`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_FID 3
2951`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_SLC 0:0
2952`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_WIDTH 1
2953`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_INT_SLC 0:0
2954`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_POSITION 0
2955`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
2956`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
2957`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_POR_VALUE 1'b0
2958`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_TST_CNTL_FORCE_RTX_TLP_FIELD_NAME "force_rtx_tlp"
2959
2960//-------------------------------------------------------
2961//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL
2962//-------------------------------------------------------
2963
2964`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ADDR 20'b11011100010010010000
2965`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_ADDR 30'b000000011011100010010010000000
2966`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_addr_cntl"
2967`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_WIDTH 64
2968`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DEPTH 1
2969`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_SLC 63:0
2970`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_INT_SLC 63:0
2971`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_POSITION 0
2972`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_addr_cntl"
2973`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_LOW_ADDR_WIDTH 0
2974`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_ADDR_RANGE 19:0
2975`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_READ_MASK 64'b0000000000000000000000000000000011110000000000001111111111111111
2976`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2977`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_WRITE_MASK 64'b0000000000000000000000000000000000110000000000001111111111111111
2978`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2979`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_SET_MASK 64'b0000000000000000000000000000000001000000000000000000000000000000
2980`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_CLEAR_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
2981`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
2982`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RMASK 64'b0000000000000000000000000000000011110000000000001111111111111111
2983`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100001111111111110000000000000000
2984`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_LD_MASK 64'b0000000000000000000000000000000011000000000000000000000000000000
2985`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
2986`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_INTERNAL_REG 0
2987`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_EXTERNAL_DECODE_REG 0
2988`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_ALIASED_FROM 0
2989`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_ZERO_TIME_OMNI 0
2990`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_JTAG_RD 1
2991`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_JTAG_WR 1
2992`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_SBUS_RD 1
2993`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_SBUS_WR 1
2994`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_RAP_RD 1
2995`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_HW_ACC_RAP_WR 1
2996`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_NUM_FIELDS 5
2997`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_FID 0
2998`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_SLC 31:31
2999`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_WIDTH 1
3000`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_INT_SLC 0:0
3001`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_POSITION 31
3002`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
3003`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_HW_LD_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
3004`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_POR_VALUE 1'b0
3005`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_DONE_FIELD_NAME "done"
3006`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_FID 1
3007`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_SLC 30:30
3008`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_WIDTH 1
3009`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_INT_SLC 0:0
3010`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_POSITION 30
3011`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_FMASK 64'b0000000000000000000000000000000001000000000000000000000000000000
3012`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_HW_LD_MASK 64'b0000000000000000000000000000000001000000000000000000000000000000
3013`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_POR_VALUE 1'b0
3014`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_GO_BIT_FIELD_NAME "go_bit"
3015`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_FID 2
3016`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_SLC 29:29
3017`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_WIDTH 1
3018`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_INT_SLC 0:0
3019`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_POSITION 29
3020`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_FMASK 64'b0000000000000000000000000000000000100000000000000000000000000000
3021`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3022`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_POR_VALUE 1'b0
3023`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_RD_WR_SEL_FIELD_NAME "rd_wr_sel"
3024`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_FID 3
3025`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_SLC 28:28
3026`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_WIDTH 1
3027`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_INT_SLC 0:0
3028`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_POSITION 28
3029`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_FMASK 64'b0000000000000000000000000000000000010000000000000000000000000000
3030`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3031`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_POR_VALUE 1'b0
3032`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_FIFO_SEL_FIELD_NAME "fifo_sel"
3033`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_FID 4
3034`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_SLC 15:0
3035`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_WIDTH 16
3036`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_INT_SLC 15:0
3037`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_POSITION 0
3038`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3039`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3040`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_POR_VALUE 16'b0000000000000000
3041`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_ADDR_CNTL_MEM_ADDR_FIELD_NAME "mem_addr"
3042
3043//-------------------------------------------------------
3044//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0
3045//-------------------------------------------------------
3046
3047`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ADDR 20'b11011100010010010001
3048`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_ADDR 30'b000000011011100010010010001000
3049`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld0"
3050`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_WIDTH 64
3051`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_DEPTH 1
3052`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_SLC 63:0
3053`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_INT_SLC 63:0
3054`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_POSITION 0
3055`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld0"
3056`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_LOW_ADDR_WIDTH 0
3057`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_ADDR_RANGE 19:0
3058`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3059`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3060`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3061`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3062`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3063`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3064`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3065`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3066`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
3067`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3068`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3069`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_INTERNAL_REG 0
3070`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_EXTERNAL_DECODE_REG 0
3071`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_ALIASED_FROM 0
3072`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_ZERO_TIME_OMNI 0
3073`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_JTAG_RD 1
3074`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_JTAG_WR 1
3075`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_SBUS_RD 1
3076`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_SBUS_WR 1
3077`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_RAP_RD 1
3078`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_HW_ACC_RAP_WR 1
3079`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_NUM_FIELDS 1
3080`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_FID 0
3081`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_SLC 31:0
3082`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_WIDTH 32
3083`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_INT_SLC 31:0
3084`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_POSITION 0
3085`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3086`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3087`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_POR_VALUE 32'b00000000000000000000000000000000
3088`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD0_MEM_RD_WR_DATA0_FIELD_NAME "mem_rd_wr_data0"
3089
3090//-------------------------------------------------------
3091//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1
3092//-------------------------------------------------------
3093
3094`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ADDR 20'b11011100010010010010
3095`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_ADDR 30'b000000011011100010010010010000
3096`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld1"
3097`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_WIDTH 64
3098`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_DEPTH 1
3099`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_SLC 63:0
3100`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_INT_SLC 63:0
3101`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_POSITION 0
3102`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld1"
3103`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_LOW_ADDR_WIDTH 0
3104`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_ADDR_RANGE 19:0
3105`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3106`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3107`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3108`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3109`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3110`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3111`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3112`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3113`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
3114`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3115`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3116`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_INTERNAL_REG 0
3117`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_EXTERNAL_DECODE_REG 0
3118`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_ALIASED_FROM 0
3119`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_ZERO_TIME_OMNI 0
3120`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_JTAG_RD 1
3121`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_JTAG_WR 1
3122`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_SBUS_RD 1
3123`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_SBUS_WR 1
3124`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_RAP_RD 1
3125`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_HW_ACC_RAP_WR 1
3126`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_NUM_FIELDS 1
3127`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_FID 0
3128`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_SLC 31:0
3129`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_WIDTH 32
3130`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_INT_SLC 31:0
3131`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_POSITION 0
3132`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3133`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3134`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_POR_VALUE 32'b00000000000000000000000000000000
3135`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD1_MEM_RD_WR_DATA1_FIELD_NAME "mem_rd_wr_data1"
3136
3137//-------------------------------------------------------
3138//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2
3139//-------------------------------------------------------
3140
3141`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ADDR 20'b11011100010010010011
3142`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_ADDR 30'b000000011011100010010010011000
3143`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld2"
3144`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_WIDTH 64
3145`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_DEPTH 1
3146`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_SLC 63:0
3147`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_INT_SLC 63:0
3148`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_POSITION 0
3149`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld2"
3150`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_LOW_ADDR_WIDTH 0
3151`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_ADDR_RANGE 19:0
3152`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3153`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3154`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3155`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3156`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3157`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3158`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3159`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3160`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
3161`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3162`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3163`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_INTERNAL_REG 0
3164`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_EXTERNAL_DECODE_REG 0
3165`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_ALIASED_FROM 0
3166`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_ZERO_TIME_OMNI 0
3167`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_JTAG_RD 1
3168`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_JTAG_WR 1
3169`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_SBUS_RD 1
3170`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_SBUS_WR 1
3171`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_RAP_RD 1
3172`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_HW_ACC_RAP_WR 1
3173`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_NUM_FIELDS 1
3174`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_FID 0
3175`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_SLC 31:0
3176`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_WIDTH 32
3177`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_INT_SLC 31:0
3178`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_POSITION 0
3179`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3180`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3181`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_POR_VALUE 32'b00000000000000000000000000000000
3182`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD2_MEM_RD_WR_DATA2_FIELD_NAME "mem_rd_wr_data2"
3183
3184//-------------------------------------------------------
3185//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3
3186//-------------------------------------------------------
3187
3188`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ADDR 20'b11011100010010010100
3189`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_ADDR 30'b000000011011100010010010100000
3190`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld3"
3191`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_WIDTH 64
3192`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_DEPTH 1
3193`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_SLC 63:0
3194`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_INT_SLC 63:0
3195`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_POSITION 0
3196`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld3"
3197`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_LOW_ADDR_WIDTH 0
3198`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_ADDR_RANGE 19:0
3199`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3200`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3201`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3202`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3203`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3204`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3205`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3206`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3207`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
3208`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3209`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3210`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_INTERNAL_REG 0
3211`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_EXTERNAL_DECODE_REG 0
3212`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_ALIASED_FROM 0
3213`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_ZERO_TIME_OMNI 0
3214`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_JTAG_RD 1
3215`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_JTAG_WR 1
3216`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_SBUS_RD 1
3217`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_SBUS_WR 1
3218`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_RAP_RD 1
3219`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_HW_ACC_RAP_WR 1
3220`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_NUM_FIELDS 1
3221`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_FID 0
3222`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_SLC 31:0
3223`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_WIDTH 32
3224`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_INT_SLC 31:0
3225`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_POSITION 0
3226`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3227`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3228`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_POR_VALUE 32'b00000000000000000000000000000000
3229`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD3_MEM_RD_WR_DATA3_FIELD_NAME "mem_rd_wr_data3"
3230
3231//-------------------------------------------------------
3232//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4
3233//-------------------------------------------------------
3234
3235`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ADDR 20'b11011100010010010101
3236`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_ADDR 30'b000000011011100010010010101000
3237`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld4"
3238`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_WIDTH 64
3239`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_DEPTH 1
3240`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_SLC 63:0
3241`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_INT_SLC 63:0
3242`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_POSITION 0
3243`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_mem_ld4"
3244`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_LOW_ADDR_WIDTH 0
3245`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_ADDR_RANGE 19:0
3246`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3247`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3248`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_WRITE_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3249`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3250`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3251`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3252`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3253`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3254`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
3255`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3256`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3257`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_INTERNAL_REG 0
3258`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_EXTERNAL_DECODE_REG 0
3259`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_ALIASED_FROM 0
3260`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_ZERO_TIME_OMNI 0
3261`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_JTAG_RD 1
3262`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_JTAG_WR 1
3263`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_SBUS_RD 1
3264`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_SBUS_WR 1
3265`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_RAP_RD 1
3266`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_HW_ACC_RAP_WR 1
3267`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_NUM_FIELDS 1
3268`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_FID 0
3269`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_SLC 15:0
3270`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_WIDTH 16
3271`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_INT_SLC 15:0
3272`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_POSITION 0
3273`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3274`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3275`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_POR_VALUE 16'b0000000000000000
3276`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_MEM_LD4_MEM_RD_WR_DATA4_FIELD_NAME "mem_rd_wr_data4"
3277
3278//-------------------------------------------------------
3279//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT
3280//-------------------------------------------------------
3281
3282`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ADDR 20'b11011100010010011000
3283`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_ADDR 30'b000000011011100010010011000000
3284`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_cnt"
3285`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_WIDTH 64
3286`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_DEPTH 1
3287`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_SLC 63:0
3288`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_INT_SLC 63:0
3289`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_POSITION 0
3290`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rtry_cnt"
3291`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_LOW_ADDR_WIDTH 0
3292`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_ADDR_RANGE 19:0
3293`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3294`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3295`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3296`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3297`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3298`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3299`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3300`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3301`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
3302`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3303`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3304`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_INTERNAL_REG 0
3305`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_EXTERNAL_DECODE_REG 0
3306`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_ALIASED_FROM 0
3307`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_ZERO_TIME_OMNI 0
3308`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_JTAG_RD 1
3309`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_JTAG_WR 1
3310`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_SBUS_RD 1
3311`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_SBUS_WR 1
3312`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_RAP_RD 1
3313`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_HW_ACC_RAP_WR 1
3314`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_NUM_FIELDS 1
3315`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_FID 0
3316`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_SLC 15:0
3317`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_WIDTH 16
3318`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_INT_SLC 15:0
3319`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_POSITION 0
3320`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3321`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
3322`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_POR_VALUE 16'b0000000000000000
3323`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RTRY_CNT_RTRY_DATA_CNT_FIELD_NAME "rtry_data_cnt"
3324
3325//-------------------------------------------------------
3326//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT
3327//-------------------------------------------------------
3328
3329`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ADDR 20'b11011100010010011001
3330`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_ADDR 30'b000000011011100010010011001000
3331`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_buff_cnt"
3332`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_WIDTH 64
3333`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_DEPTH 1
3334`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SLC 63:0
3335`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_INT_SLC 63:0
3336`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_POSITION 0
3337`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_buff_cnt"
3338`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_LOW_ADDR_WIDTH 0
3339`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_ADDR_RANGE 19:0
3340`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_READ_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3341`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3342`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3343`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3344`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3345`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3346`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3347`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_RMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3348`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111000000000000
3349`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3350`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3351`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_INTERNAL_REG 0
3352`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_EXTERNAL_DECODE_REG 0
3353`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_ALIASED_FROM 0
3354`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_ZERO_TIME_OMNI 0
3355`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_JTAG_RD 1
3356`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_JTAG_WR 1
3357`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_SBUS_RD 1
3358`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_SBUS_WR 1
3359`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_RAP_RD 1
3360`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_HW_ACC_RAP_WR 1
3361`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_NUM_FIELDS 1
3362`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_FID 0
3363`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_SLC 11:0
3364`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_WIDTH 12
3365`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_INT_SLC 11:0
3366`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_POSITION 0
3367`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3368`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3369`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_POR_VALUE 12'b000000000000
3370`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_CNT_SEQ_BUFF_CNT_FIELD_NAME "seq_buff_cnt"
3371
3372//-------------------------------------------------------
3373//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM
3374//-------------------------------------------------------
3375
3376`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ADDR 20'b11011100010010011010
3377`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_ADDR 30'b000000011011100010010011010000
3378`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_buff_btm"
3379`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_WIDTH 64
3380`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_DEPTH 1
3381`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SLC 63:0
3382`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_INT_SLC 63:0
3383`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_POSITION 0
3384`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_seq_buff_btm"
3385`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_LOW_ADDR_WIDTH 0
3386`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_ADDR_RANGE 19:0
3387`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_READ_MASK 64'b0000000000000000000000000000000001111111111111111111111111111111
3388`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3389`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_WRITE_MASK 64'b0000000000000000000000000000000001111111111111111111111111111111
3390`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3391`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3392`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3393`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3394`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_RMASK 64'b0000000000000000000000000000000001111111111111111111111111111111
3395`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_RESERVED_BIT_MASK 64'b1111111111111111111111111111111110000000000000000000000000000000
3396`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_LD_MASK 64'b0000000000000000000000000000000001111111111111111111111111111111
3397`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3398`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_INTERNAL_REG 0
3399`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_EXTERNAL_DECODE_REG 0
3400`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_ALIASED_FROM 0
3401`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_ZERO_TIME_OMNI 0
3402`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_JTAG_RD 1
3403`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_JTAG_WR 1
3404`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_SBUS_RD 1
3405`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_SBUS_WR 1
3406`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_RAP_RD 1
3407`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_HW_ACC_RAP_WR 1
3408`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_NUM_FIELDS 4
3409`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_FID 0
3410`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_SLC 30:30
3411`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_WIDTH 1
3412`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_INT_SLC 0:0
3413`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_POSITION 30
3414`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_FMASK 64'b0000000000000000000000000000000001000000000000000000000000000000
3415`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_HW_LD_MASK 64'b0000000000000000000000000000000001000000000000000000000000000000
3416`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_POR_VALUE 1'b0
3417`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBUF_BDATA_PAR_FIELD_NAME "sbuf_bdata_par"
3418`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_FID 1
3419`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_SLC 29:18
3420`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_WIDTH 12
3421`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_INT_SLC 11:0
3422`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_POSITION 18
3423`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_FMASK 64'b0000000000000000000000000000000000111111111111000000000000000000
3424`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000111111111111000000000000000000
3425`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_POR_VALUE 12'b000000000000
3426`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_SEQ_NUM_FIELD_NAME "sbdata_seq_num"
3427`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_FID 2
3428`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_SLC 17:2
3429`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_WIDTH 16
3430`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_INT_SLC 15:0
3431`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_POSITION 2
3432`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_FMASK 64'b0000000000000000000000000000000000000000000000111111111111111100
3433`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000111111111111111100
3434`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_POR_VALUE 16'b0000000000000000
3435`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_RTRY_PTR_FIELD_NAME "sbdata_rtry_ptr"
3436`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_FID 3
3437`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_SLC 1:0
3438`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_WIDTH 2
3439`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_INT_SLC 1:0
3440`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_POSITION 0
3441`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011
3442`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
3443`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_POR_VALUE 2'b00
3444`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_SEQ_BUFF_BTM_SBDATA_EOP_POS_FIELD_NAME "sbdata_eop_pos"
3445
3446//-------------------------------------------------------
3447//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR
3448//-------------------------------------------------------
3449
3450`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ADDR 20'b11011100010010100000
3451`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_ADDR 30'b000000011011100010010100000000
3452`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_nxt_rcv_seq_cntr"
3453`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_WIDTH 64
3454`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_DEPTH 1
3455`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_SLC 63:0
3456`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_INT_SLC 63:0
3457`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_POSITION 0
3458`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_nxt_rcv_seq_cntr"
3459`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_LOW_ADDR_WIDTH 0
3460`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_ADDR_RANGE 19:0
3461`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_READ_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3462`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3463`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3464`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3465`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3466`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3467`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3468`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_RMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3469`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111000000000000
3470`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3471`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000001
3472`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_INTERNAL_REG 0
3473`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_EXTERNAL_DECODE_REG 0
3474`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_ALIASED_FROM 0
3475`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_ZERO_TIME_OMNI 0
3476`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_JTAG_RD 1
3477`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_JTAG_WR 1
3478`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_SBUS_RD 1
3479`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_SBUS_WR 1
3480`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_RAP_RD 1
3481`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_HW_ACC_RAP_WR 1
3482`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NUM_FIELDS 1
3483`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_FID 0
3484`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_SLC 11:0
3485`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_WIDTH 12
3486`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_INT_SLC 11:0
3487`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_POSITION 0
3488`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3489`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
3490`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_POR_VALUE 12'b000000000001
3491`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_NXT_RCV_SEQ_CNTR_NXT_RX_SEQ_CNTR_FIELD_NAME "nxt_rx_seq_cntr"
3492
3493//-------------------------------------------------------
3494//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD
3495//-------------------------------------------------------
3496
3497`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ADDR 20'b11011100010010100001
3498`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_ADDR 30'b000000011011100010010100001000
3499`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dllp_rcvd"
3500`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_WIDTH 64
3501`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_DEPTH 1
3502`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_SLC 63:0
3503`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_INT_SLC 63:0
3504`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_POSITION 0
3505`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_dllp_rcvd"
3506`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_LOW_ADDR_WIDTH 0
3507`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_ADDR_RANGE 19:0
3508`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3509`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_READ_ONLY_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3510`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3511`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3512`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3513`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3514`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3515`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3516`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
3517`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3518`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3519`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_INTERNAL_REG 0
3520`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_EXTERNAL_DECODE_REG 0
3521`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_ALIASED_FROM 0
3522`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_ZERO_TIME_OMNI 0
3523`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_JTAG_RD 1
3524`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_JTAG_WR 1
3525`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_SBUS_RD 1
3526`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_SBUS_WR 1
3527`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_RAP_RD 1
3528`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_HW_ACC_RAP_WR 1
3529`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_NUM_FIELDS 4
3530`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_FID 0
3531`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_SLC 31:24
3532`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_WIDTH 8
3533`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_INT_SLC 7:0
3534`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_POSITION 24
3535`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_FMASK 64'b0000000000000000000000000000000011111111000000000000000000000000
3536`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3537`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_POR_VALUE 8'b00000000
3538`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE3_FIELD_NAME "byte3"
3539`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_FID 1
3540`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_SLC 23:16
3541`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_WIDTH 8
3542`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_INT_SLC 7:0
3543`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_POSITION 16
3544`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_FMASK 64'b0000000000000000000000000000000000000000111111110000000000000000
3545`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3546`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_POR_VALUE 8'b00000000
3547`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE2_FIELD_NAME "byte2"
3548`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_FID 2
3549`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_SLC 15:8
3550`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_WIDTH 8
3551`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_INT_SLC 7:0
3552`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_POSITION 8
3553`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_FMASK 64'b0000000000000000000000000000000000000000000000001111111100000000
3554`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3555`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_POR_VALUE 8'b00000000
3556`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE1_FIELD_NAME "byte1"
3557`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_FID 3
3558`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_SLC 7:0
3559`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_WIDTH 8
3560`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_INT_SLC 7:0
3561`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_POSITION 0
3562`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
3563`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3564`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_POR_VALUE 8'b00000000
3565`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_DLLP_RCVD_BYTE0_FIELD_NAME "byte0"
3566
3567//-------------------------------------------------------
3568//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL
3569//-------------------------------------------------------
3570
3571`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ADDR 20'b11011100010010100010
3572`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_ADDR 30'b000000011011100010010100010000
3573`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_link_test_cntl"
3574`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_WIDTH 64
3575`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_DEPTH 1
3576`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_SLC 63:0
3577`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_INT_SLC 63:0
3578`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_POSITION 0
3579`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_link_test_cntl"
3580`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_LOW_ADDR_WIDTH 0
3581`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_ADDR_RANGE 19:0
3582`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
3583`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3584`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
3585`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3586`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3587`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3588`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3589`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011
3590`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100
3591`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3592`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3593`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_INTERNAL_REG 0
3594`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_EXTERNAL_DECODE_REG 0
3595`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_ALIASED_FROM 0
3596`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_ZERO_TIME_OMNI 0
3597`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_JTAG_RD 1
3598`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_JTAG_WR 1
3599`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_SBUS_RD 1
3600`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_SBUS_WR 1
3601`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_RAP_RD 1
3602`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_HW_ACC_RAP_WR 1
3603`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_NUM_FIELDS 2
3604`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_FID 0
3605`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_SLC 1:1
3606`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_WIDTH 1
3607`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_INT_SLC 0:0
3608`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_POSITION 1
3609`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
3610`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3611`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_POR_VALUE 1'b0
3612`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_SEND_INIT_FC_DLLP_FIELD_NAME "force_send_init_fc_dllp"
3613`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_FID 1
3614`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_SLC 0:0
3615`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_WIDTH 1
3616`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_INT_SLC 0:0
3617`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_POSITION 0
3618`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
3619`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3620`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_POR_VALUE 1'b0
3621`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_LINK_TEST_CNTL_FORCE_PAR_ERR_DLLP_FIELD_NAME "force_par_err_dllp"
3622
3623//-------------------------------------------------------
3624//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG
3625//-------------------------------------------------------
3626
3627`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ADDR 20'b11011100010011000000
3628`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_ADDR 30'b000000011011100010011000000000
3629`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_cnfg"
3630`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_WIDTH 64
3631`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_DEPTH 1
3632`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_SLC 63:0
3633`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_INT_SLC 63:0
3634`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_POSITION 0
3635`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_cnfg"
3636`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_LOW_ADDR_WIDTH 0
3637`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_ADDR_RANGE 19:0
3638`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3639`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3640`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3641`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3642`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3643`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3644`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3645`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
3646`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
3647`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_LD_MASK 64'b0000000000000000000000000000000000010000000000000000000000000000
3648`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000010000
3649`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_INTERNAL_REG 0
3650`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_EXTERNAL_DECODE_REG 0
3651`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_ALIASED_FROM 0
3652`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_ZERO_TIME_OMNI 0
3653`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_JTAG_RD 1
3654`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_JTAG_WR 1
3655`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_SBUS_RD 1
3656`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_SBUS_WR 1
3657`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_RAP_RD 1
3658`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_HW_ACC_RAP_WR 1
3659`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_NUM_FIELDS 13
3660`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_FID 0
3661`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_SLC 31:31
3662`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_WIDTH 1
3663`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_INT_SLC 0:0
3664`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_POSITION 31
3665`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
3666`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3667`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_POR_VALUE 1'b0
3668`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_PHY_TST_EN_FIELD_NAME "phy_tst_en"
3669`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_FID 1
3670`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_SLC 30:30
3671`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_WIDTH 1
3672`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_INT_SLC 0:0
3673`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_POSITION 30
3674`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_FMASK 64'b0000000000000000000000000000000001000000000000000000000000000000
3675`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3676`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_POR_VALUE 1'b0
3677`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FAST_SIM_FIELD_NAME "fast_sim"
3678`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_FID 2
3679`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_SLC 29:29
3680`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_WIDTH 1
3681`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_INT_SLC 0:0
3682`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_POSITION 29
3683`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_FMASK 64'b0000000000000000000000000000000000100000000000000000000000000000
3684`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3685`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_POR_VALUE 1'b0
3686`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_DIS_SCRAM_FIELD_NAME "frce_dis_scram"
3687`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_FID 3
3688`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_SLC 28:28
3689`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_WIDTH 1
3690`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_INT_SLC 0:0
3691`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_POSITION 28
3692`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_FMASK 64'b0000000000000000000000000000000000010000000000000000000000000000
3693`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_HW_LD_MASK 64'b0000000000000000000000000000000000010000000000000000000000000000
3694`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_POR_VALUE 1'b0
3695`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_FRCE_EXTEN_SYNC_FIELD_NAME "frce_exten_sync"
3696`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_FID 4
3697`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_SLC 27:12
3698`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_WIDTH 16
3699`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_INT_SLC 15:0
3700`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_POSITION 12
3701`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_FMASK 64'b0000000000000000000000000000000000001111111111111111000000000000
3702`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3703`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_POR_VALUE 16'b0000000000000000
3704`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL2_FIELD_NAME "unused_cntl2"
3705`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_FID 5
3706`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_SLC 11:11
3707`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_WIDTH 1
3708`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_INT_SLC 0:0
3709`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_POSITION 11
3710`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
3711`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3712`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_POR_VALUE 1'b0
3713`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_EIDLE_POST_EN_FIELD_NAME "tx_eidle_post_en"
3714`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_FID 6
3715`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_SLC 10:8
3716`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_WIDTH 3
3717`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_INT_SLC 2:0
3718`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_POSITION 8
3719`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_FMASK 64'b0000000000000000000000000000000000000000000000000000011100000000
3720`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3721`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_POR_VALUE 3'b000
3722`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_POST_VAL_FIELD_NAME "tx_os_post_val"
3723`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_FID 7
3724`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_SLC 7:7
3725`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_WIDTH 1
3726`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_INT_SLC 0:0
3727`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_POSITION 7
3728`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
3729`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3730`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_POR_VALUE 1'b0
3731`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_BYTE_SEL_FIELD_NAME "tx_os_byte_sel"
3732`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_FID 8
3733`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_SLC 6:4
3734`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_WIDTH 3
3735`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_INT_SLC 2:0
3736`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_POSITION 4
3737`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_FMASK 64'b0000000000000000000000000000000000000000000000000000000001110000
3738`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3739`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_POR_VALUE 3'b001
3740`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_OS_PREAM_VAL_FIELD_NAME "tx_os_pream_val"
3741`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_FID 9
3742`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_SLC 3:3
3743`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_WIDTH 1
3744`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_INT_SLC 0:0
3745`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_POSITION 3
3746`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
3747`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3748`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_POR_VALUE 1'b0
3749`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_BYP_MODE_FIELD_NAME "tx_rdet_byp_mode"
3750`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_FID 10
3751`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_SLC 2:2
3752`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_WIDTH 1
3753`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_INT_SLC 0:0
3754`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_POSITION 2
3755`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
3756`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3757`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_POR_VALUE 1'b0
3758`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_RDET_SAFE_MODE_FIELD_NAME "tx_rdet_safe_mode"
3759`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_FID 11
3760`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_SLC 1:1
3761`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_WIDTH 1
3762`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_INT_SLC 0:0
3763`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_POSITION 1
3764`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
3765`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3766`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_POR_VALUE 1'b0
3767`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_UNUSED_CNTL1_FIELD_NAME "unused_cntl1"
3768`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_FID 12
3769`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_SLC 0:0
3770`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_WIDTH 1
3771`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_INT_SLC 0:0
3772`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_POSITION 0
3773`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
3774`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3775`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_POR_VALUE 1'b0
3776`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_CNFG_TX_PAR_ERR_FIELD_NAME "tx_par_err"
3777
3778//-------------------------------------------------------
3779//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT
3780//-------------------------------------------------------
3781
3782`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ADDR 20'b11011100010011000001
3783`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_ADDR 30'b000000011011100010011000001000
3784`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_stat"
3785`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_WIDTH 64
3786`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_DEPTH 1
3787`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_SLC 63:0
3788`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_INT_SLC 63:0
3789`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_POSITION 0
3790`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_stat"
3791`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_LOW_ADDR_WIDTH 0
3792`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_ADDR_RANGE 19:0
3793`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
3794`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
3795`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3796`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3797`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3798`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3799`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3800`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
3801`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111110
3802`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3803`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3804`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_INTERNAL_REG 0
3805`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_EXTERNAL_DECODE_REG 0
3806`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_ALIASED_FROM 0
3807`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_ZERO_TIME_OMNI 0
3808`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_JTAG_RD 1
3809`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_JTAG_WR 1
3810`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_SBUS_RD 1
3811`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_SBUS_WR 1
3812`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_RAP_RD 1
3813`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_HW_ACC_RAP_WR 1
3814`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_NUM_FIELDS 1
3815`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_FID 0
3816`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_SLC 0:0
3817`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_WIDTH 1
3818`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_INT_SLC 0:0
3819`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_POSITION 0
3820`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
3821`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3822`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_POR_VALUE 1'b0
3823`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_STAT_RSVDP_FIELD_NAME "rsvdp"
3824
3825//-------------------------------------------------------
3826//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT
3827//-------------------------------------------------------
3828
3829`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ADDR 20'b11011100010011000010
3830`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_ADDR 30'b000000011011100010011000010000
3831`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_int"
3832`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_WIDTH 64
3833`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_DEPTH 1
3834`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_SLC 63:0
3835`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SLC 63:0
3836`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_POSITION 0
3837`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_int"
3838`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_LOW_ADDR_WIDTH 0
3839`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_ADDR_RANGE 19:0
3840`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_READ_MASK 64'b0000000000000000000000000000000010000000000000000011111111111111
3841`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_READ_ONLY_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
3842`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3843`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3844`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3845`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000011111111111111
3846`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3847`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_RMASK 64'b0000000000000000000000000000000010000000000000000011111111111111
3848`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111100000000000000
3849`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000011111111111111
3850`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
3851`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INTERNAL_REG 0
3852`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_EXTERNAL_DECODE_REG 0
3853`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_ALIASED_FROM 0
3854`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_ZERO_TIME_OMNI 0
3855`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_JTAG_RD 1
3856`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_JTAG_WR 1
3857`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_SBUS_RD 1
3858`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_SBUS_WR 1
3859`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_RAP_RD 1
3860`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_HW_ACC_RAP_WR 1
3861`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_NUM_FIELDS 15
3862`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_FID 0
3863`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_SLC 31:31
3864`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_WIDTH 1
3865`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_INT_SLC 0:0
3866`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_POSITION 31
3867`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
3868`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
3869`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_POR_VALUE 1'b0
3870`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_PHY_LAYER_ERR_FIELD_NAME "int_phy_layer_err"
3871`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_FID 1
3872`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_SLC 13:13
3873`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_WIDTH 1
3874`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_INT_SLC 0:0
3875`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_POSITION 13
3876`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
3877`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000010000000000000
3878`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_POR_VALUE 1'b0
3879`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_NON_CONS_ES_ERR_FIELD_NAME "int_non_cons_es_err"
3880`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_FID 2
3881`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_SLC 12:12
3882`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_WIDTH 1
3883`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_INT_SLC 0:0
3884`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_POSITION 12
3885`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
3886`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001000000000000
3887`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_POR_VALUE 1'b0
3888`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ENDS_SYM_TM_ERR_FIELD_NAME "int_ends_sym_tm_err"
3889`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_FID 3
3890`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_SLC 11:11
3891`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_WIDTH 1
3892`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_INT_SLC 0:0
3893`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_POSITION 11
3894`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
3895`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000100000000000
3896`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_POR_VALUE 1'b0
3897`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_KCHAR_DLLP_ERR_FIELD_NAME "int_kchar_dllp_err"
3898`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_FID 4
3899`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_SLC 10:10
3900`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_WIDTH 1
3901`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_INT_SLC 0:0
3902`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_POSITION 10
3903`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
3904`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
3905`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_POR_VALUE 1'b0
3906`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_END_POS_ERR_FIELD_NAME "int_ill_end_pos_err"
3907`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_FID 5
3908`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_SLC 9:9
3909`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_WIDTH 1
3910`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_INT_SLC 0:0
3911`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_POSITION 9
3912`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
3913`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
3914`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_POR_VALUE 1'b0
3915`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_LNK_ERR_FIELD_NAME "int_lnk_err"
3916`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_FID 6
3917`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_SLC 8:8
3918`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_WIDTH 1
3919`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_INT_SLC 0:0
3920`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_POSITION 8
3921`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
3922`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
3923`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_POR_VALUE 1'b0
3924`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_TRN_ERR_FIELD_NAME "int_trn_err"
3925`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_FID 7
3926`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_SLC 7:7
3927`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_WIDTH 1
3928`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_INT_SLC 0:0
3929`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_POSITION 7
3930`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
3931`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
3932`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_POR_VALUE 1'b0
3933`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_EDB_DET_FIELD_NAME "int_edb_det"
3934`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_FID 8
3935`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_SLC 6:6
3936`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_WIDTH 1
3937`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_INT_SLC 0:0
3938`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_POSITION 6
3939`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
3940`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
3941`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_POR_VALUE 1'b0
3942`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_SDP_END_FIELD_NAME "int_sdp_end"
3943`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_FID 9
3944`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_SLC 5:5
3945`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_WIDTH 1
3946`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_INT_SLC 0:0
3947`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_POSITION 5
3948`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
3949`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
3950`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_POR_VALUE 1'b0
3951`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_STP_END_EDB_FIELD_NAME "int_stp_end_edb"
3952`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_FID 10
3953`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_SLC 4:4
3954`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_WIDTH 1
3955`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_INT_SLC 0:0
3956`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_POSITION 4
3957`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
3958`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
3959`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_POR_VALUE 1'b0
3960`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_PAD_POS_FIELD_NAME "int_ill_pad_pos"
3961`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_FID 11
3962`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_SLC 3:3
3963`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_WIDTH 1
3964`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_INT_SLC 0:0
3965`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_POSITION 3
3966`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
3967`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
3968`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_POR_VALUE 1'b0
3969`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_SDP_FIELD_NAME "int_multi_sdp"
3970`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_FID 12
3971`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_SLC 2:2
3972`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_WIDTH 1
3973`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_INT_SLC 0:0
3974`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_POSITION 2
3975`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
3976`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
3977`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_POR_VALUE 1'b0
3978`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_MULTI_STP_FIELD_NAME "int_multi_stp"
3979`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_FID 13
3980`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_SLC 1:1
3981`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_WIDTH 1
3982`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_INT_SLC 0:0
3983`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_POSITION 1
3984`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
3985`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
3986`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_POR_VALUE 1'b0
3987`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_SDP_POS_FIELD_NAME "int_ill_sdp_pos"
3988`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_FID 14
3989`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_SLC 0:0
3990`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_WIDTH 1
3991`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_INT_SLC 0:0
3992`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_POSITION 0
3993`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
3994`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
3995`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_POR_VALUE 1'b0
3996`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_INT_INT_ILL_STP_POS_FIELD_NAME "int_ill_stp_pos"
3997
3998//-------------------------------------------------------
3999//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST
4000//-------------------------------------------------------
4001
4002`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ADDR 20'b11011100010011000011
4003`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_ADDR 30'b000000011011100010011000011000
4004`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_tst"
4005`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_WIDTH 64
4006`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_DEPTH 1
4007`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_SLC 63:0
4008`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_INT_SLC 63:0
4009`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_POSITION 0
4010`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_tst"
4011`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_LOW_ADDR_WIDTH 0
4012`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_ADDR_RANGE 19:0
4013`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_READ_MASK 64'b0000000000000000000000000000000000000000000000000011111111111111
4014`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4015`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4016`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4017`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_SET_MASK 64'b0000000000000000000000000000000000000000000000000011111111111111
4018`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4019`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4020`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_RMASK 64'b0000000000000000000000000000000000000000000000000011111111111111
4021`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111100000000000000
4022`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000011111111111111
4023`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
4024`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_INTERNAL_REG 0
4025`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_EXTERNAL_DECODE_REG 0
4026`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_ALIASED_FROM 0
4027`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_ZERO_TIME_OMNI 0
4028`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_JTAG_RD 1
4029`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_JTAG_WR 1
4030`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_SBUS_RD 1
4031`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_SBUS_WR 1
4032`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_RAP_RD 1
4033`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_HW_ACC_RAP_WR 1
4034`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_NUM_FIELDS 14
4035`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_FID 0
4036`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_SLC 13:13
4037`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_WIDTH 1
4038`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_INT_SLC 0:0
4039`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_POSITION 13
4040`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
4041`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000010000000000000
4042`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_POR_VALUE 1'b0
4043`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_NON_CONS_ES_ERR_FIELD_NAME "tst_non_cons_es_err"
4044`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_FID 1
4045`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_SLC 12:12
4046`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_WIDTH 1
4047`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_INT_SLC 0:0
4048`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_POSITION 12
4049`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
4050`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001000000000000
4051`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_POR_VALUE 1'b0
4052`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ENDS_SYM_TM_ERR_FIELD_NAME "tst_ends_sym_tm_err"
4053`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_FID 2
4054`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_SLC 11:11
4055`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_WIDTH 1
4056`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_INT_SLC 0:0
4057`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_POSITION 11
4058`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
4059`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000100000000000
4060`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_POR_VALUE 1'b0
4061`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_KCHAR_DLLP_ERR_FIELD_NAME "tst_kchar_dllp_err"
4062`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_FID 3
4063`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_SLC 10:10
4064`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_WIDTH 1
4065`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_INT_SLC 0:0
4066`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_POSITION 10
4067`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
4068`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
4069`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_POR_VALUE 1'b0
4070`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_END_POS_ERR_FIELD_NAME "tst_ill_end_pos_err"
4071`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_FID 4
4072`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_SLC 9:9
4073`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_WIDTH 1
4074`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_INT_SLC 0:0
4075`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_POSITION 9
4076`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
4077`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
4078`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_POR_VALUE 1'b0
4079`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_LNK_ERR_FIELD_NAME "tst_lnk_err"
4080`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_FID 5
4081`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_SLC 8:8
4082`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_WIDTH 1
4083`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_INT_SLC 0:0
4084`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_POSITION 8
4085`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
4086`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
4087`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_POR_VALUE 1'b0
4088`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_TRN_ERR_FIELD_NAME "tst_trn_err"
4089`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_FID 6
4090`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_SLC 7:7
4091`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_WIDTH 1
4092`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_INT_SLC 0:0
4093`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_POSITION 7
4094`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
4095`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
4096`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_POR_VALUE 1'b0
4097`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_EDB_DET_FIELD_NAME "tst_edb_det"
4098`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_FID 7
4099`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_SLC 6:6
4100`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_WIDTH 1
4101`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_INT_SLC 0:0
4102`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_POSITION 6
4103`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
4104`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
4105`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_POR_VALUE 1'b0
4106`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_SDP_END_FIELD_NAME "tst_sdp_end"
4107`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_FID 8
4108`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_SLC 5:5
4109`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_WIDTH 1
4110`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_INT_SLC 0:0
4111`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_POSITION 5
4112`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
4113`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
4114`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_POR_VALUE 1'b0
4115`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_STP_END_EDB_FIELD_NAME "tst_stp_end_edb"
4116`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_FID 9
4117`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_SLC 4:4
4118`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_WIDTH 1
4119`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_INT_SLC 0:0
4120`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_POSITION 4
4121`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
4122`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
4123`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_POR_VALUE 1'b0
4124`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_PAD_POS_FIELD_NAME "tst_ill_pad_pos"
4125`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_FID 10
4126`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_SLC 3:3
4127`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_WIDTH 1
4128`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_INT_SLC 0:0
4129`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_POSITION 3
4130`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
4131`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
4132`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_POR_VALUE 1'b0
4133`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_SDP_FIELD_NAME "tst_multi_sdp"
4134`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_FID 11
4135`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_SLC 2:2
4136`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_WIDTH 1
4137`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_INT_SLC 0:0
4138`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_POSITION 2
4139`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
4140`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
4141`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_POR_VALUE 1'b0
4142`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_MULTI_STP_FIELD_NAME "tst_multi_stp"
4143`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_FID 12
4144`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_SLC 1:1
4145`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_WIDTH 1
4146`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_INT_SLC 0:0
4147`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_POSITION 1
4148`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
4149`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
4150`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_POR_VALUE 1'b0
4151`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_SDP_POS_FIELD_NAME "tst_ill_sdp_pos"
4152`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_FID 13
4153`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_SLC 0:0
4154`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_WIDTH 1
4155`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_INT_SLC 0:0
4156`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_POSITION 0
4157`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
4158`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
4159`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_POR_VALUE 1'b0
4160`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_TST_TST_ILL_STP_POS_FIELD_NAME "tst_ill_stp_pos"
4161
4162//-------------------------------------------------------
4163//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK
4164//-------------------------------------------------------
4165
4166`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ADDR 20'b11011100010011000100
4167`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_ADDR 30'b000000011011100010011000100000
4168`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_msk"
4169`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_WIDTH 64
4170`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_DEPTH 1
4171`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_SLC 63:0
4172`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_INT_SLC 63:0
4173`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_POSITION 0
4174`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_phy_err_msk"
4175`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_LOW_ADDR_WIDTH 0
4176`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_ADDR_RANGE 19:0
4177`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_READ_MASK 64'b0000000000000000000000000000000010000000000000000000111111111111
4178`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4179`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_WRITE_MASK 64'b0000000000000000000000000000000010000000000000000000111111111111
4180`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4181`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4182`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4183`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4184`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_RMASK 64'b0000000000000000000000000000000010000000000000000000111111111111
4185`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111111000000000000
4186`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4187`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
4188`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_INTERNAL_REG 0
4189`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_EXTERNAL_DECODE_REG 0
4190`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_ALIASED_FROM 0
4191`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_ZERO_TIME_OMNI 0
4192`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_JTAG_RD 1
4193`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_JTAG_WR 1
4194`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_SBUS_RD 1
4195`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_SBUS_WR 1
4196`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_RAP_RD 1
4197`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_HW_ACC_RAP_WR 1
4198`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_NUM_FIELDS 13
4199`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_FID 0
4200`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_SLC 31:31
4201`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_WIDTH 1
4202`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_INT_SLC 0:0
4203`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_POSITION 31
4204`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
4205`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4206`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_POR_VALUE 1'b0
4207`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_PHY_LAYER_ERR_FIELD_NAME "msk_phy_layer_err"
4208`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_FID 1
4209`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_SLC 11:11
4210`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_WIDTH 1
4211`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_INT_SLC 0:0
4212`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_POSITION 11
4213`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
4214`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4215`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_POR_VALUE 1'b0
4216`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_KCHAR_DLLP_ERR_FIELD_NAME "msk_kchar_dllp_err"
4217`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_FID 2
4218`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_SLC 10:10
4219`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_WIDTH 1
4220`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_INT_SLC 0:0
4221`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_POSITION 10
4222`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
4223`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4224`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_POR_VALUE 1'b0
4225`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_END_POS_ERR_FIELD_NAME "msk_ill_end_pos_err"
4226`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_FID 3
4227`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_SLC 9:9
4228`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_WIDTH 1
4229`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_INT_SLC 0:0
4230`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_POSITION 9
4231`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
4232`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4233`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_POR_VALUE 1'b0
4234`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_LNK_ERR_FIELD_NAME "msk_lnk_err"
4235`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_FID 4
4236`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_SLC 8:8
4237`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_WIDTH 1
4238`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_INT_SLC 0:0
4239`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_POSITION 8
4240`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
4241`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4242`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_POR_VALUE 1'b0
4243`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_TRN_ERR_FIELD_NAME "msk_trn_err"
4244`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_FID 5
4245`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_SLC 7:7
4246`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_WIDTH 1
4247`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_INT_SLC 0:0
4248`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_POSITION 7
4249`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
4250`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4251`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_POR_VALUE 1'b0
4252`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_EDB_DET_FIELD_NAME "msk_edb_det"
4253`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_FID 6
4254`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_SLC 6:6
4255`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_WIDTH 1
4256`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_INT_SLC 0:0
4257`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_POSITION 6
4258`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
4259`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4260`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_POR_VALUE 1'b0
4261`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_SDP_END_FIELD_NAME "msk_sdp_end"
4262`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_FID 7
4263`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_SLC 5:5
4264`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_WIDTH 1
4265`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_INT_SLC 0:0
4266`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_POSITION 5
4267`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
4268`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4269`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_POR_VALUE 1'b0
4270`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_STP_END_EDB_FIELD_NAME "msk_stp_end_edb"
4271`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_FID 8
4272`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_SLC 4:4
4273`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_WIDTH 1
4274`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_INT_SLC 0:0
4275`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_POSITION 4
4276`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
4277`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4278`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_POR_VALUE 1'b0
4279`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_PAD_POS_FIELD_NAME "msk_ill_pad_pos"
4280`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_FID 9
4281`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_SLC 3:3
4282`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_WIDTH 1
4283`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_INT_SLC 0:0
4284`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_POSITION 3
4285`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
4286`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4287`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_POR_VALUE 1'b0
4288`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_SDP_FIELD_NAME "msk_multi_sdp"
4289`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_FID 10
4290`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_SLC 2:2
4291`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_WIDTH 1
4292`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_INT_SLC 0:0
4293`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_POSITION 2
4294`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
4295`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4296`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_POR_VALUE 1'b0
4297`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_MULTI_STP_FIELD_NAME "msk_multi_stp"
4298`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_FID 11
4299`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_SLC 1:1
4300`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_WIDTH 1
4301`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_INT_SLC 0:0
4302`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_POSITION 1
4303`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
4304`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4305`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_POR_VALUE 1'b0
4306`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_SDP_POS_FIELD_NAME "msk_ill_sdp_pos"
4307`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_FID 12
4308`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_SLC 0:0
4309`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_WIDTH 1
4310`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_INT_SLC 0:0
4311`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_POSITION 0
4312`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
4313`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4314`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_POR_VALUE 1'b0
4315`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_PHY_ERR_MSK_MSK_ILL_STP_POS_FIELD_NAME "msk_ill_stp_pos"
4316
4317//-------------------------------------------------------
4318//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG
4319//-------------------------------------------------------
4320
4321`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ADDR 20'b11011100010011010000
4322`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_ADDR 30'b000000011011100010011010000000
4323`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_cnfg"
4324`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WIDTH 64
4325`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_DEPTH 1
4326`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_SLC 63:0
4327`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_INT_SLC 63:0
4328`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_POSITION 0
4329`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_cnfg"
4330`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_LOW_ADDR_WIDTH 0
4331`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_ADDR_RANGE 19:0
4332`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
4333`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4334`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
4335`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4336`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4337`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4338`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4339`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
4340`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
4341`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4342`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
4343`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_INTERNAL_REG 0
4344`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_EXTERNAL_DECODE_REG 0
4345`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_ALIASED_FROM 0
4346`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_ZERO_TIME_OMNI 0
4347`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_JTAG_RD 1
4348`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_JTAG_WR 1
4349`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_SBUS_RD 1
4350`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_SBUS_WR 1
4351`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_RAP_RD 1
4352`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_HW_ACC_RAP_WR 1
4353`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_NUM_FIELDS 4
4354`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_FID 0
4355`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_SLC 31:31
4356`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_WIDTH 1
4357`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_INT_SLC 0:0
4358`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_POSITION 31
4359`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
4360`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4361`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_POR_VALUE 1'b0
4362`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RX_PHY_TST_FIELD_NAME "rx_phy_tst"
4363`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_FID 1
4364`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_SLC 30:18
4365`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_WIDTH 13
4366`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_INT_SLC 12:0
4367`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_POSITION 18
4368`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_FMASK 64'b0000000000000000000000000000000001111111111111000000000000000000
4369`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4370`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_POR_VALUE 13'b0000000000000
4371`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_UNUSED_CONTROL_FIELD_NAME "unused_control"
4372`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_FID 2
4373`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_SLC 17:16
4374`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_WIDTH 2
4375`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_INT_SLC 1:0
4376`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_POSITION 16
4377`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_FMASK 64'b0000000000000000000000000000000000000000000000110000000000000000
4378`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4379`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_POR_VALUE 2'b00
4380`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_WM_SEL_FIFO_FIELD_NAME "wm_sel_fifo"
4381`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_FID 3
4382`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_SLC 15:0
4383`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_WIDTH 16
4384`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_INT_SLC 15:0
4385`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_POSITION 0
4386`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
4387`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4388`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_POR_VALUE 16'b0000000000000000
4389`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_CNFG_RST_RCV_LANE_FIELD_NAME "rst_rcv_lane"
4390
4391//-------------------------------------------------------
4392//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1
4393//-------------------------------------------------------
4394
4395`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ADDR 20'b11011100010011010001
4396`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ADDR 30'b000000011011100010011010001000
4397`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat1"
4398`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_WIDTH 64
4399`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_DEPTH 1
4400`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_SLC 63:0
4401`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_INT_SLC 63:0
4402`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_POSITION 0
4403`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat1"
4404`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_LOW_ADDR_WIDTH 0
4405`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ADDR_RANGE 19:0
4406`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_READ_MASK 64'b0000000000000000000000000000000000000000000000011111111111111111
4407`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000010000000000000000
4408`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_WRITE_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
4409`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4410`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4411`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4412`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4413`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RMASK 64'b0000000000000000000000000000000000000000000000011111111111111111
4414`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111100000000000000000
4415`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000011111111111111111
4416`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
4417`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_INTERNAL_REG 0
4418`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_EXTERNAL_DECODE_REG 0
4419`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIASED_FROM 0
4420`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ZERO_TIME_OMNI 0
4421`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_JTAG_RD 1
4422`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_JTAG_WR 1
4423`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_SBUS_RD 1
4424`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_SBUS_WR 1
4425`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_RAP_RD 1
4426`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_HW_ACC_RAP_WR 1
4427`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_NUM_FIELDS 2
4428`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_FID 0
4429`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_SLC 16:16
4430`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_WIDTH 1
4431`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_INT_SLC 0:0
4432`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_POSITION 16
4433`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_FMASK 64'b0000000000000000000000000000000000000000000000010000000000000000
4434`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000010000000000000000
4435`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_POR_VALUE 1'b0
4436`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_ALIGN_STS_FIELD_NAME "align_sts"
4437`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_FID 1
4438`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_SLC 15:0
4439`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_WIDTH 16
4440`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_INT_SLC 15:0
4441`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_POSITION 0
4442`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
4443`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
4444`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_POR_VALUE 16'b0000000000000000
4445`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT1_RX_PHY_STS_FIELD_NAME "rx_phy_sts"
4446
4447//-------------------------------------------------------
4448//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2
4449//-------------------------------------------------------
4450
4451`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ADDR 20'b11011100010011010010
4452`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_ADDR 30'b000000011011100010011010010000
4453`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat2"
4454`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_WIDTH 64
4455`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_DEPTH 1
4456`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_SLC 63:0
4457`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_INT_SLC 63:0
4458`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_POSITION 0
4459`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat2"
4460`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_LOW_ADDR_WIDTH 0
4461`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_ADDR_RANGE 19:0
4462`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_READ_MASK 64'b0000000000000000000000000000000000001111111111111111111111111111
4463`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_READ_ONLY_MASK 64'b0000000000000000000000000000000000001111111111111111111111111111
4464`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4465`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4466`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4467`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4468`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4469`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RMASK 64'b0000000000000000000000000000000000001111111111111111111111111111
4470`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111110000000000000000000000000000
4471`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_LD_MASK 64'b0000000000000000000000000000000000001000000000000000000000000000
4472`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
4473`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_INTERNAL_REG 0
4474`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_EXTERNAL_DECODE_REG 0
4475`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_ALIASED_FROM 0
4476`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_ZERO_TIME_OMNI 0
4477`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_JTAG_RD 1
4478`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_JTAG_WR 1
4479`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_SBUS_RD 1
4480`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_SBUS_WR 1
4481`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_RAP_RD 1
4482`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_HW_ACC_RAP_WR 1
4483`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_NUM_FIELDS 7
4484`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_FID 0
4485`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_SLC 27:27
4486`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_WIDTH 1
4487`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_INT_SLC 0:0
4488`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_POSITION 27
4489`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_FMASK 64'b0000000000000000000000000000000000001000000000000000000000000000
4490`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_HW_LD_MASK 64'b0000000000000000000000000000000000001000000000000000000000000000
4491`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_POR_VALUE 1'b0
4492`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_SCRAM_FIELD_NAME "rcv_dis_scram"
4493`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_FID 1
4494`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_SLC 26:26
4495`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_WIDTH 1
4496`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_INT_SLC 0:0
4497`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_POSITION 26
4498`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_FMASK 64'b0000000000000000000000000000000000000100000000000000000000000000
4499`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4500`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_POR_VALUE 1'b0
4501`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_EN_LOOPBACK_FIELD_NAME "rcv_en_loopback"
4502`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_FID 2
4503`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_SLC 25:25
4504`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_WIDTH 1
4505`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_INT_SLC 0:0
4506`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_POSITION 25
4507`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_FMASK 64'b0000000000000000000000000000000000000010000000000000000000000000
4508`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4509`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_POR_VALUE 1'b0
4510`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DIS_LINK_FIELD_NAME "rcv_dis_link"
4511`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_FID 3
4512`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_SLC 24:24
4513`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_WIDTH 1
4514`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_INT_SLC 0:0
4515`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_POSITION 24
4516`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_FMASK 64'b0000000000000000000000000000000000000001000000000000000000000000
4517`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4518`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_POR_VALUE 1'b0
4519`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_HOT_RST_FIELD_NAME "rcv_hot_rst"
4520`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_FID 4
4521`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_SLC 23:16
4522`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_WIDTH 8
4523`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_INT_SLC 7:0
4524`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_POSITION 16
4525`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_FMASK 64'b0000000000000000000000000000000000000000111111110000000000000000
4526`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4527`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_POR_VALUE 8'b00000000
4528`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_DATA_RATE_FIELD_NAME "rcv_data_rate"
4529`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_FID 5
4530`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_SLC 15:8
4531`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_WIDTH 8
4532`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_INT_SLC 7:0
4533`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_POSITION 8
4534`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_FMASK 64'b0000000000000000000000000000000000000000000000001111111100000000
4535`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4536`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_POR_VALUE 8'b00000000
4537`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_FTS_NUM_FIELD_NAME "rcv_fts_num"
4538`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_FID 6
4539`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_SLC 7:0
4540`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_WIDTH 8
4541`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_INT_SLC 7:0
4542`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_POSITION 0
4543`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
4544`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4545`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_POR_VALUE 8'b00000000
4546`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT2_RCV_LINK_NUM_FIELD_NAME "rcv_link_num"
4547
4548//-------------------------------------------------------
4549//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3
4550//-------------------------------------------------------
4551
4552`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ADDR 20'b11011100010011010011
4553`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_ADDR 30'b000000011011100010011010011000
4554`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat3"
4555`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_WIDTH 64
4556`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_DEPTH 1
4557`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_SLC 63:0
4558`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_INT_SLC 63:0
4559`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_POSITION 0
4560`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_stat3"
4561`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_LOW_ADDR_WIDTH 0
4562`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_ADDR_RANGE 19:0
4563`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
4564`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
4565`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4566`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4567`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4568`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4569`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4570`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
4571`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
4572`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4573`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
4574`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_INTERNAL_REG 0
4575`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_EXTERNAL_DECODE_REG 0
4576`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_ALIASED_FROM 0
4577`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_ZERO_TIME_OMNI 0
4578`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_JTAG_RD 1
4579`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_JTAG_WR 1
4580`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_SBUS_RD 1
4581`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_SBUS_WR 1
4582`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_RAP_RD 1
4583`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_HW_ACC_RAP_WR 1
4584`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_NUM_FIELDS 1
4585`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_FID 0
4586`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_SLC 15:0
4587`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_WIDTH 16
4588`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_INT_SLC 15:0
4589`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_POSITION 0
4590`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
4591`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4592`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_POR_VALUE 16'b0000000000000000
4593`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_STAT3_BYTE_SYNC_STS_FIELD_NAME "byte_sync_sts"
4594
4595//-------------------------------------------------------
4596//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT
4597//-------------------------------------------------------
4598
4599`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ADDR 20'b11011100010011010100
4600`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_ADDR 30'b000000011011100010011010100000
4601`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_int"
4602`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_WIDTH 64
4603`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_DEPTH 1
4604`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_SLC 63:0
4605`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_SLC 63:0
4606`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_POSITION 0
4607`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_int"
4608`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_LOW_ADDR_WIDTH 0
4609`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_ADDR_RANGE 19:0
4610`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_READ_MASK 64'b0000000000000000000000000000000010000000000000000000111111111111
4611`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_READ_ONLY_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
4612`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4613`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4614`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4615`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
4616`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4617`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_RMASK 64'b0000000000000000000000000000000010000000000000000000111111111111
4618`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111111000000000000
4619`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
4620`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
4621`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INTERNAL_REG 0
4622`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_EXTERNAL_DECODE_REG 0
4623`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_ALIASED_FROM 0
4624`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_ZERO_TIME_OMNI 0
4625`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_JTAG_RD 1
4626`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_JTAG_WR 1
4627`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_SBUS_RD 1
4628`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_SBUS_WR 1
4629`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_RAP_RD 1
4630`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_HW_ACC_RAP_WR 1
4631`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_NUM_FIELDS 5
4632`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_FID 0
4633`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_SLC 31:31
4634`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_WIDTH 1
4635`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_INT_SLC 0:0
4636`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_POSITION 31
4637`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
4638`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4639`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_POR_VALUE 1'b0
4640`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_RCV_PHY_FIELD_NAME "int_rcv_phy"
4641`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_FID 1
4642`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_SLC 11:3
4643`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_WIDTH 9
4644`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_INT_SLC 8:0
4645`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_POSITION 3
4646`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111000
4647`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111000
4648`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_POR_VALUE 9'b000000000
4649`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_UNUSED_FIELD_NAME "int_unused"
4650`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_FID 2
4651`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_SLC 2:2
4652`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_WIDTH 1
4653`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_INT_SLC 0:0
4654`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_POSITION 2
4655`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
4656`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
4657`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_POR_VALUE 1'b0
4658`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ALIGN_ERR_FIELD_NAME "int_align_err"
4659`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_FID 3
4660`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_SLC 1:1
4661`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_WIDTH 1
4662`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_INT_SLC 0:0
4663`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_POSITION 1
4664`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
4665`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
4666`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_POR_VALUE 1'b0
4667`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_OVRFLW_FIELD_NAME "int_elstc_fifo_ovrflw"
4668`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_FID 4
4669`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_SLC 0:0
4670`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_WIDTH 1
4671`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_INT_SLC 0:0
4672`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_POSITION 0
4673`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
4674`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
4675`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_POR_VALUE 1'b0
4676`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_INT_INT_ELSTC_FIFO_UNDRFLW_FIELD_NAME "int_elstc_fifo_undrflw"
4677
4678//-------------------------------------------------------
4679//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST
4680//-------------------------------------------------------
4681
4682`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ADDR 20'b11011100010011010101
4683`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_ADDR 30'b000000011011100010011010101000
4684`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_tst"
4685`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_WIDTH 64
4686`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_DEPTH 1
4687`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_SLC 63:0
4688`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_INT_SLC 63:0
4689`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_POSITION 0
4690`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_tst"
4691`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_LOW_ADDR_WIDTH 0
4692`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_ADDR_RANGE 19:0
4693`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_READ_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
4694`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4695`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4696`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4697`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_SET_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
4698`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4699`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4700`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_RMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
4701`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111000000000000
4702`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
4703`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
4704`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_INTERNAL_REG 0
4705`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_EXTERNAL_DECODE_REG 0
4706`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_ALIASED_FROM 0
4707`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_ZERO_TIME_OMNI 0
4708`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_JTAG_RD 1
4709`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_JTAG_WR 1
4710`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_SBUS_RD 1
4711`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_SBUS_WR 1
4712`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_RAP_RD 1
4713`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_HW_ACC_RAP_WR 1
4714`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_NUM_FIELDS 4
4715`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_FID 0
4716`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_SLC 11:3
4717`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_WIDTH 9
4718`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_INT_SLC 8:0
4719`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_POSITION 3
4720`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111000
4721`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111000
4722`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_POR_VALUE 9'b000000000
4723`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_UNUSED_FIELD_NAME "tst_unused"
4724`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_FID 1
4725`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_SLC 2:2
4726`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_WIDTH 1
4727`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_INT_SLC 0:0
4728`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_POSITION 2
4729`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
4730`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
4731`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_POR_VALUE 1'b0
4732`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ALIGN_ERR_FIELD_NAME "tst_align_err"
4733`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_FID 2
4734`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_SLC 1:1
4735`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_WIDTH 1
4736`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_INT_SLC 0:0
4737`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_POSITION 1
4738`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
4739`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
4740`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_POR_VALUE 1'b0
4741`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_OVRFLW_FIELD_NAME "tst_elstc_fifo_ovrflw"
4742`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_FID 3
4743`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_SLC 0:0
4744`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_WIDTH 1
4745`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_INT_SLC 0:0
4746`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_POSITION 0
4747`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
4748`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
4749`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_POR_VALUE 1'b0
4750`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_TST_TST_ELSTC_FIFO_UNDRFLW_FIELD_NAME "tst_elstc_fifo_undrflw"
4751
4752//-------------------------------------------------------
4753//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK
4754//-------------------------------------------------------
4755
4756`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ADDR 20'b11011100010011010110
4757`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_ADDR 30'b000000011011100010011010110000
4758`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_msk"
4759`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_WIDTH 64
4760`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_DEPTH 1
4761`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_SLC 63:0
4762`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_INT_SLC 63:0
4763`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_POSITION 0
4764`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_rx_phy_msk"
4765`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_LOW_ADDR_WIDTH 0
4766`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_ADDR_RANGE 19:0
4767`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_READ_MASK 64'b0000000000000000000000000000000010000000000000000000111111111111
4768`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4769`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_WRITE_MASK 64'b0000000000000000000000000000000010000000000000000000111111111111
4770`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4771`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4772`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4773`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4774`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_RMASK 64'b0000000000000000000000000000000010000000000000000000111111111111
4775`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111111000000000000
4776`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4777`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_POR_VALUE 64'b0000000000000000000000000000000010000000000000000000111111111111
4778`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_INTERNAL_REG 0
4779`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_EXTERNAL_DECODE_REG 0
4780`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_ALIASED_FROM 0
4781`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_ZERO_TIME_OMNI 0
4782`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_JTAG_RD 1
4783`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_JTAG_WR 1
4784`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_SBUS_RD 1
4785`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_SBUS_WR 1
4786`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_RAP_RD 1
4787`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_HW_ACC_RAP_WR 1
4788`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_NUM_FIELDS 5
4789`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_FID 0
4790`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_SLC 31:31
4791`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_WIDTH 1
4792`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_INT_SLC 0:0
4793`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_POSITION 31
4794`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
4795`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4796`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_POR_VALUE 1'b1
4797`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_RCV_PHY_INT_FIELD_NAME "msk_rcv_phy_int"
4798`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_FID 1
4799`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_SLC 11:3
4800`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_WIDTH 9
4801`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_INT_SLC 8:0
4802`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_POSITION 3
4803`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111000
4804`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4805`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_POR_VALUE 9'b111111111
4806`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_UNUSED_FIELD_NAME "msk_unused"
4807`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_FID 2
4808`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_SLC 2:2
4809`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_WIDTH 1
4810`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_INT_SLC 0:0
4811`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_POSITION 2
4812`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
4813`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4814`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_POR_VALUE 1'b1
4815`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ALIGN_ERR_FIELD_NAME "msk_align_err"
4816`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_FID 3
4817`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_SLC 1:1
4818`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_WIDTH 1
4819`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_INT_SLC 0:0
4820`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_POSITION 1
4821`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
4822`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4823`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_POR_VALUE 1'b1
4824`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_OVRFLW_FIELD_NAME "msk_elstc_fifo_ovrflw"
4825`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_FID 4
4826`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_SLC 0:0
4827`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_WIDTH 1
4828`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_INT_SLC 0:0
4829`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_POSITION 0
4830`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
4831`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4832`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_POR_VALUE 1'b1
4833`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_RX_PHY_MSK_MSK_ELSTC_FIFO_UNDRFLW_FIELD_NAME "msk_elstc_fifo_undrflw"
4834
4835//-------------------------------------------------------
4836//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG
4837//-------------------------------------------------------
4838
4839`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ADDR 20'b11011100010011100000
4840`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_ADDR 30'b000000011011100010011100000000
4841`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_config"
4842`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_WIDTH 64
4843`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_DEPTH 1
4844`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_SLC 63:0
4845`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_INT_SLC 63:0
4846`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_POSITION 0
4847`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_config"
4848`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_LOW_ADDR_WIDTH 0
4849`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_ADDR_RANGE 19:0
4850`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
4851`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4852`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
4853`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4854`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4855`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4856`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4857`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
4858`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
4859`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4860`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
4861`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_INTERNAL_REG 0
4862`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_EXTERNAL_DECODE_REG 0
4863`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_ALIASED_FROM 0
4864`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_ZERO_TIME_OMNI 0
4865`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_JTAG_RD 1
4866`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_JTAG_WR 1
4867`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_SBUS_RD 1
4868`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_SBUS_WR 1
4869`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_RAP_RD 1
4870`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_HW_ACC_RAP_WR 1
4871`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_NUM_FIELDS 2
4872`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_FID 0
4873`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_SLC 31:16
4874`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_WIDTH 16
4875`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_INT_SLC 15:0
4876`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_POSITION 16
4877`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
4878`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4879`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_POR_VALUE 16'b0000000000000000
4880`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_RCVR_DET_FIELD_NAME "frce_rcvr_det"
4881`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_FID 1
4882`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_SLC 15:0
4883`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_WIDTH 16
4884`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_INT_SLC 15:0
4885`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_POSITION 0
4886`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
4887`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4888`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_POR_VALUE 16'b0000000000000000
4889`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_CONFIG_FRCE_ELEC_IDLE_FIELD_NAME "frce_elec_idle"
4890
4891//-------------------------------------------------------
4892//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT
4893//-------------------------------------------------------
4894
4895`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ADDR 20'b11011100010011100001
4896`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_ADDR 30'b000000011011100010011100001000
4897`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_stat"
4898`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_WIDTH 64
4899`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_DEPTH 1
4900`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_SLC 63:0
4901`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_INT_SLC 63:0
4902`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_POSITION 0
4903`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_stat"
4904`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_LOW_ADDR_WIDTH 0
4905`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_ADDR_RANGE 19:0
4906`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_READ_MASK 64'b0000000000000000000000000000000011111111011111111111111111111111
4907`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_READ_ONLY_MASK 64'b0000000000000000000000000000000011111111011111111111111111111111
4908`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4909`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4910`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4911`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4912`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
4913`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_RMASK 64'b0000000000000000000000000000000011111111011111111111111111111111
4914`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000100000000000000000000000
4915`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_LD_MASK 64'b0000000000000000000000000000000011111111011111111111111111111111
4916`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_POR_VALUE 64'b0000000000000000000000000000000001110011000000000000000000010000
4917`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_INTERNAL_REG 0
4918`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_EXTERNAL_DECODE_REG 0
4919`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_ALIASED_FROM 0
4920`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_ZERO_TIME_OMNI 0
4921`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_JTAG_RD 1
4922`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_JTAG_WR 1
4923`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_SBUS_RD 1
4924`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_SBUS_WR 1
4925`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_RAP_RD 1
4926`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_HW_ACC_RAP_WR 1
4927`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NUM_FIELDS 6
4928`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_FID 0
4929`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_SLC 31:28
4930`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_WIDTH 4
4931`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_INT_SLC 3:0
4932`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_POSITION 28
4933`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_FMASK 64'b0000000000000000000000000000000011110000000000000000000000000000
4934`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_HW_LD_MASK 64'b0000000000000000000000000000000011110000000000000000000000000000
4935`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_POR_VALUE 4'b0111
4936`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_NEG_LANE_WDTH_FIELD_NAME "neg_lane_wdth"
4937`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_FID 1
4938`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_SLC 27:27
4939`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_WIDTH 1
4940`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_INT_SLC 0:0
4941`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_POSITION 27
4942`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_FMASK 64'b0000000000000000000000000000000000001000000000000000000000000000
4943`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_HW_LD_MASK 64'b0000000000000000000000000000000000001000000000000000000000000000
4944`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_POR_VALUE 1'b0
4945`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TXPHY_SCRAM_EN_FIELD_NAME "txphy_scram_en"
4946`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_FID 2
4947`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_SLC 26:26
4948`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_WIDTH 1
4949`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_INT_SLC 0:0
4950`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_POSITION 26
4951`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_FMASK 64'b0000000000000000000000000000000000000100000000000000000000000000
4952`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_HW_LD_MASK 64'b0000000000000000000000000000000000000100000000000000000000000000
4953`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_POR_VALUE 1'b0
4954`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_REV_FIELD_NAME "tx_lane_rev"
4955`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_FID 3
4956`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_SLC 25:25
4957`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_WIDTH 1
4958`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_INT_SLC 0:0
4959`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_POSITION 25
4960`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_FMASK 64'b0000000000000000000000000000000000000010000000000000000000000000
4961`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_HW_LD_MASK 64'b0000000000000000000000000000000000000010000000000000000000000000
4962`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_POR_VALUE 1'b1
4963`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LANE_PAD_FIELD_NAME "tx_lane_pad"
4964`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_FID 4
4965`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_SLC 24:24
4966`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_WIDTH 1
4967`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_INT_SLC 0:0
4968`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_POSITION 24
4969`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_FMASK 64'b0000000000000000000000000000000000000001000000000000000000000000
4970`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_HW_LD_MASK 64'b0000000000000000000000000000000000000001000000000000000000000000
4971`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_POR_VALUE 1'b1
4972`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_LINK_PAD_FIELD_NAME "tx_link_pad"
4973`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_FID 5
4974`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_SLC 22:0
4975`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_WIDTH 23
4976`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_INT_SLC 22:0
4977`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_POSITION 0
4978`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_FMASK 64'b0000000000000000000000000000000000000000011111111111111111111111
4979`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_HW_LD_MASK 64'b0000000000000000000000000000000000000000011111111111111111111111
4980`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_POR_VALUE 23'b00000000000000000010000
4981`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STAT_TX_PHY_SMS_FIELD_NAME "tx_phy_sms"
4982
4983//-------------------------------------------------------
4984//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT
4985//-------------------------------------------------------
4986
4987`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ADDR 20'b11011100010011100010
4988`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_ADDR 30'b000000011011100010011100010000
4989`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_int"
4990`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_WIDTH 64
4991`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_DEPTH 1
4992`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_SLC 63:0
4993`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SLC 63:0
4994`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_POSITION 0
4995`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_int"
4996`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_LOW_ADDR_WIDTH 0
4997`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_ADDR_RANGE 19:0
4998`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_READ_MASK 64'b0000000000000000000000000000000010000000000000000000111111111111
4999`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_READ_ONLY_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
5000`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5001`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5002`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5003`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
5004`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5005`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_RMASK 64'b0000000000000000000000000000000010000000000000000000111111111111
5006`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111111000000000000
5007`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
5008`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
5009`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INTERNAL_REG 0
5010`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_EXTERNAL_DECODE_REG 0
5011`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_ALIASED_FROM 0
5012`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_ZERO_TIME_OMNI 0
5013`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_JTAG_RD 1
5014`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_JTAG_WR 1
5015`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_SBUS_RD 1
5016`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_SBUS_WR 1
5017`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_RAP_RD 1
5018`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_HW_ACC_RAP_WR 1
5019`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_NUM_FIELDS 12
5020`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_FID 0
5021`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_SLC 31:31
5022`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_WIDTH 1
5023`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_INT_SLC 0:0
5024`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_POSITION 31
5025`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
5026`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5027`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_POR_VALUE 1'b0
5028`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNMSK_FIELD_NAME "int_unmsk"
5029`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_FID 1
5030`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_SLC 11:11
5031`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_WIDTH 1
5032`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_INT_SLC 0:0
5033`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_POSITION 11
5034`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
5035`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000100000000000
5036`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_POR_VALUE 1'b0
5037`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_IDLE_FIELD_NAME "int_rcv_idle"
5038`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_FID 2
5039`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_SLC 10:10
5040`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_WIDTH 1
5041`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_INT_SLC 0:0
5042`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_POSITION 10
5043`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
5044`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
5045`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_POR_VALUE 1'b0
5046`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS2_FIELD_NAME "int_rcv_ts2"
5047`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_FID 3
5048`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_SLC 9:9
5049`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_WIDTH 1
5050`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_INT_SLC 0:0
5051`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_POSITION 9
5052`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
5053`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
5054`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_POR_VALUE 1'b0
5055`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCV_TS1_FIELD_NAME "int_rcv_ts1"
5056`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_FID 4
5057`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_SLC 8:8
5058`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_WIDTH 1
5059`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_INT_SLC 0:0
5060`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_POSITION 8
5061`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
5062`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
5063`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_POR_VALUE 1'b0
5064`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ERR_FIELD_NAME "int_skp_err"
5065`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_FID 5
5066`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_SLC 7:7
5067`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_WIDTH 1
5068`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_INT_SLC 0:0
5069`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_POSITION 7
5070`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
5071`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
5072`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_POR_VALUE 1'b0
5073`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_BK2BK_FIELD_NAME "int_skp_done_bk2bk"
5074`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_FID 6
5075`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_SLC 6:6
5076`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_WIDTH 1
5077`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_INT_SLC 0:0
5078`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_POSITION 6
5079`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
5080`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
5081`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_POR_VALUE 1'b0
5082`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_ACK_DECR_FIELD_NAME "int_skp_ack_decr"
5083`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_FID 7
5084`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_SLC 5:5
5085`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_WIDTH 1
5086`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_INT_SLC 0:0
5087`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_POSITION 5
5088`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
5089`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
5090`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_POR_VALUE 1'b0
5091`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_DONE_DECR_FIELD_NAME "int_skp_done_decr"
5092`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_FID 8
5093`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_SLC 4:4
5094`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_WIDTH 1
5095`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_INT_SLC 0:0
5096`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_POSITION 4
5097`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
5098`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
5099`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_POR_VALUE 1'b0
5100`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_SKP_TRIG_FIELD_NAME "int_skp_trig"
5101`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_FID 9
5102`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_SLC 3:2
5103`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_WIDTH 2
5104`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_INT_SLC 1:0
5105`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_POSITION 2
5106`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001100
5107`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001100
5108`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_POR_VALUE 2'b00
5109`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_UNUSED_2_FIELD_NAME "int_unused_2"
5110`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_FID 10
5111`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_SLC 1:1
5112`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_WIDTH 1
5113`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_INT_SLC 0:0
5114`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_POSITION 1
5115`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
5116`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
5117`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_POR_VALUE 1'b0
5118`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_RCVR_DET_VALID_FIELD_NAME "int_rcvr_det_valid"
5119`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_FID 11
5120`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_SLC 0:0
5121`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_WIDTH 1
5122`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_INT_SLC 0:0
5123`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_POSITION 0
5124`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
5125`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
5126`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_POR_VALUE 1'b0
5127`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_INT_INT_TX_PAR_ERR_FIELD_NAME "int_tx_par_err"
5128
5129//-------------------------------------------------------
5130//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST
5131//-------------------------------------------------------
5132
5133`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ADDR 20'b11011100010011100011
5134`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_ADDR 30'b000000011011100010011100011000
5135`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_tst"
5136`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_WIDTH 64
5137`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_DEPTH 1
5138`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_SLC 63:0
5139`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_INT_SLC 63:0
5140`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_POSITION 0
5141`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_tst"
5142`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_LOW_ADDR_WIDTH 0
5143`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_ADDR_RANGE 19:0
5144`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_READ_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
5145`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5146`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5147`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5148`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_SET_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
5149`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5150`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5151`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_RMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
5152`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111000000000000
5153`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
5154`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
5155`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_INTERNAL_REG 0
5156`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_EXTERNAL_DECODE_REG 0
5157`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_ALIASED_FROM 0
5158`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_ZERO_TIME_OMNI 0
5159`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_JTAG_RD 1
5160`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_JTAG_WR 1
5161`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_SBUS_RD 1
5162`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_SBUS_WR 1
5163`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_RAP_RD 1
5164`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_HW_ACC_RAP_WR 1
5165`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_NUM_FIELDS 1
5166`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_FID 0
5167`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_SLC 11:0
5168`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_WIDTH 12
5169`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_INT_SLC 11:0
5170`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_POSITION 0
5171`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
5172`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000111111111111
5173`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_POR_VALUE 12'b000000000000
5174`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_TST_TST_TX_PHY_INT_FIELD_NAME "tst_tx_phy_int"
5175
5176//-------------------------------------------------------
5177//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK
5178//-------------------------------------------------------
5179
5180`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ADDR 20'b11011100010011100100
5181`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_ADDR 30'b000000011011100010011100100000
5182`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_msk"
5183`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_WIDTH 64
5184`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_DEPTH 1
5185`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_SLC 63:0
5186`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_INT_SLC 63:0
5187`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_POSITION 0
5188`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_msk"
5189`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_LOW_ADDR_WIDTH 0
5190`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_ADDR_RANGE 19:0
5191`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_READ_MASK 64'b0000000000000000000000000000000010000000000000000000111111111111
5192`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5193`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_WRITE_MASK 64'b0000000000000000000000000000000010000000000000000000111111111111
5194`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5195`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5196`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5197`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5198`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_RMASK 64'b0000000000000000000000000000000010000000000000000000111111111111
5199`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111111111000000000000
5200`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5201`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_POR_VALUE 64'b0000000000000000000000000000000010000000000000000000111111111111
5202`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_INTERNAL_REG 0
5203`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_EXTERNAL_DECODE_REG 0
5204`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_ALIASED_FROM 0
5205`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_ZERO_TIME_OMNI 0
5206`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_JTAG_RD 1
5207`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_JTAG_WR 1
5208`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_SBUS_RD 1
5209`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_SBUS_WR 1
5210`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_RAP_RD 1
5211`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_HW_ACC_RAP_WR 1
5212`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_NUM_FIELDS 2
5213`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_FID 0
5214`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_SLC 31:31
5215`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_WIDTH 1
5216`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_INT_SLC 0:0
5217`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_POSITION 31
5218`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
5219`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5220`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_POR_VALUE 1'b1
5221`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_GLOBL_INT_FIELD_NAME "msk_globl_int"
5222`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_FID 1
5223`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_SLC 11:0
5224`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_WIDTH 12
5225`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_INT_SLC 11:0
5226`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_POSITION 0
5227`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_FMASK 64'b0000000000000000000000000000000000000000000000000000111111111111
5228`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5229`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_POR_VALUE 12'b111111111111
5230`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_MSK_MSK_IMPLEM_INT_FIELD_NAME "msk_implem_int"
5231
5232//-------------------------------------------------------
5233//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2
5234//-------------------------------------------------------
5235
5236`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ADDR 20'b11011100010011100101
5237`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_ADDR 30'b000000011011100010011100101000
5238`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_sts_2"
5239`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_WIDTH 64
5240`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_DEPTH 1
5241`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_SLC 63:0
5242`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_INT_SLC 63:0
5243`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_POSITION 0
5244`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_tx_phy_sts_2"
5245`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_LOW_ADDR_WIDTH 0
5246`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_ADDR_RANGE 19:0
5247`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5248`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_READ_ONLY_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5249`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5250`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5251`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5252`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5253`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5254`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5255`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
5256`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5257`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
5258`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_INTERNAL_REG 0
5259`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_EXTERNAL_DECODE_REG 0
5260`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_ALIASED_FROM 0
5261`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_ZERO_TIME_OMNI 0
5262`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_JTAG_RD 1
5263`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_JTAG_WR 1
5264`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_SBUS_RD 1
5265`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_SBUS_WR 1
5266`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_RAP_RD 1
5267`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_HW_ACC_RAP_WR 1
5268`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_NUM_FIELDS 2
5269`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_FID 0
5270`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_SLC 31:16
5271`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_WIDTH 16
5272`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_INT_SLC 15:0
5273`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_POSITION 16
5274`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
5275`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111110000000000000000
5276`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_POR_VALUE 16'b0000000000000000
5277`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_STS_FIELD_NAME "recv_det_sts"
5278`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_FID 1
5279`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_SLC 15:0
5280`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_WIDTH 16
5281`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_INT_SLC 15:0
5282`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_POSITION 0
5283`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
5284`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
5285`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_POR_VALUE 16'b0000000000000000
5286`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_TX_PHY_STS_2_RECV_DET_RAW_STS_FIELD_NAME "recv_det_raw_sts"
5287
5288//-------------------------------------------------------
5289//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1
5290//-------------------------------------------------------
5291
5292`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ADDR 20'b11011100010011110000
5293`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_ADDR 30'b000000011011100010011110000000
5294`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config1"
5295`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_WIDTH 64
5296`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_DEPTH 1
5297`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_SLC 63:0
5298`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_INT_SLC 63:0
5299`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_POSITION 0
5300`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config1"
5301`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LOW_ADDR_WIDTH 0
5302`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_ADDR_RANGE 19:0
5303`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5304`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5305`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5306`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5307`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5308`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5309`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5310`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5311`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
5312`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5313`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000001100100000101
5314`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_INTERNAL_REG 0
5315`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_EXTERNAL_DECODE_REG 0
5316`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_ALIASED_FROM 0
5317`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_ZERO_TIME_OMNI 0
5318`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_JTAG_RD 1
5319`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_JTAG_WR 1
5320`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_SBUS_RD 1
5321`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_SBUS_WR 1
5322`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_RAP_RD 1
5323`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HW_ACC_RAP_WR 1
5324`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_NUM_FIELDS 6
5325`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_FID 0
5326`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_SLC 31:31
5327`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_WIDTH 1
5328`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_INT_SLC 0:0
5329`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_POSITION 31
5330`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
5331`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5332`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_POR_VALUE 1'b0
5333`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_TST_FIELD_NAME "ltssm_tst"
5334`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_FID 1
5335`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_SLC 30:18
5336`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_WIDTH 13
5337`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_INT_SLC 12:0
5338`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_POSITION 18
5339`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_FMASK 64'b0000000000000000000000000000000001111111111111000000000000000000
5340`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5341`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_POR_VALUE 13'b0000000000000
5342`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_UNUSED_CNTL_FIELD_NAME "unused_cntl"
5343`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_FID 2
5344`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_SLC 17:17
5345`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_WIDTH 1
5346`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_INT_SLC 0:0
5347`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_POSITION 17
5348`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_FMASK 64'b0000000000000000000000000000000000000000000000100000000000000000
5349`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5350`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_POR_VALUE 1'b0
5351`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LPBK_MSTR_FIELD_NAME "lpbk_mstr"
5352`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_FID 3
5353`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_SLC 16:16
5354`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_WIDTH 1
5355`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_INT_SLC 0:0
5356`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_POSITION 16
5357`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_FMASK 64'b0000000000000000000000000000000000000000000000010000000000000000
5358`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5359`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_POR_VALUE 1'b0
5360`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_HI_DATA_SUP_FIELD_NAME "hi_data_sup"
5361`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_FID 4
5362`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_SLC 15:8
5363`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_WIDTH 8
5364`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_INT_SLC 7:0
5365`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_POSITION 8
5366`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_FMASK 64'b0000000000000000000000000000000000000000000000001111111100000000
5367`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5368`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_POR_VALUE 8'b00011001
5369`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_8_TO_FIELD_NAME "ltssm_8_to"
5370`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_FID 5
5371`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_SLC 7:0
5372`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_WIDTH 8
5373`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_INT_SLC 7:0
5374`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_POSITION 0
5375`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
5376`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5377`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_POR_VALUE 8'b00000101
5378`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG1_LTSSM_20_TO_FIELD_NAME "ltssm_20_to"
5379
5380//-------------------------------------------------------
5381//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2
5382//-------------------------------------------------------
5383
5384`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ADDR 20'b11011100010011110001
5385`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_ADDR 30'b000000011011100010011110001000
5386`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config2"
5387`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_WIDTH 64
5388`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_DEPTH 1
5389`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_SLC 63:0
5390`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_INT_SLC 63:0
5391`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_POSITION 0
5392`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config2"
5393`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LOW_ADDR_WIDTH 0
5394`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_ADDR_RANGE 19:0
5395`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5396`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5397`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5398`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5399`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5400`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5401`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5402`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5403`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
5404`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5405`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_POR_VALUE 64'b0000000000000000000000000000000000000000001011011100011011000000
5406`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_INTERNAL_REG 0
5407`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_EXTERNAL_DECODE_REG 0
5408`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_ALIASED_FROM 0
5409`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_ZERO_TIME_OMNI 0
5410`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_JTAG_RD 1
5411`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_JTAG_WR 1
5412`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_SBUS_RD 1
5413`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_SBUS_WR 1
5414`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_RAP_RD 1
5415`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_HW_ACC_RAP_WR 1
5416`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_NUM_FIELDS 1
5417`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_FID 0
5418`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_SLC 31:0
5419`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_WIDTH 32
5420`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_INT_SLC 31:0
5421`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_POSITION 0
5422`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5423`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5424`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_POR_VALUE 32'b00000000001011011100011011000000
5425`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG2_LTSSM_12_TO_FIELD_NAME "ltssm_12_to"
5426
5427//-------------------------------------------------------
5428//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3
5429//-------------------------------------------------------
5430
5431`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ADDR 20'b11011100010011110010
5432`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_ADDR 30'b000000011011100010011110010000
5433`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config3"
5434`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_WIDTH 64
5435`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_DEPTH 1
5436`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_SLC 63:0
5437`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_INT_SLC 63:0
5438`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_POSITION 0
5439`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config3"
5440`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LOW_ADDR_WIDTH 0
5441`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_ADDR_RANGE 19:0
5442`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5443`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5444`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5445`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5446`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5447`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5448`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5449`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5450`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
5451`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5452`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_POR_VALUE 64'b0000000000000000000000000000000000000000000001111010000100100000
5453`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_INTERNAL_REG 0
5454`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_EXTERNAL_DECODE_REG 0
5455`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_ALIASED_FROM 0
5456`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_ZERO_TIME_OMNI 0
5457`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_JTAG_RD 1
5458`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_JTAG_WR 1
5459`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_SBUS_RD 1
5460`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_SBUS_WR 1
5461`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_RAP_RD 1
5462`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_HW_ACC_RAP_WR 1
5463`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_NUM_FIELDS 1
5464`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_FID 0
5465`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_SLC 31:0
5466`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_WIDTH 32
5467`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_INT_SLC 31:0
5468`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_POSITION 0
5469`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5470`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5471`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_POR_VALUE 32'b00000000000001111010000100100000
5472`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG3_LTSSM_2_TO_FIELD_NAME "ltssm_2_to"
5473
5474//-------------------------------------------------------
5475//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4
5476//-------------------------------------------------------
5477
5478`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ADDR 20'b11011100010011110011
5479`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_ADDR 30'b000000011011100010011110011000
5480`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config4"
5481`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_WIDTH 64
5482`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DEPTH 1
5483`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_SLC 63:0
5484`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_INT_SLC 63:0
5485`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_POSITION 0
5486`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config4"
5487`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LOW_ADDR_WIDTH 0
5488`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_ADDR_RANGE 19:0
5489`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5490`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5491`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5492`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5493`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5494`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5495`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5496`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5497`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
5498`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5499`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_POR_VALUE 64'b0000000000000000000000000000000000000000000000101000110000000000
5500`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_INTERNAL_REG 0
5501`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_EXTERNAL_DECODE_REG 0
5502`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_ALIASED_FROM 0
5503`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_ZERO_TIME_OMNI 0
5504`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_JTAG_RD 1
5505`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_JTAG_WR 1
5506`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_SBUS_RD 1
5507`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_SBUS_WR 1
5508`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_RAP_RD 1
5509`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_HW_ACC_RAP_WR 1
5510`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_NUM_FIELDS 4
5511`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_FID 0
5512`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_SLC 31:24
5513`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_WIDTH 8
5514`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_INT_SLC 7:0
5515`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_POSITION 24
5516`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_FMASK 64'b0000000000000000000000000000000011111111000000000000000000000000
5517`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5518`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_POR_VALUE 8'b00000000
5519`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_TRN_CNTRL_FIELD_NAME "trn_cntrl"
5520`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_FID 1
5521`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_SLC 23:16
5522`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_WIDTH 8
5523`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_INT_SLC 7:0
5524`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_POSITION 16
5525`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_FMASK 64'b0000000000000000000000000000000000000000111111110000000000000000
5526`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5527`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_POR_VALUE 8'b00000010
5528`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_DATA_RATE_FIELD_NAME "data_rate"
5529`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_FID 2
5530`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_SLC 15:8
5531`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_WIDTH 8
5532`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_INT_SLC 7:0
5533`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_POSITION 8
5534`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_FMASK 64'b0000000000000000000000000000000000000000000000001111111100000000
5535`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5536`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_POR_VALUE 8'b10001100
5537`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_N_FTS_FIELD_NAME "n_fts"
5538`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_FID 3
5539`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_SLC 7:0
5540`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_WIDTH 8
5541`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_INT_SLC 7:0
5542`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_POSITION 0
5543`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
5544`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5545`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_POR_VALUE 8'b00000000
5546`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG4_LNK_NUM_FIELD_NAME "lnk_num"
5547
5548//-------------------------------------------------------
5549//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5
5550//-------------------------------------------------------
5551
5552`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ADDR 20'b11011100010011110100
5553`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_ADDR 30'b000000011011100010011110100000
5554`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config5"
5555`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_WIDTH 64
5556`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_DEPTH 1
5557`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_SLC 63:0
5558`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_INT_SLC 63:0
5559`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POSITION 0
5560`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_config5"
5561`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LOW_ADDR_WIDTH 0
5562`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_ADDR_RANGE 19:0
5563`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5564`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5565`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5566`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5567`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5568`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5569`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5570`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5571`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
5572`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5573`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
5574`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_INTERNAL_REG 0
5575`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_EXTERNAL_DECODE_REG 0
5576`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_ALIASED_FROM 0
5577`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_ZERO_TIME_OMNI 0
5578`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_JTAG_RD 1
5579`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_JTAG_WR 1
5580`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_SBUS_RD 1
5581`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_SBUS_WR 1
5582`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_RAP_RD 1
5583`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_HW_ACC_RAP_WR 1
5584`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_NUM_FIELDS 13
5585`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_FID 0
5586`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_SLC 31:13
5587`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_WIDTH 19
5588`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_INT_SLC 18:0
5589`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_POSITION 13
5590`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_FMASK 64'b0000000000000000000000000000000011111111111111111110000000000000
5591`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5592`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_POR_VALUE 19'b0000000000000000000
5593`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL2_FIELD_NAME "unused_cntl2"
5594`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_FID 1
5595`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_SLC 12:12
5596`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_WIDTH 1
5597`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_INT_SLC 0:0
5598`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_POSITION 12
5599`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
5600`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5601`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_POR_VALUE 1'b0
5602`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RCV_DET_TST_MODE_FIELD_NAME "rcv_det_tst_mode"
5603`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_FID 2
5604`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_SLC 11:11
5605`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_WIDTH 1
5606`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_INT_SLC 0:0
5607`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_POSITION 11
5608`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
5609`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5610`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_POR_VALUE 1'b0
5611`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_POLL_CMPLNC_DIS_FIELD_NAME "poll_cmplnc_dis"
5612`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_FID 3
5613`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_SLC 10:10
5614`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_WIDTH 1
5615`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_INT_SLC 0:0
5616`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_POSITION 10
5617`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
5618`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5619`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_POR_VALUE 1'b0
5620`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_TX_IDLE_TX_FTS_FIELD_NAME "tx_idle_tx_fts"
5621`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_FID 4
5622`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_SLC 9:9
5623`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_WIDTH 1
5624`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_INT_SLC 0:0
5625`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_POSITION 9
5626`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
5627`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5628`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_POR_VALUE 1'b0
5629`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_RX_FTS_RVR_LK_FIELD_NAME "rx_fts_rvr_lk"
5630`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_FID 5
5631`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_SLC 8:7
5632`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_WIDTH 2
5633`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_INT_SLC 1:0
5634`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_POSITION 7
5635`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_FMASK 64'b0000000000000000000000000000000000000000000000000000000110000000
5636`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5637`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_POR_VALUE 2'b00
5638`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL1_FIELD_NAME "unused_cntl1"
5639`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_FID 6
5640`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_SLC 6:6
5641`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_WIDTH 1
5642`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_INT_SLC 0:0
5643`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_POSITION 6
5644`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
5645`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5646`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_POR_VALUE 1'b0
5647`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_ACTIVE_FIELD_NAME "lpbk_entry_active"
5648`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_FID 7
5649`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_SLC 5:5
5650`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_WIDTH 1
5651`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_INT_SLC 0:0
5652`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_POSITION 5
5653`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
5654`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5655`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_POR_VALUE 1'b0
5656`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ENTRY_EXIT_FIELD_NAME "lpbk_entry_exit"
5657`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_FID 8
5658`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_SLC 4:4
5659`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_WIDTH 1
5660`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_INT_SLC 0:0
5661`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_POSITION 4
5662`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
5663`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5664`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_POR_VALUE 1'b0
5665`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_LPBK_ACTIVE_EXIT_FIELD_NAME "lpbk_active_exit"
5666`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_FID 9
5667`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_SLC 3:3
5668`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_WIDTH 1
5669`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_INT_SLC 0:0
5670`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_POSITION 3
5671`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
5672`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5673`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_POR_VALUE 1'b0
5674`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L1_IDLE_RCVRY_LK_FIELD_NAME "l1_idle_rcvry_lk"
5675`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_FID 10
5676`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_SLC 2:2
5677`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_WIDTH 1
5678`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_INT_SLC 0:0
5679`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_POSITION 2
5680`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
5681`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5682`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_POR_VALUE 1'b0
5683`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_TRN_CNTRL_RST_FIELD_NAME "l0_trn_cntrl_rst"
5684`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_FID 11
5685`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_SLC 1:1
5686`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_WIDTH 1
5687`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_INT_SLC 0:0
5688`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_POSITION 1
5689`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
5690`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5691`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_POR_VALUE 1'b0
5692`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_L0_LPBK_FIELD_NAME "l0_lpbk"
5693`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_FID 12
5694`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_SLC 0:0
5695`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_WIDTH 1
5696`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_INT_SLC 0:0
5697`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_POSITION 0
5698`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
5699`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5700`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_POR_VALUE 1'b0
5701`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CONFIG5_UNUSED_CNTL0_FIELD_NAME "unused_cntl0"
5702
5703//-------------------------------------------------------
5704//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1
5705//-------------------------------------------------------
5706
5707`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ADDR 20'b11011100010011110101
5708`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_ADDR 30'b000000011011100010011110101000
5709`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat1"
5710`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_WIDTH 64
5711`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_DEPTH 1
5712`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_SLC 63:0
5713`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_INT_SLC 63:0
5714`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_POSITION 0
5715`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat1"
5716`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LOW_ADDR_WIDTH 0
5717`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_ADDR_RANGE 19:0
5718`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5719`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5720`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5721`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5722`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5723`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5724`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5725`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5726`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
5727`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5728`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
5729`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_INTERNAL_REG 0
5730`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_EXTERNAL_DECODE_REG 0
5731`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_ALIASED_FROM 0
5732`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_ZERO_TIME_OMNI 0
5733`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_JTAG_RD 1
5734`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_JTAG_WR 1
5735`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_SBUS_RD 1
5736`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_SBUS_WR 1
5737`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_RAP_RD 1
5738`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_HW_ACC_RAP_WR 1
5739`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_NUM_FIELDS 9
5740`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_FID 0
5741`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_SLC 31:16
5742`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_WIDTH 16
5743`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_INT_SLC 15:0
5744`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_POSITION 16
5745`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
5746`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111110000000000000000
5747`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_POR_VALUE 16'b0000000000000000
5748`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_LN_EN_MSK_FIELD_NAME "rx_ln_en_msk"
5749`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_FID 1
5750`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_SLC 15:15
5751`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_WIDTH 1
5752`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_INT_SLC 0:0
5753`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_POSITION 15
5754`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
5755`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001000000000000000
5756`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_POR_VALUE 1'b0
5757`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_RX_ALGN_CMD_FIELD_NAME "rx_algn_cmd"
5758`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_FID 2
5759`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_SLC 14:14
5760`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_WIDTH 1
5761`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_INT_SLC 0:0
5762`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_POSITION 14
5763`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000100000000000000
5764`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000100000000000000
5765`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_POR_VALUE 1'b0
5766`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_MSTR_LN_SEL_FIELD_NAME "mstr_ln_sel"
5767`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_FID 3
5768`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_SLC 13:13
5769`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_WIDTH 1
5770`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_INT_SLC 0:0
5771`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_POSITION 13
5772`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
5773`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000010000000000000
5774`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_POR_VALUE 1'b0
5775`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_RX_FIELD_NAME "lnk_ot_rx"
5776`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_FID 4
5777`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_SLC 12:12
5778`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_WIDTH 1
5779`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_INT_SLC 0:0
5780`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_POSITION 12
5781`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
5782`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001000000000000
5783`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_POR_VALUE 1'b0
5784`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_OT_TX_FIELD_NAME "lnk_ot_tx"
5785`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_FID 5
5786`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_SLC 11:11
5787`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_WIDTH 1
5788`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_INT_SLC 0:0
5789`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_POSITION 11
5790`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
5791`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000100000000000
5792`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_POR_VALUE 1'b0
5793`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LN_RVRSD_FIELD_NAME "ln_rvrsd"
5794`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_FID 6
5795`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_SLC 10:10
5796`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_WIDTH 1
5797`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_INT_SLC 0:0
5798`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_POSITION 10
5799`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
5800`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
5801`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_POR_VALUE 1'b0
5802`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LNK_UP_DWN_STS_FIELD_NAME "lnk_up_dwn_sts"
5803`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_FID 7
5804`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_SLC 9:4
5805`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_WIDTH 6
5806`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_INT_SLC 5:0
5807`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_POSITION 4
5808`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000001111110000
5809`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001111110000
5810`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_POR_VALUE 6'b000000
5811`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_LTSSM_STATE_FIELD_NAME "ltssm_state"
5812`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_FID 8
5813`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_SLC 3:0
5814`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_WIDTH 4
5815`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_INT_SLC 3:0
5816`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_POSITION 0
5817`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001111
5818`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111
5819`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_POR_VALUE 4'b0000
5820`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT1_CNFG_LNK_WDTH_FIELD_NAME "cnfg_lnk_wdth"
5821
5822//-------------------------------------------------------
5823//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2
5824//-------------------------------------------------------
5825
5826`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ADDR 20'b11011100010011110110
5827`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_ADDR 30'b000000011011100010011110110000
5828`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat2"
5829`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_WIDTH 64
5830`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_DEPTH 1
5831`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_SLC 63:0
5832`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_INT_SLC 63:0
5833`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_POSITION 0
5834`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat2"
5835`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_LOW_ADDR_WIDTH 0
5836`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_ADDR_RANGE 19:0
5837`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5838`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5839`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5840`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5841`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5842`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5843`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5844`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5845`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
5846`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
5847`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
5848`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_INTERNAL_REG 0
5849`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_EXTERNAL_DECODE_REG 0
5850`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_ALIASED_FROM 0
5851`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_ZERO_TIME_OMNI 0
5852`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_JTAG_RD 1
5853`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_JTAG_WR 1
5854`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_SBUS_RD 1
5855`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_SBUS_WR 1
5856`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_RAP_RD 1
5857`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_HW_ACC_RAP_WR 1
5858`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_NUM_FIELDS 2
5859`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_FID 0
5860`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_SLC 31:16
5861`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_WIDTH 16
5862`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_INT_SLC 15:0
5863`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_POSITION 16
5864`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
5865`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111110000000000000000
5866`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_POR_VALUE 16'b0000000000000000
5867`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_TX_CMD_TX_PHY_FIELD_NAME "tx_cmd_tx_phy"
5868`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_FID 1
5869`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_SLC 15:0
5870`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_WIDTH 16
5871`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_INT_SLC 15:0
5872`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_POSITION 0
5873`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
5874`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
5875`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_POR_VALUE 16'b0000000000000000
5876`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT2_RX_CMD_RX_PHY_FIELD_NAME "rx_cmd_rx_phy"
5877
5878//-------------------------------------------------------
5879//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT
5880//-------------------------------------------------------
5881
5882`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ADDR 20'b11011100010011110111
5883`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_ADDR 30'b000000011011100010011110111000
5884`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_int"
5885`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_WIDTH 64
5886`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_DEPTH 1
5887`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_SLC 63:0
5888`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SLC 63:0
5889`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_POSITION 0
5890`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_int"
5891`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_LOW_ADDR_WIDTH 0
5892`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_ADDR_RANGE 19:0
5893`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_READ_MASK 64'b0000000000000000000000000000000010000000000000001111111111111111
5894`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_READ_ONLY_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
5895`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5896`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5897`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5898`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
5899`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
5900`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_RMASK 64'b0000000000000000000000000000000010000000000000001111111111111111
5901`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111110000000000000000
5902`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_LD_MASK 64'b0000000000000000000000000000000010000000000000001111111111111111
5903`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
5904`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INTERNAL_REG 0
5905`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_EXTERNAL_DECODE_REG 0
5906`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_ALIASED_FROM 0
5907`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_ZERO_TIME_OMNI 0
5908`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_JTAG_RD 1
5909`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_JTAG_WR 1
5910`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_SBUS_RD 1
5911`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_SBUS_WR 1
5912`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_RAP_RD 1
5913`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_HW_ACC_RAP_WR 1
5914`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_NUM_FIELDS 17
5915`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_FID 0
5916`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_SLC 31:31
5917`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_WIDTH 1
5918`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_INT_SLC 0:0
5919`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_POSITION 31
5920`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
5921`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_HW_LD_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
5922`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_POR_VALUE 1'b0
5923`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_ANY_FIELD_NAME "int_any"
5924`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_FID 1
5925`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_SLC 15:15
5926`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_WIDTH 1
5927`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_INT_SLC 0:0
5928`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_POSITION 15
5929`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
5930`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001000000000000000
5931`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_POR_VALUE 1'b0
5932`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_SKIP_OS_FIELD_NAME "int_skip_os"
5933`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_FID 2
5934`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_SLC 14:14
5935`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_WIDTH 1
5936`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_INT_SLC 0:0
5937`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_POSITION 14
5938`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_FMASK 64'b0000000000000000000000000000000000000000000000000100000000000000
5939`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000100000000000000
5940`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_POR_VALUE 1'b0
5941`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_FTS_FIELD_NAME "int_fts"
5942`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_FID 3
5943`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_SLC 13:13
5944`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_WIDTH 1
5945`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_INT_SLC 0:0
5946`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_POSITION 13
5947`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
5948`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000010000000000000
5949`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_POR_VALUE 1'b0
5950`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_RECOV_FIELD_NAME "int_ts2_recov"
5951`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_FID 4
5952`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_SLC 12:12
5953`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_WIDTH 1
5954`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_INT_SLC 0:0
5955`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_POSITION 12
5956`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
5957`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001000000000000
5958`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_POR_VALUE 1'b0
5959`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_8IDLE_DATA_FIELD_NAME "int_8idle_data"
5960`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_FID 5
5961`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_SLC 11:11
5962`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_WIDTH 1
5963`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_INT_SLC 0:0
5964`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_POSITION 11
5965`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
5966`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000100000000000
5967`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_POR_VALUE 1'b0
5968`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_IDLE_DATA_FIELD_NAME "int_idle_data"
5969`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_FID 6
5970`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_SLC 10:10
5971`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_WIDTH 1
5972`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_INT_SLC 0:0
5973`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_POSITION 10
5974`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
5975`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
5976`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_POR_VALUE 1'b0
5977`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_POLL_FIELD_NAME "int_tsx_poll"
5978`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_FID 7
5979`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_SLC 9:9
5980`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_WIDTH 1
5981`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_INT_SLC 0:0
5982`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_POSITION 9
5983`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
5984`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
5985`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_POR_VALUE 1'b0
5986`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_INV_FIELD_NAME "int_tsx_inv"
5987`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_FID 8
5988`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_SLC 8:8
5989`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_WIDTH 1
5990`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_INT_SLC 0:0
5991`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_POSITION 8
5992`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
5993`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
5994`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_POR_VALUE 1'b0
5995`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_EXIT_FIELD_NAME "int_eidle_exit"
5996`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_FID 9
5997`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_SLC 7:7
5998`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_WIDTH 1
5999`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_INT_SLC 0:0
6000`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_POSITION 7
6001`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
6002`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
6003`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_POR_VALUE 1'b0
6004`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_COMP_FIELD_NAME "int_tsx_comp"
6005`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_FID 10
6006`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_SLC 6:6
6007`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_WIDTH 1
6008`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_INT_SLC 0:0
6009`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_POSITION 6
6010`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
6011`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
6012`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_POR_VALUE 1'b0
6013`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_LB_FIELD_NAME "int_tsx_lb"
6014`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_FID 11
6015`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_SLC 5:5
6016`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_WIDTH 1
6017`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_INT_SLC 0:0
6018`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_POSITION 5
6019`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
6020`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
6021`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_POR_VALUE 1'b0
6022`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_DIS_FIELD_NAME "int_tsx_dis"
6023`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_FID 12
6024`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_SLC 4:4
6025`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_WIDTH 1
6026`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_INT_SLC 0:0
6027`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_POSITION 4
6028`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
6029`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
6030`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_POR_VALUE 1'b0
6031`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TSX_RST_FIELD_NAME "int_tsx_rst"
6032`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_FID 13
6033`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_SLC 3:3
6034`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_WIDTH 1
6035`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_INT_SLC 0:0
6036`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_POSITION 3
6037`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
6038`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
6039`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_POR_VALUE 1'b0
6040`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_EIDLE_FIELD_NAME "int_eidle"
6041`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_FID 14
6042`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_SLC 2:2
6043`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_WIDTH 1
6044`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_INT_SLC 0:0
6045`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_POSITION 2
6046`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
6047`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
6048`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_POR_VALUE 1'b0
6049`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS2_FIELD_NAME "int_ts2"
6050`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_FID 15
6051`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_SLC 1:1
6052`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_WIDTH 1
6053`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_INT_SLC 0:0
6054`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_POSITION 1
6055`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
6056`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
6057`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_POR_VALUE 1'b0
6058`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_TS1_FIELD_NAME "int_ts1"
6059`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_FID 16
6060`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_SLC 0:0
6061`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_WIDTH 1
6062`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_INT_SLC 0:0
6063`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_POSITION 0
6064`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
6065`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
6066`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_POR_VALUE 1'b0
6067`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_INT_INT_NONE_FIELD_NAME "int_none"
6068
6069//-------------------------------------------------------
6070//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST
6071//-------------------------------------------------------
6072
6073`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ADDR 20'b11011100010011111000
6074`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_ADDR 30'b000000011011100010011111000000
6075`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_tst"
6076`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_WIDTH 64
6077`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_DEPTH 1
6078`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_SLC 63:0
6079`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_INT_SLC 63:0
6080`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_POSITION 0
6081`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_tst"
6082`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_LOW_ADDR_WIDTH 0
6083`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_ADDR_RANGE 19:0
6084`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
6085`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6086`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6087`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6088`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_SET_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
6089`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6090`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6091`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
6092`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
6093`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
6094`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
6095`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_INTERNAL_REG 0
6096`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_EXTERNAL_DECODE_REG 0
6097`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_ALIASED_FROM 0
6098`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_ZERO_TIME_OMNI 0
6099`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_JTAG_RD 1
6100`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_JTAG_WR 1
6101`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_SBUS_RD 1
6102`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_SBUS_WR 1
6103`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_RAP_RD 1
6104`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_HW_ACC_RAP_WR 1
6105`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_NUM_FIELDS 16
6106`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_FID 0
6107`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_SLC 15:15
6108`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_WIDTH 1
6109`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_INT_SLC 0:0
6110`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_POSITION 15
6111`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
6112`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001000000000000000
6113`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_POR_VALUE 1'b0
6114`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_SKIP_OS_FIELD_NAME "tst_skip_os"
6115`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_FID 1
6116`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_SLC 14:14
6117`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_WIDTH 1
6118`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_INT_SLC 0:0
6119`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_POSITION 14
6120`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_FMASK 64'b0000000000000000000000000000000000000000000000000100000000000000
6121`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000100000000000000
6122`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_POR_VALUE 1'b0
6123`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_FTS_FIELD_NAME "tst_fts"
6124`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_FID 2
6125`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_SLC 13:13
6126`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_WIDTH 1
6127`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_INT_SLC 0:0
6128`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_POSITION 13
6129`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
6130`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000010000000000000
6131`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_POR_VALUE 1'b0
6132`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_RECOV_FIELD_NAME "tst_ts2_recov"
6133`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_FID 3
6134`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_SLC 12:12
6135`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_WIDTH 1
6136`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_INT_SLC 0:0
6137`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_POSITION 12
6138`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
6139`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001000000000000
6140`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_POR_VALUE 1'b0
6141`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_8IDLE_DATA_FIELD_NAME "tst_8idle_data"
6142`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_FID 4
6143`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_SLC 11:11
6144`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_WIDTH 1
6145`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_INT_SLC 0:0
6146`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_POSITION 11
6147`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
6148`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000100000000000
6149`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_POR_VALUE 1'b0
6150`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_IDLE_DATA_FIELD_NAME "tst_idle_data"
6151`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_FID 5
6152`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_SLC 10:10
6153`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_WIDTH 1
6154`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_INT_SLC 0:0
6155`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_POSITION 10
6156`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
6157`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
6158`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_POR_VALUE 1'b0
6159`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_POLL_FIELD_NAME "tst_tsx_poll"
6160`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_FID 6
6161`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_SLC 9:9
6162`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_WIDTH 1
6163`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_INT_SLC 0:0
6164`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_POSITION 9
6165`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
6166`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
6167`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_POR_VALUE 1'b0
6168`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_INV_FIELD_NAME "tst_tsx_inv"
6169`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_FID 7
6170`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_SLC 8:8
6171`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_WIDTH 1
6172`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_INT_SLC 0:0
6173`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_POSITION 8
6174`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
6175`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
6176`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_POR_VALUE 1'b0
6177`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_EXIT_FIELD_NAME "tst_eidle_exit"
6178`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_FID 8
6179`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_SLC 7:7
6180`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_WIDTH 1
6181`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_INT_SLC 0:0
6182`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_POSITION 7
6183`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
6184`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
6185`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_POR_VALUE 1'b0
6186`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_COMP_FIELD_NAME "tst_tsx_comp"
6187`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_FID 9
6188`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_SLC 6:6
6189`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_WIDTH 1
6190`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_INT_SLC 0:0
6191`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_POSITION 6
6192`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
6193`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
6194`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_POR_VALUE 1'b0
6195`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_LB_FIELD_NAME "tst_tsx_lb"
6196`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_FID 10
6197`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_SLC 5:5
6198`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_WIDTH 1
6199`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_INT_SLC 0:0
6200`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_POSITION 5
6201`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
6202`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
6203`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_POR_VALUE 1'b0
6204`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_DIS_FIELD_NAME "tst_tsx_dis"
6205`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_FID 11
6206`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_SLC 4:4
6207`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_WIDTH 1
6208`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_INT_SLC 0:0
6209`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_POSITION 4
6210`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
6211`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
6212`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_POR_VALUE 1'b0
6213`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TSX_RST_FIELD_NAME "tst_tsx_rst"
6214`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_FID 12
6215`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_SLC 3:3
6216`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_WIDTH 1
6217`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_INT_SLC 0:0
6218`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_POSITION 3
6219`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
6220`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
6221`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_POR_VALUE 1'b0
6222`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_EIDLE_FIELD_NAME "tst_eidle"
6223`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_FID 13
6224`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_SLC 2:2
6225`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_WIDTH 1
6226`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_INT_SLC 0:0
6227`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_POSITION 2
6228`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
6229`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
6230`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_POR_VALUE 1'b0
6231`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS2_FIELD_NAME "tst_ts2"
6232`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_FID 14
6233`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_SLC 1:1
6234`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_WIDTH 1
6235`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_INT_SLC 0:0
6236`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_POSITION 1
6237`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
6238`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
6239`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_POR_VALUE 1'b0
6240`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_TS1_FIELD_NAME "tst_ts1"
6241`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_FID 15
6242`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_SLC 0:0
6243`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_WIDTH 1
6244`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_INT_SLC 0:0
6245`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_POSITION 0
6246`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
6247`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
6248`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_POR_VALUE 1'b0
6249`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_TST_TST_NONE_FIELD_NAME "tst_none"
6250
6251//-------------------------------------------------------
6252//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK
6253//-------------------------------------------------------
6254
6255`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ADDR 20'b11011100010011111001
6256`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_ADDR 30'b000000011011100010011111001000
6257`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_msk"
6258`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_WIDTH 64
6259`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_DEPTH 1
6260`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_SLC 63:0
6261`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_INT_SLC 63:0
6262`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_POSITION 0
6263`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_msk"
6264`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_LOW_ADDR_WIDTH 0
6265`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_ADDR_RANGE 19:0
6266`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_READ_MASK 64'b0000000000000000000000000000000010000000000000001111111111111111
6267`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6268`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_WRITE_MASK 64'b0000000000000000000000000000000010000000000000001111111111111111
6269`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6270`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6271`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6272`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6273`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_RMASK 64'b0000000000000000000000000000000010000000000000001111111111111111
6274`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111111111110000000000000000
6275`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6276`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_POR_VALUE 64'b0000000000000000000000000000000010000000000000001111111111111111
6277`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_INTERNAL_REG 0
6278`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_EXTERNAL_DECODE_REG 0
6279`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_ALIASED_FROM 0
6280`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_ZERO_TIME_OMNI 0
6281`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_JTAG_RD 1
6282`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_JTAG_WR 1
6283`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_SBUS_RD 1
6284`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_SBUS_WR 1
6285`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_RAP_RD 1
6286`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_HW_ACC_RAP_WR 1
6287`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_NUM_FIELDS 17
6288`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_FID 0
6289`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_SLC 31:31
6290`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_WIDTH 1
6291`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_INT_SLC 0:0
6292`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_POSITION 31
6293`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
6294`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6295`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_POR_VALUE 1'b1
6296`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_ANY_FIELD_NAME "msk_any"
6297`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_FID 1
6298`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_SLC 15:15
6299`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_WIDTH 1
6300`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_INT_SLC 0:0
6301`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_POSITION 15
6302`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
6303`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6304`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_POR_VALUE 1'b1
6305`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_SKIP_OS_FIELD_NAME "msk_skip_os"
6306`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_FID 2
6307`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_SLC 14:14
6308`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_WIDTH 1
6309`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_INT_SLC 0:0
6310`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_POSITION 14
6311`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_FMASK 64'b0000000000000000000000000000000000000000000000000100000000000000
6312`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6313`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_POR_VALUE 1'b1
6314`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_FTS_FIELD_NAME "msk_fts"
6315`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_FID 3
6316`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_SLC 13:13
6317`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_WIDTH 1
6318`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_INT_SLC 0:0
6319`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_POSITION 13
6320`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
6321`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6322`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_POR_VALUE 1'b1
6323`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_RECOV_FIELD_NAME "msk_ts2_recov"
6324`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_FID 4
6325`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_SLC 12:12
6326`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_WIDTH 1
6327`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_INT_SLC 0:0
6328`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_POSITION 12
6329`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
6330`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6331`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_POR_VALUE 1'b1
6332`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_8IDLE_DATA_FIELD_NAME "msk_8idle_data"
6333`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_FID 5
6334`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_SLC 11:11
6335`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_WIDTH 1
6336`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_INT_SLC 0:0
6337`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_POSITION 11
6338`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
6339`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6340`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_POR_VALUE 1'b1
6341`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_IDLE_DATA_FIELD_NAME "msk_idle_data"
6342`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_FID 6
6343`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_SLC 10:10
6344`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_WIDTH 1
6345`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_INT_SLC 0:0
6346`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_POSITION 10
6347`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
6348`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6349`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_POR_VALUE 1'b1
6350`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_POLL_FIELD_NAME "msk_tsx_poll"
6351`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_FID 7
6352`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_SLC 9:9
6353`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_WIDTH 1
6354`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_INT_SLC 0:0
6355`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_POSITION 9
6356`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
6357`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6358`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_POR_VALUE 1'b1
6359`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_INV_FIELD_NAME "msk_tsx_inv"
6360`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_FID 8
6361`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_SLC 8:8
6362`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_WIDTH 1
6363`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_INT_SLC 0:0
6364`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_POSITION 8
6365`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
6366`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6367`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_POR_VALUE 1'b1
6368`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_EXIT_FIELD_NAME "msk_eidle_exit"
6369`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_FID 9
6370`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_SLC 7:7
6371`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_WIDTH 1
6372`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_INT_SLC 0:0
6373`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_POSITION 7
6374`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
6375`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6376`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_POR_VALUE 1'b1
6377`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_COMP_FIELD_NAME "msk_tsx_comp"
6378`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_FID 10
6379`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_SLC 6:6
6380`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_WIDTH 1
6381`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_INT_SLC 0:0
6382`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_POSITION 6
6383`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
6384`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6385`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_POR_VALUE 1'b1
6386`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_LB_FIELD_NAME "msk_tsx_lb"
6387`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_FID 11
6388`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_SLC 5:5
6389`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_WIDTH 1
6390`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_INT_SLC 0:0
6391`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_POSITION 5
6392`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
6393`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6394`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_POR_VALUE 1'b1
6395`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_DIS_FIELD_NAME "msk_tsx_dis"
6396`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_FID 12
6397`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_SLC 4:4
6398`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_WIDTH 1
6399`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_INT_SLC 0:0
6400`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_POSITION 4
6401`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
6402`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6403`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_POR_VALUE 1'b1
6404`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TSX_RST_FIELD_NAME "msk_tsx_rst"
6405`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_FID 13
6406`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_SLC 3:3
6407`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_WIDTH 1
6408`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_INT_SLC 0:0
6409`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_POSITION 3
6410`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
6411`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6412`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_POR_VALUE 1'b1
6413`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_EIDLE_FIELD_NAME "msk_eidle"
6414`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_FID 14
6415`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_SLC 2:2
6416`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_WIDTH 1
6417`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_INT_SLC 0:0
6418`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_POSITION 2
6419`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
6420`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6421`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_POR_VALUE 1'b1
6422`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS2_FIELD_NAME "msk_ts2"
6423`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_FID 15
6424`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_SLC 1:1
6425`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_WIDTH 1
6426`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_INT_SLC 0:0
6427`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_POSITION 1
6428`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
6429`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6430`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_POR_VALUE 1'b1
6431`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_TS1_FIELD_NAME "msk_ts1"
6432`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_FID 16
6433`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_SLC 0:0
6434`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_WIDTH 1
6435`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_INT_SLC 0:0
6436`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_POSITION 0
6437`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
6438`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6439`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_POR_VALUE 1'b1
6440`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_MSK_MSK_NONE_FIELD_NAME "msk_none"
6441
6442//-------------------------------------------------------
6443//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN
6444//-------------------------------------------------------
6445
6446`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ADDR 20'b11011100010011111010
6447`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_ADDR 30'b000000011011100010011111010000
6448`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat_wr_en"
6449`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_WIDTH 64
6450`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_DEPTH 1
6451`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_SLC 63:0
6452`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_INT_SLC 63:0
6453`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_POSITION 0
6454`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_ltssm_stat_wr_en"
6455`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LOW_ADDR_WIDTH 0
6456`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_ADDR_RANGE 19:0
6457`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6458`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6459`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6460`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6461`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6462`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6463`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6464`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6465`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
6466`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6467`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
6468`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_INTERNAL_REG 0
6469`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_EXTERNAL_DECODE_REG 0
6470`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_ALIASED_FROM 0
6471`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_ZERO_TIME_OMNI 0
6472`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_JTAG_RD 1
6473`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_JTAG_WR 1
6474`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_SBUS_RD 1
6475`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_SBUS_WR 1
6476`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_RAP_RD 1
6477`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_HW_ACC_RAP_WR 1
6478`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_NUM_FIELDS 12
6479`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_FID 0
6480`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_SLC 31:11
6481`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_WIDTH 21
6482`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_INT_SLC 20:0
6483`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_POSITION 11
6484`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_FMASK 64'b0000000000000000000000000000000011111111111111111111100000000000
6485`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6486`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_POR_VALUE 21'b000000000000000000000
6487`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_UNUSED_CNTL_FIELD_NAME "unused_cntl"
6488`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_FID 1
6489`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_SLC 10:10
6490`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_WIDTH 1
6491`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_INT_SLC 0:0
6492`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_POSITION 10
6493`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
6494`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6495`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_POR_VALUE 1'b0
6496`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_TX_CMD_TX_PHY_FIELD_NAME "tx_cmd_tx_phy"
6497`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_FID 2
6498`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_SLC 9:9
6499`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_WIDTH 1
6500`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_INT_SLC 0:0
6501`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_POSITION 9
6502`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
6503`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6504`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_POR_VALUE 1'b0
6505`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_CMD_RX_PHY_FIELD_NAME "rx_cmd_rx_phy"
6506`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_FID 3
6507`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_SLC 8:8
6508`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_WIDTH 1
6509`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_INT_SLC 0:0
6510`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_POSITION 8
6511`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
6512`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6513`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_POR_VALUE 1'b0
6514`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_LN_EN_MSK_FIELD_NAME "rx_ln_en_msk"
6515`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_FID 4
6516`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_SLC 7:7
6517`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_WIDTH 1
6518`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_INT_SLC 0:0
6519`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_POSITION 7
6520`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
6521`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6522`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_POR_VALUE 1'b0
6523`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_RX_ALGN_CMD_FIELD_NAME "rx_algn_cmd"
6524`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_FID 5
6525`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_SLC 6:6
6526`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_WIDTH 1
6527`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_INT_SLC 0:0
6528`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_POSITION 6
6529`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
6530`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6531`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_POR_VALUE 1'b0
6532`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_MSTR_LN_SEL_FIELD_NAME "mstr_ln_sel"
6533`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_FID 6
6534`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_SLC 5:5
6535`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_WIDTH 1
6536`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_INT_SLC 0:0
6537`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_POSITION 5
6538`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
6539`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6540`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_POR_VALUE 1'b0
6541`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_RX_FIELD_NAME "lnk_ot_rx"
6542`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_FID 7
6543`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_SLC 4:4
6544`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_WIDTH 1
6545`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_INT_SLC 0:0
6546`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_POSITION 4
6547`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
6548`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6549`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_POR_VALUE 1'b0
6550`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_OT_TX_FIELD_NAME "lnk_ot_tx"
6551`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_FID 8
6552`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_SLC 3:3
6553`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_WIDTH 1
6554`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_INT_SLC 0:0
6555`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_POSITION 3
6556`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
6557`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6558`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_POR_VALUE 1'b0
6559`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LN_RVRSD_FIELD_NAME "ln_rvrsd"
6560`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_FID 9
6561`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_SLC 2:2
6562`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_WIDTH 1
6563`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_INT_SLC 0:0
6564`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_POSITION 2
6565`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
6566`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6567`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_POR_VALUE 1'b0
6568`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LNK_UP_DWN_STS_FIELD_NAME "lnk_up_dwn_sts"
6569`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_FID 10
6570`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_SLC 1:1
6571`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_WIDTH 1
6572`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_INT_SLC 0:0
6573`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_POSITION 1
6574`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
6575`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6576`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_POR_VALUE 1'b0
6577`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_LTSSM_STATE_FIELD_NAME "ltssm_state"
6578`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_FID 11
6579`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_SLC 0:0
6580`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_WIDTH 1
6581`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_INT_SLC 0:0
6582`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_POSITION 0
6583`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
6584`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6585`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_POR_VALUE 1'b0
6586`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_STAT_WR_EN_CNFG_LNK_WDTH_FIELD_NAME "cnfg_lnk_wdth"
6587
6588//-------------------------------------------------------
6589//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1
6590//-------------------------------------------------------
6591
6592`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ADDR 20'b11011100010100000000
6593`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_ADDR 30'b000000011011100010100000000000
6594`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config1"
6595`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_WIDTH 64
6596`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_DEPTH 1
6597`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_SLC 63:0
6598`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_INT_SLC 63:0
6599`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_POSITION 0
6600`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config1"
6601`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LOW_ADDR_WIDTH 0
6602`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_ADDR_RANGE 19:0
6603`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6604`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6605`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6606`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6607`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6608`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6609`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6610`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6611`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
6612`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6613`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_POR_VALUE 64'b0000000000000000000000000000000000000000000010001001000000011001
6614`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_INTERNAL_REG 0
6615`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_EXTERNAL_DECODE_REG 0
6616`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_ALIASED_FROM 0
6617`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_ZERO_TIME_OMNI 0
6618`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_JTAG_RD 1
6619`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_JTAG_WR 1
6620`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_SBUS_RD 1
6621`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_SBUS_WR 1
6622`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_RAP_RD 1
6623`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_HW_ACC_RAP_WR 1
6624`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_NUM_FIELDS 11
6625`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_FID 0
6626`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_SLC 31:28
6627`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_WIDTH 4
6628`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_INT_SLC 3:0
6629`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_POSITION 28
6630`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_FMASK 64'b0000000000000000000000000000000011110000000000000000000000000000
6631`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6632`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_POR_VALUE 4'b0000
6633`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL1_FIELD_NAME "unused_cntl1"
6634`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_FID 1
6635`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_SLC 27:24
6636`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_WIDTH 4
6637`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_INT_SLC 3:0
6638`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_POSITION 24
6639`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_FMASK 64'b0000000000000000000000000000000000001111000000000000000000000000
6640`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6641`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_POR_VALUE 4'b0000
6642`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_STM_SEL_FIELD_NAME "stm_sel"
6643`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_FID 2
6644`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_SLC 23:22
6645`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_WIDTH 2
6646`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_INT_SLC 1:0
6647`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_POSITION 22
6648`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_FMASK 64'b0000000000000000000000000000000000000000110000000000000000000000
6649`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6650`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_POR_VALUE 2'b00
6651`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_UNUSED_CNTL2_FIELD_NAME "unused_cntl2"
6652`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_FID 3
6653`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_SLC 21:20
6654`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_WIDTH 2
6655`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_INT_SLC 1:0
6656`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_POSITION 20
6657`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_FMASK 64'b0000000000000000000000000000000000000000001100000000000000000000
6658`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6659`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_POR_VALUE 2'b00
6660`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_SEL_FIELD_NAME "rev_lpbk_sel"
6661`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_FID 4
6662`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_SLC 19:19
6663`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_WIDTH 1
6664`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_INT_SLC 0:0
6665`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_POSITION 19
6666`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_FMASK 64'b0000000000000000000000000000000000000000000010000000000000000000
6667`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6668`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_POR_VALUE 1'b1
6669`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_REV_LPBK_MODE_FIELD_NAME "rev_lpbk_mode"
6670`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_FID 5
6671`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_SLC 18:18
6672`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_WIDTH 1
6673`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_INT_SLC 0:0
6674`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_POSITION 18
6675`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_FMASK 64'b0000000000000000000000000000000000000000000001000000000000000000
6676`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6677`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_POR_VALUE 1'b0
6678`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_ENB_FIELD_NAME "lpbk_enb"
6679`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_FID 6
6680`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_SLC 17:16
6681`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_WIDTH 2
6682`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_INT_SLC 1:0
6683`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_POSITION 16
6684`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_FMASK 64'b0000000000000000000000000000000000000000000000110000000000000000
6685`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6686`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_POR_VALUE 2'b00
6687`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_LPBK_MODE_SEL_FIELD_NAME "lpbk_mode_sel"
6688`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_FID 7
6689`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_SLC 15:15
6690`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_WIDTH 1
6691`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_INT_SLC 0:0
6692`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_POSITION 15
6693`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
6694`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6695`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_POR_VALUE 1'b1
6696`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_FLTR_EN_FIELD_NAME "rxlos_fltr_en"
6697`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_FID 8
6698`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_SLC 14:12
6699`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_WIDTH 3
6700`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_INT_SLC 2:0
6701`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_POSITION 12
6702`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_FMASK 64'b0000000000000000000000000000000000000000000000000111000000000000
6703`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6704`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_POR_VALUE 3'b001
6705`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_ADJUST_FIELD_NAME "rxlos_adjust"
6706`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_FID 9
6707`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_SLC 11:8
6708`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_WIDTH 4
6709`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_INT_SLC 3:0
6710`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_POSITION 8
6711`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_FMASK 64'b0000000000000000000000000000000000000000000000000000111100000000
6712`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6713`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_POR_VALUE 4'b0000
6714`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_SMPL_RT_FIELD_NAME "rxlos_smpl_rt"
6715`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_FID 10
6716`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_SLC 7:0
6717`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_WIDTH 8
6718`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_INT_SLC 7:0
6719`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_POSITION 0
6720`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
6721`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6722`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_POR_VALUE 8'b00011001
6723`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG1_RXLOS_THRSH_CN_FIELD_NAME "rxlos_thrsh_cn"
6724
6725//-------------------------------------------------------
6726//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2
6727//-------------------------------------------------------
6728
6729`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ADDR 20'b11011100010100000001
6730`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_ADDR 30'b000000011011100010100000001000
6731`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config2"
6732`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_WIDTH 64
6733`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_DEPTH 1
6734`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_SLC 63:0
6735`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_INT_SLC 63:0
6736`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_POSITION 0
6737`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config2"
6738`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_LOW_ADDR_WIDTH 0
6739`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_ADDR_RANGE 19:0
6740`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6741`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6742`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6743`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6744`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6745`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6746`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6747`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6748`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
6749`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6750`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_POR_VALUE 64'b0000000000000000000000000000000010100001101000111110000101110101
6751`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_INTERNAL_REG 0
6752`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_EXTERNAL_DECODE_REG 0
6753`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_ALIASED_FROM 0
6754`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_ZERO_TIME_OMNI 0
6755`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_JTAG_RD 1
6756`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_JTAG_WR 1
6757`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_SBUS_RD 1
6758`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_SBUS_WR 1
6759`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_RAP_RD 1
6760`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_HW_ACC_RAP_WR 1
6761`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_NUM_FIELDS 14
6762`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_FID 0
6763`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_SLC 31:30
6764`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_WIDTH 2
6765`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_INT_SLC 1:0
6766`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_POSITION 30
6767`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_FMASK 64'b0000000000000000000000000000000011000000000000000000000000000000
6768`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6769`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_POR_VALUE 2'b10
6770`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VPULSE_CTL_FIELD_NAME "tx_vpulse_ctl"
6771`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_FID 1
6772`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_SLC 29:28
6773`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_WIDTH 2
6774`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_INT_SLC 1:0
6775`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_POSITION 28
6776`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_FMASK 64'b0000000000000000000000000000000000110000000000000000000000000000
6777`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6778`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_POR_VALUE 2'b10
6779`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VMUX_CTL_FIELD_NAME "tx_vmux_ctl"
6780`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_FID 2
6781`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_SLC 27:25
6782`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_WIDTH 3
6783`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_INT_SLC 2:0
6784`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_POSITION 25
6785`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_FMASK 64'b0000000000000000000000000000000000001110000000000000000000000000
6786`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6787`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_POR_VALUE 3'b000
6788`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_RISE_FALL_FIELD_NAME "tx_rise_fall"
6789`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_FID 3
6790`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_SLC 24:22
6791`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_WIDTH 3
6792`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_INT_SLC 2:0
6793`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_POSITION 22
6794`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_FMASK 64'b0000000000000000000000000000000000000001110000000000000000000000
6795`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6796`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_POR_VALUE 3'b110
6797`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PRE_EMPH_FIELD_NAME "tx_pre_emph"
6798`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_FID 4
6799`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_SLC 21:18
6800`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_WIDTH 4
6801`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_INT_SLC 3:0
6802`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_POSITION 18
6803`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_FMASK 64'b0000000000000000000000000000000000000000001111000000000000000000
6804`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6805`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_POR_VALUE 4'b1000
6806`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_VSWNG_CTL_FIELD_NAME "tx_vswng_ctl"
6807`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_FID 5
6808`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_SLC 17:16
6809`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_WIDTH 2
6810`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_INT_SLC 1:0
6811`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_POSITION 16
6812`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_FMASK 64'b0000000000000000000000000000000000000000000000110000000000000000
6813`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6814`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_POR_VALUE 2'b11
6815`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_ZERO_CTL_FIELD_NAME "tx_pll_zero_ctl"
6816`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_FID 6
6817`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_SLC 15:14
6818`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_WIDTH 2
6819`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_INT_SLC 1:0
6820`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_POSITION 14
6821`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_FMASK 64'b0000000000000000000000000000000000000000000000001100000000000000
6822`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6823`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_POR_VALUE 2'b11
6824`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_PLL_POLE_CTL_FIELD_NAME "tx_pll_pole_ctl"
6825`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_FID 7
6826`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_SLC 13:12
6827`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_WIDTH 2
6828`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_INT_SLC 1:0
6829`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_POSITION 12
6830`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_FMASK 64'b0000000000000000000000000000000000000000000000000011000000000000
6831`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6832`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_POR_VALUE 2'b10
6833`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_ZERO_CTL_FIELD_NAME "rx_pll_zero_ctl"
6834`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_FID 8
6835`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_SLC 11:10
6836`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_WIDTH 2
6837`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_INT_SLC 1:0
6838`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_POSITION 10
6839`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_FMASK 64'b0000000000000000000000000000000000000000000000000000110000000000
6840`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6841`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_POR_VALUE 2'b00
6842`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_PLL_POLE_CTL_FIELD_NAME "rx_pll_pole_ctl"
6843`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_FID 9
6844`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_SLC 9:6
6845`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_WIDTH 4
6846`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_INT_SLC 3:0
6847`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_POSITION 6
6848`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000
6849`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6850`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_POR_VALUE 4'b0101
6851`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_EQLIZR_CTL_FIELD_NAME "rx_eqlizr_ctl"
6852`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_FID 10
6853`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_SLC 5:5
6854`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_WIDTH 1
6855`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_INT_SLC 0:0
6856`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_POSITION 5
6857`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
6858`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6859`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_POR_VALUE 1'b1
6860`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_OHM_SEL_FIELD_NAME "ohm_sel"
6861`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_FID 11
6862`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_SLC 4:4
6863`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_WIDTH 1
6864`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_INT_SLC 0:0
6865`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_POSITION 4
6866`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
6867`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6868`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_POR_VALUE 1'b1
6869`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RTRIMEN_FIELD_NAME "rtrimen"
6870`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_FID 12
6871`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_SLC 3:2
6872`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_WIDTH 2
6873`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_INT_SLC 1:0
6874`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_POSITION 2
6875`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001100
6876`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6877`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_POR_VALUE 2'b01
6878`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_TX_TERM_FIELD_NAME "tx_term"
6879`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_FID 13
6880`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_SLC 1:0
6881`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_WIDTH 2
6882`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_INT_SLC 1:0
6883`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_POSITION 0
6884`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011
6885`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6886`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_POR_VALUE 2'b01
6887`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG2_RX_TERM_FIELD_NAME "rx_term"
6888
6889//-------------------------------------------------------
6890//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3
6891//-------------------------------------------------------
6892
6893`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ADDR 20'b11011100010100000010
6894`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_ADDR 30'b000000011011100010100000010000
6895`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config3"
6896`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_WIDTH 64
6897`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_DEPTH 1
6898`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_SLC 63:0
6899`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_INT_SLC 63:0
6900`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_POSITION 0
6901`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config3"
6902`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_LOW_ADDR_WIDTH 0
6903`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_ADDR_RANGE 19:0
6904`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6905`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6906`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6907`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6908`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6909`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6910`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6911`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
6912`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
6913`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6914`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_POR_VALUE 64'b0000000000000000000000000000000000000000010001000000000111110100
6915`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_INTERNAL_REG 0
6916`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_EXTERNAL_DECODE_REG 0
6917`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_ALIASED_FROM 0
6918`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_ZERO_TIME_OMNI 0
6919`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_JTAG_RD 1
6920`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_JTAG_WR 1
6921`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_SBUS_RD 1
6922`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_SBUS_WR 1
6923`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_RAP_RD 1
6924`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_HW_ACC_RAP_WR 1
6925`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_NUM_FIELDS 8
6926`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_FID 0
6927`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_SLC 31:27
6928`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_WIDTH 5
6929`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_INT_SLC 4:0
6930`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_POSITION 27
6931`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_FMASK 64'b0000000000000000000000000000000011111000000000000000000000000000
6932`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6933`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_POR_VALUE 5'b00000
6934`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_UNUSED_CNTL3_FIELD_NAME "unused_cntl3"
6935`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_FID 1
6936`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_SLC 26:26
6937`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_WIDTH 1
6938`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_INT_SLC 0:0
6939`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_POSITION 26
6940`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_FMASK 64'b0000000000000000000000000000000000000100000000000000000000000000
6941`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6942`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_POR_VALUE 1'b0
6943`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_OUT_BIAS_CTL_FIELD_NAME "out_bias_ctl"
6944`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_FID 2
6945`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_SLC 25:24
6946`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_WIDTH 2
6947`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_INT_SLC 1:0
6948`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_POSITION 24
6949`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_FMASK 64'b0000000000000000000000000000000000000011000000000000000000000000
6950`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6951`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_POR_VALUE 2'b00
6952`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_RCV_DET_FIELD_NAME "tx_rcv_det"
6953`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_FID 3
6954`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_SLC 23:23
6955`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_WIDTH 1
6956`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_INT_SLC 0:0
6957`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_POSITION 23
6958`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_FMASK 64'b0000000000000000000000000000000000000000100000000000000000000000
6959`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6960`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_POR_VALUE 1'b0
6961`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_HLF_RT_CTL_FIELD_NAME "tx_pll_hlf_rt_ctl"
6962`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_FID 4
6963`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_SLC 22:20
6964`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_WIDTH 3
6965`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_INT_SLC 2:0
6966`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_POSITION 20
6967`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_FMASK 64'b0000000000000000000000000000000000000000011100000000000000000000
6968`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6969`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_POR_VALUE 3'b100
6970`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_TX_PLL_FDBK_DIV_FIELD_NAME "tx_pll_fdbk_div"
6971`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_FID 5
6972`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_SLC 19:19
6973`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_WIDTH 1
6974`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_INT_SLC 0:0
6975`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_POSITION 19
6976`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_FMASK 64'b0000000000000000000000000000000000000000000010000000000000000000
6977`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6978`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_POR_VALUE 1'b0
6979`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_HLF_RT_CTL_FIELD_NAME "rx_pll_hlf_rt_ctl"
6980`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_FID 6
6981`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_SLC 18:16
6982`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_WIDTH 3
6983`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_INT_SLC 2:0
6984`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_POSITION 16
6985`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_FMASK 64'b0000000000000000000000000000000000000000000001110000000000000000
6986`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6987`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_POR_VALUE 3'b100
6988`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_RX_PLL_FDBK_DIV_FIELD_NAME "rx_pll_fdbk_div"
6989`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_FID 7
6990`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_SLC 15:0
6991`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_WIDTH 16
6992`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_INT_SLC 15:0
6993`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_POSITION 0
6994`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
6995`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
6996`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_POR_VALUE 16'b0000000111110100
6997`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG3_BIT_LCK_TM_FIELD_NAME "bit_lck_tm"
6998
6999//-------------------------------------------------------
7000//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4
7001//-------------------------------------------------------
7002
7003`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ADDR 20'b11011100010100000011
7004`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_ADDR 30'b000000011011100010100000011000
7005`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config4"
7006`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_WIDTH 64
7007`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_DEPTH 1
7008`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_SLC 63:0
7009`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INT_SLC 63:0
7010`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_POSITION 0
7011`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config4"
7012`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_LOW_ADDR_WIDTH 0
7013`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_ADDR_RANGE 19:0
7014`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7015`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7016`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7017`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7018`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7019`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7020`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7021`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7022`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
7023`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7024`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_POR_VALUE 64'b0000000000000000000000000000000000000000000000011110100001001000
7025`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INTERNAL_REG 0
7026`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_EXTERNAL_DECODE_REG 0
7027`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_ALIASED_FROM 0
7028`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_ZERO_TIME_OMNI 0
7029`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_JTAG_RD 1
7030`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_JTAG_WR 1
7031`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_SBUS_RD 1
7032`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_SBUS_WR 1
7033`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_RAP_RD 1
7034`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_HW_ACC_RAP_WR 1
7035`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_NUM_FIELDS 2
7036`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_FID 0
7037`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_SLC 31:20
7038`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_WIDTH 12
7039`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_INT_SLC 11:0
7040`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_POSITION 20
7041`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_FMASK 64'b0000000000000000000000000000000011111111111100000000000000000000
7042`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7043`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_POR_VALUE 12'b000000000000
7044`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_UNUSED_CNTL_FIELD_NAME "unused_cntl"
7045`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_FID 1
7046`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_SLC 19:0
7047`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_WIDTH 20
7048`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_INT_SLC 19:0
7049`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_POSITION 0
7050`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_FMASK 64'b0000000000000000000000000000000000000000000011111111111111111111
7051`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7052`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_POR_VALUE 20'b00011110100001001000
7053`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG4_INIT_TIME_FIELD_NAME "init_time"
7054
7055//-------------------------------------------------------
7056//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT
7057//-------------------------------------------------------
7058
7059`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ADDR 20'b11011100010100000100
7060`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_ADDR 30'b000000011011100010100000100000
7061`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_stat"
7062`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_WIDTH 64
7063`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_DEPTH 1
7064`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_SLC 63:0
7065`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_INT_SLC 63:0
7066`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_POSITION 0
7067`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_stat"
7068`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_LOW_ADDR_WIDTH 0
7069`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_ADDR_RANGE 19:0
7070`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7071`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_READ_ONLY_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7072`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7073`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7074`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7075`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7076`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7077`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7078`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
7079`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7080`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_POR_VALUE 64'b0000000000000000000000000000000011111111111111110000000000000000
7081`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_INTERNAL_REG 0
7082`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_EXTERNAL_DECODE_REG 0
7083`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_ALIASED_FROM 0
7084`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_ZERO_TIME_OMNI 0
7085`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_JTAG_RD 1
7086`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_JTAG_WR 1
7087`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_SBUS_RD 1
7088`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_SBUS_WR 1
7089`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_RAP_RD 1
7090`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_HW_ACC_RAP_WR 1
7091`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_NUM_FIELDS 2
7092`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_FID 0
7093`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_SLC 31:16
7094`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_WIDTH 16
7095`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_INT_SLC 15:0
7096`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_POSITION 16
7097`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
7098`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_HW_LD_MASK 64'b0000000000000000000000000000000011111111111111110000000000000000
7099`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_POR_VALUE 16'b1111111111111111
7100`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_RCV_ELECT_IDLE_FIELD_NAME "rcv_elect_idle"
7101`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_FID 1
7102`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_SLC 15:0
7103`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_WIDTH 16
7104`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_INT_SLC 15:0
7105`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_POSITION 0
7106`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
7107`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
7108`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_POR_VALUE 16'b0000000000000000
7109`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_STAT_BIT_SYNC_DN_FIELD_NAME "bit_sync_dn"
7110
7111//-------------------------------------------------------
7112//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT
7113//-------------------------------------------------------
7114
7115`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ADDR 20'b11011100010100000101
7116`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_ADDR 30'b000000011011100010100000101000
7117`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_int"
7118`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_WIDTH 64
7119`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_DEPTH 1
7120`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_SLC 63:0
7121`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_SLC 63:0
7122`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_POSITION 0
7123`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_int"
7124`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_LOW_ADDR_WIDTH 0
7125`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_ADDR_RANGE 19:0
7126`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_READ_MASK 64'b0000000000000000000000000000000010000000111111111111111111111111
7127`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_READ_ONLY_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
7128`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7129`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7130`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7131`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_CLEAR_MASK 64'b0000000000000000000000000000000000000000111111111111111111111111
7132`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7133`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_RMASK 64'b0000000000000000000000000000000010000000111111111111111111111111
7134`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111000000000000000000000000
7135`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_LD_MASK 64'b0000000000000000000000000000000010000000111111111111111111111111
7136`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
7137`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INTERNAL_REG 0
7138`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_EXTERNAL_DECODE_REG 0
7139`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_ALIASED_FROM 0
7140`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_ZERO_TIME_OMNI 0
7141`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_JTAG_RD 1
7142`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_JTAG_WR 1
7143`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_SBUS_RD 1
7144`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_SBUS_WR 1
7145`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_RAP_RD 1
7146`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_HW_ACC_RAP_WR 1
7147`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_NUM_FIELDS 3
7148`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_FID 0
7149`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_SLC 31:31
7150`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_WIDTH 1
7151`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_INT_SLC 0:0
7152`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_POSITION 31
7153`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
7154`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_HW_LD_MASK 64'b0000000000000000000000000000000010000000000000000000000000000000
7155`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_POR_VALUE 1'b0
7156`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_GLOBL_UNMSK_FIELD_NAME "int_globl_unmsk"
7157`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_FID 1
7158`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_SLC 23:16
7159`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_WIDTH 8
7160`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_INT_SLC 7:0
7161`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_POSITION 16
7162`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_FMASK 64'b0000000000000000000000000000000000000000111111110000000000000000
7163`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_HW_LD_MASK 64'b0000000000000000000000000000000000000000111111110000000000000000
7164`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_POR_VALUE 8'b00000000
7165`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_UNUSED_FIELD_NAME "int_unused"
7166`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_FID 2
7167`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_SLC 15:0
7168`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_WIDTH 16
7169`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_INT_SLC 15:0
7170`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_POSITION 0
7171`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
7172`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
7173`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_POR_VALUE 16'b0000000000000000
7174`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_INT_INT_BYTE_SYNC_STS_FIELD_NAME "int_byte_sync_sts"
7175
7176//-------------------------------------------------------
7177//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST
7178//-------------------------------------------------------
7179
7180`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ADDR 20'b11011100010100000110
7181`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_ADDR 30'b000000011011100010100000110000
7182`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_tst"
7183`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_WIDTH 64
7184`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_DEPTH 1
7185`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_SLC 63:0
7186`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_INT_SLC 63:0
7187`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_POSITION 0
7188`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_tst"
7189`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_LOW_ADDR_WIDTH 0
7190`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_ADDR_RANGE 19:0
7191`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_READ_MASK 64'b0000000000000000000000000000000000000000111111111111111111111111
7192`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7193`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7194`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7195`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_SET_MASK 64'b0000000000000000000000000000000000000000111111111111111111111111
7196`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7197`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7198`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_RMASK 64'b0000000000000000000000000000000000000000111111111111111111111111
7199`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111000000000000000000000000
7200`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_LD_MASK 64'b0000000000000000000000000000000000000000111111111111111111111111
7201`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
7202`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_INTERNAL_REG 0
7203`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_EXTERNAL_DECODE_REG 0
7204`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_ALIASED_FROM 0
7205`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_ZERO_TIME_OMNI 0
7206`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_JTAG_RD 1
7207`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_JTAG_WR 1
7208`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_SBUS_RD 1
7209`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_SBUS_WR 1
7210`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_RAP_RD 1
7211`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_HW_ACC_RAP_WR 1
7212`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_NUM_FIELDS 2
7213`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_FID 0
7214`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_SLC 23:16
7215`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_WIDTH 8
7216`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_INT_SLC 7:0
7217`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_POSITION 16
7218`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_FMASK 64'b0000000000000000000000000000000000000000111111110000000000000000
7219`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000111111110000000000000000
7220`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_POR_VALUE 8'b00000000
7221`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_W1S_INT_FIELD_NAME "tst_w1s_int"
7222`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_FID 1
7223`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_SLC 15:0
7224`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_WIDTH 16
7225`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_INT_SLC 15:0
7226`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_POSITION 0
7227`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
7228`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
7229`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_POR_VALUE 16'b0000000000000000
7230`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_TST_TST_BSSS_INT_FIELD_NAME "tst_bsss_int"
7231
7232//-------------------------------------------------------
7233//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK
7234//-------------------------------------------------------
7235
7236`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ADDR 20'b11011100010100000111
7237`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_ADDR 30'b000000011011100010100000111000
7238`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_msk"
7239`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_WIDTH 64
7240`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_DEPTH 1
7241`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_SLC 63:0
7242`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_INT_SLC 63:0
7243`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_POSITION 0
7244`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_msk"
7245`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_LOW_ADDR_WIDTH 0
7246`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_ADDR_RANGE 19:0
7247`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_READ_MASK 64'b0000000000000000000000000000000010000000111111111111111111111111
7248`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7249`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_WRITE_MASK 64'b0000000000000000000000000000000010000000111111111111111111111111
7250`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7251`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7252`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7253`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7254`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_RMASK 64'b0000000000000000000000000000000010000000111111111111111111111111
7255`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_RESERVED_BIT_MASK 64'b1111111111111111111111111111111101111111000000000000000000000000
7256`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7257`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_POR_VALUE 64'b0000000000000000000000000000000010000000111111111111111111111111
7258`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_INTERNAL_REG 0
7259`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_EXTERNAL_DECODE_REG 0
7260`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_ALIASED_FROM 0
7261`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_ZERO_TIME_OMNI 0
7262`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_JTAG_RD 1
7263`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_JTAG_WR 1
7264`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_SBUS_RD 1
7265`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_SBUS_WR 1
7266`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_RAP_RD 1
7267`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_HW_ACC_RAP_WR 1
7268`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_NUM_FIELDS 2
7269`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_FID 0
7270`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_SLC 31:31
7271`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_WIDTH 1
7272`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_INT_SLC 0:0
7273`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_POSITION 31
7274`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
7275`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7276`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_POR_VALUE 1'b1
7277`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_GLOBL_INT_FIELD_NAME "msk_globl_int"
7278`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_FID 1
7279`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_SLC 23:0
7280`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_WIDTH 24
7281`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_INT_SLC 23:0
7282`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_POSITION 0
7283`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_FMASK 64'b0000000000000000000000000000000000000000111111111111111111111111
7284`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7285`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_POR_VALUE 24'b111111111111111111111111
7286`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_MSK_MSK_INT_FIELD_NAME "msk_int"
7287
7288//-------------------------------------------------------
7289//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1
7290//-------------------------------------------------------
7291
7292`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ADDR 20'b11011100010100001000
7293`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_ADDR 30'b000000011011100010100001000000
7294`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_pdwn1"
7295`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_WIDTH 64
7296`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_DEPTH 1
7297`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_SLC 63:0
7298`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_INT_SLC 63:0
7299`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_POSITION 0
7300`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_pdwn1"
7301`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_LOW_ADDR_WIDTH 0
7302`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_ADDR_RANGE 19:0
7303`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7304`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7305`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7306`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7307`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7308`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7309`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7310`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7311`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
7312`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7313`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
7314`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_INTERNAL_REG 0
7315`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_EXTERNAL_DECODE_REG 0
7316`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_ALIASED_FROM 0
7317`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_ZERO_TIME_OMNI 0
7318`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_JTAG_RD 1
7319`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_JTAG_WR 1
7320`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_SBUS_RD 1
7321`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_SBUS_WR 1
7322`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_RAP_RD 1
7323`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_HW_ACC_RAP_WR 1
7324`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_NUM_FIELDS 2
7325`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_FID 0
7326`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_SLC 31:16
7327`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_WIDTH 16
7328`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_INT_SLC 15:0
7329`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_POSITION 16
7330`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_FMASK 64'b0000000000000000000000000000000011111111111111110000000000000000
7331`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7332`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_POR_VALUE 16'b0000000000000000
7333`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_TX_PWR_DN_FIELD_NAME "tx_pwr_dn"
7334`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_FID 1
7335`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_SLC 15:0
7336`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_WIDTH 16
7337`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_INT_SLC 15:0
7338`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_POSITION 0
7339`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
7340`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7341`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_POR_VALUE 16'b0000000000000000
7342`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN1_RX_PWR_DN_FIELD_NAME "rx_pwr_dn"
7343
7344//-------------------------------------------------------
7345//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2
7346//-------------------------------------------------------
7347
7348`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ADDR 20'b11011100010100001001
7349`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_ADDR 30'b000000011011100010100001001000
7350`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_pdwn2"
7351`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_WIDTH 64
7352`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_DEPTH 1
7353`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_SLC 63:0
7354`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_INT_SLC 63:0
7355`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_POSITION 0
7356`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_pdwn2"
7357`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_LOW_ADDR_WIDTH 0
7358`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_ADDR_RANGE 19:0
7359`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7360`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7361`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7362`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7363`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7364`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7365`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7366`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7367`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
7368`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7369`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
7370`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_INTERNAL_REG 0
7371`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_EXTERNAL_DECODE_REG 0
7372`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_ALIASED_FROM 0
7373`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_ZERO_TIME_OMNI 0
7374`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_JTAG_RD 1
7375`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_JTAG_WR 1
7376`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_SBUS_RD 1
7377`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_SBUS_WR 1
7378`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_RAP_RD 1
7379`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_HW_ACC_RAP_WR 1
7380`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_NUM_FIELDS 5
7381`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_FID 0
7382`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_SLC 31:22
7383`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_WIDTH 10
7384`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_INT_SLC 9:0
7385`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_POSITION 22
7386`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_FMASK 64'b0000000000000000000000000000000011111111110000000000000000000000
7387`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7388`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_POR_VALUE 10'b0000000000
7389`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_UNUSED_CNTL_FIELD_NAME "unused_cntl"
7390`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_FID 1
7391`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_SLC 21:21
7392`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_WIDTH 1
7393`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_INT_SLC 0:0
7394`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_POSITION 21
7395`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_FMASK 64'b0000000000000000000000000000000000000000001000000000000000000000
7396`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7397`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_POR_VALUE 1'b0
7398`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_CLK_BUF_FIELD_NAME "pwr_dn_clk_buf"
7399`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_FID 2
7400`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_SLC 20:20
7401`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_WIDTH 1
7402`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_INT_SLC 0:0
7403`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_POSITION 20
7404`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_FMASK 64'b0000000000000000000000000000000000000000000100000000000000000000
7405`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7406`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_POR_VALUE 1'b0
7407`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_PWR_DN_RES_TRIM_FIELD_NAME "pwr_dn_res_trim"
7408`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_FID 3
7409`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_SLC 19:16
7410`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_WIDTH 4
7411`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_INT_SLC 3:0
7412`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_POSITION 16
7413`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_FMASK 64'b0000000000000000000000000000000000000000000011110000000000000000
7414`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7415`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_POR_VALUE 4'b0000
7416`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_TX_PLL_PWR_D_FIELD_NAME "tx_pll_pwr_d"
7417`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_FID 4
7418`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_SLC 15:0
7419`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_WIDTH 16
7420`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_INT_SLC 15:0
7421`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_POSITION 0
7422`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
7423`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7424`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_POR_VALUE 16'b0000000000000000
7425`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_PDWN2_RXLOS_PWR_DN_FIELD_NAME "rxlos_pwr_dn"
7426
7427//-------------------------------------------------------
7428//----- Variable definitions for register FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5
7429//-------------------------------------------------------
7430
7431`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ADDR 20'b11011100010100001010
7432`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_ADDR 30'b000000011011100010100001010000
7433`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config5"
7434`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_WIDTH 64
7435`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_DEPTH 1
7436`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_SLC 63:0
7437`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_INT_SLC 63:0
7438`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_POSITION 0
7439`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_FIELD_NAME "fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_gb_gl_config5"
7440`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_LOW_ADDR_WIDTH 0
7441`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_ADDR_RANGE 19:0
7442`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_READ_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7443`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7444`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_WRITE_MASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7445`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7446`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7447`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7448`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7449`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_RMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7450`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000000000000000000000000000
7451`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7452`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
7453`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_INTERNAL_REG 0
7454`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_EXTERNAL_DECODE_REG 0
7455`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_ALIASED_FROM 0
7456`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_ZERO_TIME_OMNI 0
7457`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_JTAG_RD 1
7458`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_JTAG_WR 1
7459`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_SBUS_RD 1
7460`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_SBUS_WR 1
7461`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_RAP_RD 1
7462`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_HW_ACC_RAP_WR 1
7463`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_NUM_FIELDS 1
7464`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_FID 0
7465`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_SLC 31:0
7466`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_WIDTH 32
7467`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_INT_SLC 31:0
7468`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_POSITION 0
7469`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_FMASK 64'b0000000000000000000000000000000011111111111111111111111111111111
7470`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
7471`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_POR_VALUE 32'b00000000000000000000000000000000
7472`define FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_GB_GL_CONFIG5_UNUSED_CNTL_FIELD_NAME "unused_cntl"
7473
7474
7475#endif
7476
Full OpenSPARC design & verification tarball including full HDL.