Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / niu / rxc_sat / vera / include / dmc_zcp_drv_ports.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmc_zcp_drv_ports.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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#include "rxc_defines.vri"
//#dfine ZCP_PATH RXC_DUV_PATH.rxc_top 
#define	RXC_CK_IN_TIMING PSAMPLE #-1
#define RXC_CK_OUT_TIMING PHOLD #0
#define RXC_CK_CLK_TIMING  CLOCK

#ifdef NIU_GATE

interface dmc_zcp_port0_if{
  input [129:0] zcp_dmc_pkt_data	RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat0";
  input		zcp_dmc_ful_pkt		RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ful_pkt0";
  input		zcp_dmc_empty		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp0";
  input		zcp_dmc_err		RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat_err0";
  input		zcp_dmc_ack		RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ack0";

  output	dmc_zcp_req		RXC_CK_OUT_TIMING verilog_node TOP.cpu.rtx.dmc_zcp_req0";

  input		clk			RXC_CK_CLK_TIMING verilog_node TOP.cpu.rtx.iol2clk";
}

#else

interface dmc_zcp_port0_if{
  input	[129:0]	zcp_dmc_pkt_data	RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat0";
  input		zcp_dmc_ful_pkt		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ful_pkt0";
  input		zcp_dmc_empty		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp0";
  input		zcp_dmc_err		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat_err0";
  input		zcp_dmc_ack		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ack0";

  output	dmc_zcp_req		RXC_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_zcp_req0";

  input	 	clk		        RXC_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk";
}
#endif

#ifdef NIU_GATE
interface dmc_zcp_port1_if{
  input [129:0] zcp_dmc_pkt_data	RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat1";
  input		zcp_dmc_ful_pkt		RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ful_pkt1";
  input		zcp_dmc_empty		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp1";
  input		zcp_dmc_err		RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat_err1";
  input		zcp_dmc_ack		RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ack1";

  output	dmc_zcp_req		RXC_CK_OUT_TIMING verilog_node TOP.cpu.rtx.dmc_zcp_req1";

  input		clk			RXC_CK_CLK_TIMING verilog_node TOP.cpu.rtx.iol2clk";
}
#else
interface dmc_zcp_port1_if{
  input	[129:0]	zcp_dmc_pkt_data	RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat1";
  input		zcp_dmc_ful_pkt		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ful_pkt1";
  input		zcp_dmc_empty		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp1";
  input		zcp_dmc_err		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat_err1";
  input		zcp_dmc_ack		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ack1";

  output	dmc_zcp_req		RXC_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_zcp_req1";

  input	 	clk		        RXC_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk";
}
#endif

port dmc_zcp_drv_port{
  zcp_dmc_pkt_data;
  zcp_dmc_ful_pkt;
  zcp_dmc_empty;
  zcp_dmc_err;
  zcp_dmc_ack;
  dmc_zcp_req;
  clk;
}

bind dmc_zcp_drv_port dmc_zcp_drv0{
	zcp_dmc_pkt_data	dmc_zcp_port0_if.zcp_dmc_pkt_data;
	zcp_dmc_ful_pkt		dmc_zcp_port0_if.zcp_dmc_ful_pkt;
	zcp_dmc_empty		dmc_zcp_port0_if.zcp_dmc_empty;
	zcp_dmc_err		dmc_zcp_port0_if.zcp_dmc_err;
	zcp_dmc_ack		dmc_zcp_port0_if.zcp_dmc_ack;
	dmc_zcp_req		dmc_zcp_port0_if.dmc_zcp_req;
  	clk		        dmc_zcp_port0_if.clk;
}

bind dmc_zcp_drv_port dmc_zcp_drv1{
	zcp_dmc_pkt_data	dmc_zcp_port1_if.zcp_dmc_pkt_data;
	zcp_dmc_ful_pkt		dmc_zcp_port1_if.zcp_dmc_ful_pkt;
	zcp_dmc_empty		dmc_zcp_port1_if.zcp_dmc_empty;
	zcp_dmc_err		dmc_zcp_port1_if.zcp_dmc_err;
	zcp_dmc_ack		dmc_zcp_port1_if.zcp_dmc_ack;
	dmc_zcp_req		dmc_zcp_port1_if.dmc_zcp_req;
  	clk		        dmc_zcp_port1_if.clk;
}