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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: control_fifo_mon.vri | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef __CONTROL_FIFO_MON_VRI__ | |
36 | #define __CONTROL_FIFO_MON_VRI__ | |
37 | ||
38 | #include "neptune_defines.vri" | |
39 | #define RXC_CK_IN_TIMING PSAMPLE #-1 | |
40 | #define RXC_CK_OUT_TIMING PHOLD #0 | |
41 | #define RXC_CK_CLK_TIMING CLOCK | |
42 | ||
43 | #ifdef MAC_SAT | |
44 | #else | |
45 | #ifdef NIU_GATE | |
46 | interface dmc_zcp_port0_if{ | |
47 | input [129:0] control_fifo_data RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat0"; | |
48 | input control_fifo_ful_pkt RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ful_pkt0"; | |
49 | //input control_fifo_empty RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp0"; | |
50 | input control_fifo_err RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat_err0"; | |
51 | input control_fifo_ack RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ack0"; | |
52 | ||
53 | output control_fifo_req RXC_CK_OUT_TIMING verilog_node TOP.cpu.rtx.dmc_zcp_req0"; | |
54 | ||
55 | input clk RXC_CK_CLK_TIMING verilog_node TOP.cpu.rtx.iol2clk"; | |
56 | } | |
57 | ||
58 | interface dmc_zcp_port1_if{ | |
59 | input [129:0] control_fifo_data RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat1"; | |
60 | input control_fifo_ful_pkt RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ful_pkt1"; | |
61 | //input control_fifo_empty RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp1"; | |
62 | input control_fifo_err RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_dat_err1"; | |
63 | input control_fifo_ack RXC_CK_IN_TIMING verilog_node TOP.cpu.rtx.zcp_dmc_ack1"; | |
64 | ||
65 | output control_fifo_req RXC_CK_OUT_TIMING verilog_node TOP.cpu.rtx.dmc_zcp_req1"; | |
66 | ||
67 | input clk RXC_CK_CLK_TIMING verilog_node TOP.cpu.rtx.iol2clk"; | |
68 | } | |
69 | #else | |
70 | interface dmc_zcp_port0_if{ | |
71 | input [129:0] control_fifo_data RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat0"; | |
72 | input control_fifo_ful_pkt RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ful_pkt0"; | |
73 | //input control_fifo_empty RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp0"; | |
74 | input control_fifo_err RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat_err0"; | |
75 | input control_fifo_ack RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ack0"; | |
76 | ||
77 | output control_fifo_req RXC_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_zcp_req0"; | |
78 | ||
79 | input clk RXC_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk"; | |
80 | } | |
81 | ||
82 | interface dmc_zcp_port1_if{ | |
83 | input [129:0] control_fifo_data RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat1"; | |
84 | input control_fifo_ful_pkt RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ful_pkt1"; | |
85 | //input control_fifo_empty RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_emp1"; | |
86 | input control_fifo_err RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_dat_err1"; | |
87 | input control_fifo_ack RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.zcp_dmc_ack1"; | |
88 | ||
89 | output control_fifo_req RXC_CK_OUT_TIMING verilog_node RXC_DUV_PATH.dmc_zcp_req1"; | |
90 | ||
91 | input clk RXC_CK_CLK_TIMING verilog_node RXC_DUV_PATH.niu_clk"; | |
92 | } | |
93 | #endif | |
94 | ||
95 | #endif | |
96 | ||
97 | #ifdef MAC_SAT | |
98 | #else | |
99 | port dmc_zcp_drv_port{ | |
100 | control_fifo_data; | |
101 | control_fifo_ful_pkt; | |
102 | //control_fifo_empty; | |
103 | control_fifo_err; | |
104 | control_fifo_ack; | |
105 | control_fifo_req; | |
106 | clk; | |
107 | } | |
108 | #endif | |
109 | ||
110 | #ifdef MAC_SAT | |
111 | #else | |
112 | bind dmc_zcp_drv_port dmc_zcp_drv0{ | |
113 | control_fifo_data dmc_zcp_port0_if.control_fifo_data; | |
114 | control_fifo_ful_pkt dmc_zcp_port0_if.control_fifo_ful_pkt; | |
115 | //control_fifo_empty dmc_zcp_port0_if.control_fifo_empty; | |
116 | control_fifo_err dmc_zcp_port0_if.control_fifo_err; | |
117 | control_fifo_ack dmc_zcp_port0_if.control_fifo_ack; | |
118 | control_fifo_req dmc_zcp_port0_if.control_fifo_req; | |
119 | clk dmc_zcp_port0_if.clk; | |
120 | } | |
121 | ||
122 | bind dmc_zcp_drv_port dmc_zcp_drv1{ | |
123 | control_fifo_data dmc_zcp_port1_if.control_fifo_data; | |
124 | control_fifo_ful_pkt dmc_zcp_port1_if.control_fifo_ful_pkt; | |
125 | //control_fifo_empty dmc_zcp_port1_if.control_fifo_empty; | |
126 | control_fifo_err dmc_zcp_port1_if.control_fifo_err; | |
127 | control_fifo_ack dmc_zcp_port1_if.control_fifo_ack; | |
128 | control_fifo_req dmc_zcp_port1_if.control_fifo_req; | |
129 | clk dmc_zcp_port1_if.clk; | |
130 | } | |
131 | ||
132 | #endif | |
133 | #endif |