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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / txc_sat / vera / include / tx_port_drr_if.vri
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: tx_port_drr_if.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35
36#ifdef N2_FC
37#define OUTPUT_EDGE PHOLD
38#define INPUT_EDGE PSAMPLE #-1
39#define OUTPUT_SKEW #1
40#endif
41
42#ifdef N2_IOS
43#include "top_defines.vrh"
44#endif
45
46
47#include "neptune_defines.vri"
48
49 #ifndef RXC_SAT
50 #ifndef MAC_SAT
51 #ifdef NIU_GATE
52 #define RTX_PATH tb_top.cpu.rtx
53 #define TXC_PATH NIU_DUV_PATH.rtx
54 #define TXC0_PATH NIU_DUV_PATH.rtx
55 #define TXC1_PATH NIU_DUV_PATH.rtx
56 #else
57 #define TXC_PATH NIU_DUV_PATH.rtx.txc
58 #define TXC0_PATH NIU_DUV_PATH.rtx.txc.niu_txc_debug
59 #define TXC1_PATH NIU_DUV_PATH.rtx.txc.niu_txc_debug
60 #endif
61 #else //else for MAC_SAT
62 #define TXC_PATH NIU_DUV_PATH.rtx.txc
63 #define TXC0_PATH NIU_DUV_PATH.rtx.txc
64 #define TXC1_PATH NIU_DUV_PATH.rtx.txc
65 #endif
66 #else //else for RXC_SAT
67 #define TXC_PATH NIU_DUV_PATH.rtx.txc
68 #define TXC0_PATH NIU_DUV_PATH.rtx.txc
69 #define TXC1_PATH NIU_DUV_PATH.rtx.txc
70 #endif
71
72interface txc_port0_drr_if
73{
74#ifdef NIU_GATE
75 input clk CLOCK verilog_node TXC_PATH.iol2clk";
76#else
77#ifdef NIU_SYSTEMC_T2
78 input clk CLOCK verilog_node NIU_DUV_PATH.rtx_txc_niu_clk";
79#else
80 input clk CLOCK verilog_node TXC_PATH.niu_clk";
81#endif
82#endif
83
84 #ifndef RXC_SAT
85 #ifdef NIU_GATE
86 #ifdef POST_LAYOUT
87 input latch_activedma INPUT_EDGE verilog_node TXC0_PATH.txc_niu_txc_packetengine0_niu_txc_drr_engine_niu_txc_drr_arbiter_n438ASThfnNet23960";
88
89 input [23:0] activeListDMA INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.txc_port0_contextactivelist_15_, tb_top.cpu.rtx.txc_port0_contextactivelist_14_, tb_top.cpu.rtx.txc_port0_contextactivelist_13_, tb_top.cpu.rtx.txc_port0_contextactivelist_12_, tb_top.cpu.rtx.txc_port0_contextactivelist_11_, tb_top.cpu.rtx.txc_port0_contextactivelist_10_, tb_top.cpu.rtx.txc_port0_contextactivelist_9_, tb_top.cpu.rtx.txc_port0_contextactivelist_8_, tb_top.cpu.rtx.txc_port0_contextactivelist_7_, tb_top.cpu.rtx.txc_port0_contextactivelist_6_, tb_top.cpu.rtx.txc_port0_contextactivelist_5_, tb_top.cpu.rtx.txc_port0_contextactivelist_4_, tb_top.cpu.rtx.txc_port0_contextactivelist_3_, tb_top.cpu.rtx.txc_port0_contextactivelist_2_, tb_top.cpu.rtx.txc_port0_contextactivelist_1_, tb_top.cpu.rtx.txc_port0_contextactivelist_0_}";
90
91 #else // if pre-layout gate netlist NOTE: now all lower case in pre-to_1.0
92 // When defining LatchActiveDMA use the clken for the *port0_ContextActiveList* flip flops
93 input latch_activedma INPUT_EDGE verilog_node TXC0_PATH.n105044";
94
95 input [23:0] activeListDMA INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.txc_port0_contextactivelist_15_, tb_top.cpu.rtx.txc_port0_contextactivelist_14_, tb_top.cpu.rtx.txc_port0_contextactivelist_13_, tb_top.cpu.rtx.txc_port0_contextactivelist_12_, tb_top.cpu.rtx.txc_port0_contextactivelist_11_, tb_top.cpu.rtx.txc_port0_contextactivelist_10_, tb_top.cpu.rtx.txc_port0_contextactivelist_9_, tb_top.cpu.rtx.txc_port0_contextactivelist_8_, tb_top.cpu.rtx.txc_port0_contextactivelist_7_, tb_top.cpu.rtx.txc_port0_contextactivelist_6_, tb_top.cpu.rtx.txc_port0_contextactivelist_5_, tb_top.cpu.rtx.txc_port0_contextactivelist_4_, tb_top.cpu.rtx.txc_port0_contextactivelist_3_, tb_top.cpu.rtx.txc_port0_contextactivelist_2_, tb_top.cpu.rtx.txc_port0_contextactivelist_1_, tb_top.cpu.rtx.txc_port0_contextactivelist_0_}";
96 #endif // switch between Pre and Post layout
97
98// The following inputs were defined for RTL nodes which are not in the netlist
99// tying them to 0's for now. SOME TEST WILL FAIL BECAUSE OF THIS HENCE THESE
100// SIGNALS WILL CONTRIBUTE TO A GATE VS. RTL MISMATCH!!!! VJH
101 input add_credit INPUT_EDGE verilog_node "1'b0";
102 input clr_eoflist INPUT_EDGE verilog_node "1'b0";
103 input [23:0] eoflist INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.dmc_txc_dma15_eoflist, tb_top.cpu.rtx.dmc_txc_dma14_eoflist,tb_top.cpu.rtx.dmc_txc_dma13_eoflist,tb_top.cpu.rtx.dmc_txc_dma12_eoflist,tb_top.cpu.rtx.dmc_txc_dma11_eoflist,tb_top.cpu.rtx.dmc_txc_dma10_eoflist,tb_top.cpu.rtx.dmc_txc_dma9_eoflist,tb_top.cpu.rtx.dmc_txc_dma8_eoflist, tb_top.cpu.rtx.dmc_txc_dma7_eoflist, tb_top.cpu.rtx.dmc_txc_dma6_eoflist, tb_top.cpu.rtx.dmc_txc_dma5_eoflist, tb_top.cpu.rtx.dmc_txc_dma4_eoflist, tb_top.cpu.rtx.dmc_txc_dma3_eoflist, tb_top.cpu.rtx.dmc_txc_dma2_eoflist, tb_top.cpu.rtx.dmc_txc_dma1_eoflist, tb_top.cpu.rtx.dmc_txc_dma0_eoflist}";
104
105 #else // if GATEs vs RTL
106 #ifdef NIU_SYSTEMC_T2
107 input latch_activedma INPUT_EDGE verilog_node "1'b0";
108 input [23:0] activeListDMA INPUT_EDGE verilog_node "24'b0";
109 input add_credit INPUT_EDGE verilog_node "1'b0";
110 input clr_eoflist INPUT_EDGE verilog_node "1'b0";
111 #else
112 input latch_activedma INPUT_EDGE verilog_node TXC0_PATH.Port0_LatchActiveDMA";
113 input [23:0] activeListDMA INPUT_EDGE verilog_node TXC0_PATH.Port0_ContextActiveList";
114 input add_credit INPUT_EDGE verilog_node TXC_PATH.niu_txc_packetEngine0.niu_txc_drr_engine.niu_txc_drr_arbiter.AddCreditToContext";
115 input clr_eoflist INPUT_EDGE verilog_node TXC_PATH.niu_txc_packetEngine0.niu_txc_drr_engine.niu_txc_drr_arbiter.ClrDeficitForEofList";
116 #endif
117 #ifdef NIU_SYSTEMC_T2
118 input [23:0] eoflist INPUT_EDGE verilog_node "24'h0";
119 #else
120 input [23:0] eoflist INPUT_EDGE verilog_node "{8'h0,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma15_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma14_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma13_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma12_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma11_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma10_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma9_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma8_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma7_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma6_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma5_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma4_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma3_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma2_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma1_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma0_eoflist}";
121 #endif // NIU_SYSTEMC_T2
122 #endif
123 #endif
124
125}
126
127interface txc_port1_drr_if
128{
129#ifdef NIU_GATE
130 input clk CLOCK verilog_node TXC_PATH.iol2clk";
131#else
132 #ifdef NIU_SYSTEMC_T2
133 input clk CLOCK verilog_node NIU_DUV_PATH.rtx_txc_niu_clk";
134 #else
135 input clk CLOCK verilog_node TXC_PATH.niu_clk";
136 #endif // NIU_SYSTEMC_T2
137#endif
138
139 #ifndef RXC_SAT
140 #ifdef NIU_GATE
141 #ifdef POST_LAYOUT
142 input latch_activedma INPUT_EDGE verilog_node TXC1_PATH.txc_niu_txc_packetengine1_niu_txc_drr_engine_niu_txc_drr_arbiter_n438ASThfnNet23961";
143 input [23:0] activeListDMA INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.txc_port1_contextactivelist_15_, tb_top.cpu.rtx.txc_port1_contextactivelist_14_, tb_top.cpu.rtx.txc_port1_contextactivelist_13_, tb_top.cpu.rtx.txc_port1_contextactivelist_12_, tb_top.cpu.rtx.txc_port1_contextactivelist_11_, tb_top.cpu.rtx.txc_port1_contextactivelist_10_, tb_top.cpu.rtx.txc_port1_contextactivelist_9_, tb_top.cpu.rtx.txc_port1_contextactivelist_8_, tb_top.cpu.rtx.txc_port1_contextactivelist_7_, tb_top.cpu.rtx.txc_port1_contextactivelist_6_, tb_top.cpu.rtx.txc_port1_contextactivelist_5_, tb_top.cpu.rtx.txc_port1_contextactivelist_4_, tb_top.cpu.rtx.txc_port1_contextactivelist_3_, tb_top.cpu.rtx.txc_port1_contextactivelist_2_, tb_top.cpu.rtx.txc_port1_contextactivelist_1_, tb_top.cpu.rtx.txc_port1_contextactivelist_0_}"; // if RTL
144 #else // If pre-layout gates
145 // When defining LatchActiveDMA use the clken for the *port1_ContextActiveList* flip flops
146 input latch_activedma INPUT_EDGE verilog_node TXC1_PATH.n105047";
147 input [23:0] activeListDMA INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.txc_port1_contextactivelist_15_, tb_top.cpu.rtx.txc_port1_contextactivelist_14_, tb_top.cpu.rtx.txc_port1_contextactivelist_13_, tb_top.cpu.rtx.txc_port1_contextactivelist_12_, tb_top.cpu.rtx.txc_port1_contextactivelist_11_, tb_top.cpu.rtx.txc_port1_contextactivelist_10_, tb_top.cpu.rtx.txc_port1_contextactivelist_9_, tb_top.cpu.rtx.txc_port1_contextactivelist_8_, tb_top.cpu.rtx.txc_port1_contextactivelist_7_, tb_top.cpu.rtx.txc_port1_contextactivelist_6_, tb_top.cpu.rtx.txc_port1_contextactivelist_5_, tb_top.cpu.rtx.txc_port1_contextactivelist_4_, tb_top.cpu.rtx.txc_port1_contextactivelist_3_, tb_top.cpu.rtx.txc_port1_contextactivelist_2_, tb_top.cpu.rtx.txc_port1_contextactivelist_1_, tb_top.cpu.rtx.txc_port1_contextactivelist_0_}";
148
149 #endif // Pre vs. Post gates
150
151// The following inputs were defined for RTL nodes which are not in the netlist
152// tying them to 0's for now. SOME TEST WILL FAIL BECAUSE OF THIS HENCE THESE
153// SIGNALS WILL CONTRIBUTE TO A GATE VS. RTL MISMATCH!!!! VJH
154 input add_credit INPUT_EDGE verilog_node "1'b0";
155 input clr_eoflist INPUT_EDGE verilog_node "1'b0";
156 input [23:0] eoflist INPUT_EDGE verilog_node "{8'b0, tb_top.cpu.rtx.dmc_txc_dma15_eoflist, tb_top.cpu.rtx.dmc_txc_dma14_eoflist,tb_top.cpu.rtx.dmc_txc_dma13_eoflist,tb_top.cpu.rtx.dmc_txc_dma12_eoflist,tb_top.cpu.rtx.dmc_txc_dma11_eoflist,tb_top.cpu.rtx.dmc_txc_dma10_eoflist,tb_top.cpu.rtx.dmc_txc_dma9_eoflist,tb_top.cpu.rtx.dmc_txc_dma8_eoflist, tb_top.cpu.rtx.dmc_txc_dma7_eoflist, tb_top.cpu.rtx.dmc_txc_dma6_eoflist, tb_top.cpu.rtx.dmc_txc_dma5_eoflist, tb_top.cpu.rtx.dmc_txc_dma4_eoflist, tb_top.cpu.rtx.dmc_txc_dma3_eoflist, tb_top.cpu.rtx.dmc_txc_dma2_eoflist, tb_top.cpu.rtx.dmc_txc_dma1_eoflist, tb_top.cpu.rtx.dmc_txc_dma0_eoflist}";
157
158 #else // if RTL
159 #ifdef NIU_SYSTEMC_T2
160 input latch_activedma INPUT_EDGE verilog_node "1'b0";
161 input [23:0] activeListDMA INPUT_EDGE verilog_node "24'b0";
162 input add_credit INPUT_EDGE verilog_node "1'b0";
163 input clr_eoflist INPUT_EDGE verilog_node "1'b0";
164 #else
165 input latch_activedma INPUT_EDGE verilog_node TXC1_PATH.Port1_LatchActiveDMA";
166 input [23:0] activeListDMA INPUT_EDGE verilog_node TXC1_PATH.Port1_ContextActiveList";
167 input add_credit INPUT_EDGE verilog_node TXC_PATH.niu_txc_packetEngine1.niu_txc_drr_engine.niu_txc_drr_arbiter.AddCreditToContext";
168 input clr_eoflist INPUT_EDGE verilog_node TXC_PATH.niu_txc_packetEngine1.niu_txc_drr_engine.niu_txc_drr_arbiter.ClrDeficitForEofList";
169 #endif
170 #ifdef NIU_SYSTEMC_T2
171 input [23:0] eoflist INPUT_EDGE verilog_node "24'h0";
172 #else
173 input [23:0] eoflist INPUT_EDGE verilog_node "{8'h0,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma15_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma14_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma13_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma12_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma11_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma10_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma9_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma8_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma7_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma6_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma5_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma4_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma3_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma2_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma1_eoflist,tb_top.cpu.tds.niu_tdmc.dmc_txc_dma0_eoflist}";
174 #endif
175 #endif
176#endif
177
178}
179
180port txc_port_drr{
181
182 clk;
183 #ifndef RXC_SAT
184 latch_activedma;
185 activeListDMA;
186 add_credit;
187 clr_eoflist;
188 eoflist;
189 #endif
190}
191bind txc_port_drr txc_port0_drr_bind {
192 clk txc_port0_drr_if.clk;
193 #ifndef RXC_SAT
194 latch_activedma txc_port0_drr_if.latch_activedma;
195 activeListDMA txc_port0_drr_if.activeListDMA;
196 add_credit txc_port0_drr_if.add_credit;
197 clr_eoflist txc_port0_drr_if.clr_eoflist;
198 eoflist txc_port0_drr_if.eoflist;
199 #endif
200}
201
202
203bind txc_port_drr txc_port1_drr_bind {
204 clk txc_port1_drr_if.clk;
205 #ifndef RXC_SAT
206 latch_activedma txc_port1_drr_if.latch_activedma;
207 activeListDMA txc_port1_drr_if.activeListDMA;
208 add_credit txc_port1_drr_if.add_credit;
209 clr_eoflist txc_port1_drr_if.clr_eoflist;
210 eoflist txc_port1_drr_if.eoflist;
211 #endif
212}
213
Full OpenSPARC design & verification tarball including full HDL.