Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / tcu / vera / include / ccu_defines.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ccu_defines.vri
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// ========== Copyright Header End ============================================
#ifndef INC_CCU_DEFINES_VRI      
#define INC_CCU_DEFINES_VRI

//------CCU CSRs -------
#define CCU__PLL_CTL                    40'h83_0000_0000  // CSR's addr
#define CCU__PLL_CTL__INIT_VALUE        64'h01_0020_11c1  // change=1, D4=8 or 4.0, D3=1, D2=7, D1=1
#define CCU__PLL_CTL__WRITABLE_MASK     64'h0000_001f_ffff_ffff  // 36:0] are writable
#define CCU__PLL_CTL__PLL_DIV1__POS       0
#define CCU__PLL_CTL__PLL_DIV1__SIZE      6
#define CCU__PLL_CTL__PLL_DIV1__MSB       5
#define CCU__PLL_CTL__PLL_DIV2__POS       6
#define CCU__PLL_CTL__PLL_DIV2__SIZE      6
#define CCU__PLL_CTL__PLL_DIV2__MSB       11
#define CCU__PLL_CTL__PLL_DIV3__POS       12
#define CCU__PLL_CTL__PLL_DIV3__SIZE      6
#define CCU__PLL_CTL__PLL_DIV3__MSB       17
#define CCU__PLL_CTL__PLL_DIV4__POS       18
#define CCU__PLL_CTL__PLL_DIV4__SIZE      7
#define CCU__PLL_CTL__PLL_DIV4__MSB       24
#define CCU__PLL_CTL__ST_PHASE_HI__POS    25
#define CCU__PLL_CTL__ST_DELAY_CMP__POS   26
#define CCU__PLL_CTL__ST_DELAY_CMP__SIZE  2
#define CCU__PLL_CTL__ST_DELAY_CMP__MSB   27
#define CCU__PLL_CTL__SERDES_DTM1__POS    28
#define CCU__PLL_CTL__SERDES_DTM2__POS    29
#define CCU__PLL_CTL__ALIGN_SHIFT__POS    30
#define CCU__PLL_CTL__ALIGN_SHIFT__SIZE   2
#define CCU__PLL_CTL__ALIGN_SHIFT__MSB    31
#define CCU__PLL_CTL__CHANGE__POS         32
#define CCU__PLL_CTL__PLL_CHAR_IN__POS    33
#define CCU__PLL_CTL__ST_DELAY_DR__POS    34
#define CCU__PLL_CTL__ST_DELAY_DR__SIZE   2
#define CCU__PLL_CTL__ST_DELAY_DR__MSB    35
#define CCU__PLL_CTL__PLL_CLAMP_FLTR__POS 36


#define CCU__RNG_CTL                         40'h83_0000_0020  // CSR's addr
#define CCU__RNG_CTL__INIT_VALUE             64'h00_7c0f
#define CCU__RNG_CTL__WRITABLE_MASK          64'h0000_0000_01ff_ffff  // [24:0] are writable
#define CCU__RNG_CTL__RNG_CTL1__POS          0
#define CCU__RNG_CTL__RNG_CTL2__POS          1
#define CCU__RNG_CTL__RNG_CTL3__POS          2
#define CCU__RNG_CTL__RNG_CTL4__POS          3
#define CCU__RNG_CTL__RNG_ANLG_SEL__POS      4
#define CCU__RNG_CTL__RNG_ANLG_SEL__SIZE     2
#define CCU__RNG_CTL__RNG_ANLG_SEL__MSB      5
#define CCU__RNG_CTL__RNG_VCOCTRL_SEL__POS   6
#define CCU__RNG_CTL__RNG_VCOCTRL_SEL__SIZE  2
#define CCU__RNG_CTL__RNG_VCOCTRL_SEL__MSB   7
#define CCU__RNG_CTL__RNG_BYPASS__POS        8
#define CCU__RNG_CTL__RNG_WAIT_CNT__POS      9
#define CCU__RNG_CTL__RNG_WAIT_CNT__SIZE     16
#define CCU__RNG_CTL__RNG_WAIT_CNT__MSB      24

#define CCU__RNG_DATA         40'h83_0000_0030  // CSR's addr

//---encoding of tcu_ccu_mux_sel ---
#define CCU__PLL_MUX_SEL__PLL_CLK      2'b00
#define CCU__PLL_MUX_SEL__STRETCH_CLK  2'b01
#define CCU__PLL_MUX_SEL__EXT_CLK      2'b10
#define CCU__PLL_MUX_SEL__BYPASS_CLK   2'b11

#endif