projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / tcu / vera / include / tcu.if.vri
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: tcu.if.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef INC_TCU_IF_VRI
36#define INC_TCU_IF_VRI
37
38#include <tcu_top_defines.vri>
39
40// WHAT: cmp clock (aka l2clk)
41interface tcu_l2clk_if {
42#ifdef TCU_GATE
43 input l2clk CLOCK verilog_node "`TCU.clkgen_tcu_cmp__cclk";
44#else
45 input l2clk CLOCK verilog_node "`TCU.clkgen_tcu_cmp.l2clk";
46#endif
47}
48
49// WHAT: IO clock
50interface tcu_iol2clk_if {
51#ifdef TCU_GATE
52 input l2clk CLOCK verilog_node "`TCU.clkgen_tcu_io__cclk";
53#else
54 input l2clk CLOCK verilog_node "`TCU.clkgen_tcu_io.l2clk";
55#endif
56}
57
58// WHAT: gclk which is input of TCU cluster headers
59interface tcu_gclk_if {
60#ifdef TCU_GATE
61 input gclk CLOCK verilog_node "`TCU.gclk";
62#else
63 input gclk CLOCK verilog_node "`TCU.clkgen_tcu_cmp.gclk";
64#endif
65}
66
67//
68// WHAT: interface for DMO signals
69//
70
71interface tcu_mbist_dmo_if {
72 input l2clk CLOCK verilog_node "`TCU.l2clk";
73 //--- these signals are TCU output ports ---
74 input [5:0] dmo_coresel PSAMPLE #-1 verilog_node "`TCU.dmo_coresel";
75 input [5:0] dmo_l2tsel PSAMPLE #-1 verilog_node "`TCU.dmo_l2tsel";
76 input [2:0] tcu_rtx_dmo_ctl PSAMPLE #-1 verilog_node "`TCU.tcu_rtx_dmo_ctl";
77 input dmo_dcmuxctl PSAMPLE #-1 verilog_node "`TCU.dmo_dcmuxctl";
78 input dmo_icmuxctl PSAMPLE #-1 verilog_node "`TCU.dmo_icmuxctl";
79 input dmo_tagmuxctl PSAMPLE #-1 verilog_node "`TCU.dmo_tagmuxctl";
80}
81
82//
83// WHAT: important TCU-RST interface signals and reset-related signals
84// NOTE: some signals are defined in rst.if.vri, but rst.if.vri is not included in fc_top.vr.
85//
86interface tcu_rst_if {
87 input l2clk CLOCK verilog_node "`TCU.l2clk";
88
89 input PWRON_RST_L INPUT_EDGE INPUT_SKEW verilog_node "`CPU.PWRON_RST_L";
90 input tcu_por_reset INPUT_EDGE INPUT_SKEW verilog_node "`TCU.POR_"; // output of RST block
91 input rst_tcu_asicflush_stop_req INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rst_tcu_asicflush_stop_req";
92 input tcu_rst_asicflush_stop_ack INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rst_asicflush_stop_ack";
93 input rst_tcu_flush_init_req INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rst_tcu_flush_init_req";
94 input tcu_rst_flush_init_ack INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rst_flush_init_ack";
95 input rst_tcu_flush_stop_req INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rst_tcu_flush_stop_req";
96 input tcu_rst_flush_stop_ack INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rst_flush_stop_ack";
97 input tcu_efu_read_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_read_start";
98 input tcu_rst_efu_done INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rst_efu_done";
99 input rst_ncu_unpark_thread INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_ncu_unpark_thread"; // warn: IO clk domain
100}
101
102//
103// WHAT: core/bank available/enable signals that are NCU outputs and TCU inputs
104//
105interface tcu_corebank_if {
106 input l2clk CLOCK verilog_node "`TCU.l2clk";
107 input [7:0] core_available INPUT_EDGE INPUT_SKEW verilog_node "{`TCU.ncu_spc7_core_available,`TCU.ncu_spc6_core_available,`TCU.ncu_spc5_core_available,`TCU.ncu_spc4_core_available,`TCU.ncu_spc3_core_available,`TCU.ncu_spc2_core_available,`TCU.ncu_spc1_core_available,`TCU.ncu_spc0_core_available}";
108 input [7:0] core_enable INPUT_EDGE INPUT_SKEW verilog_node "{`TCU.ncu_spc7_core_enable_status,`TCU.ncu_spc6_core_enable_status,`TCU.ncu_spc5_core_enable_status,`TCU.ncu_spc4_core_enable_status,`TCU.ncu_spc3_core_enable_status,`TCU.ncu_spc2_core_enable_status,`TCU.ncu_spc1_core_enable_status,`TCU.ncu_spc0_core_enable_status}";
109 input [7:0] bank_available INPUT_EDGE INPUT_SKEW verilog_node "`TCU.ncu_tcu_bank_avail";
110 input [7:0] bank_enable INPUT_EDGE INPUT_SKEW verilog_node "{`TCU.ncu_spc_ba67, `TCU.ncu_spc_ba67, `TCU.ncu_spc_ba45, `TCU.ncu_spc_ba45, `TCU.ncu_spc_ba23, `TCU.ncu_spc_ba23, `TCU.ncu_spc_ba01, `TCU.ncu_spc_ba01}";
111}
112
113interface bscan {
114 input TCK CLOCK verilog_node "`CPU.TCK" ;
115 input bs_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mio_bs_scan_en" ;
116 input bs_clk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mio_bs_clk" ;
117 input bs_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mio_bs_aclk" ;
118 input bs_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mio_bs_bclk" ;
119 input bs_uclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mio_bs_uclk" ;
120}
121
122interface mbist {
123 input TCK CLOCK verilog_node "`TCU.gclk";
124 input mbist_user INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mbist_user_mode";
125 input tcu_rdp_rdmc_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rdp_rdmc_mbist_start";
126 input tcu_rtx_rxc_ipp0_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rtx_rxc_ipp0_mbist_start";
127 input tcu_rtx_rxc_ipp1_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rtx_rxc_ipp1_mbist_start";
128 input tcu_rtx_rxc_mb5_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rtx_rxc_mb5_mbist_start";
129 input tcu_rtx_rxc_mb6_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rtx_rxc_mb6_mbist_start";
130 input tcu_rtx_rxc_zcp0_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rtx_rxc_zcp0_mbist_start";
131 input tcu_rtx_rxc_zcp1_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rtx_rxc_zcp1_mbist_start";
132 input tcu_rtx_txc_txe0_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rtx_txc_txe0_mbist_start";
133 input tcu_rtx_txc_txe1_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rtx_txc_txe1_mbist_start";
134 input tcu_tds_smx_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_tds_smx_mbist_start";
135 input tcu_tds_tdmc_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_tds_tdmc_mbist_start";
136 input tcu_peu_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_peu_mbist_start";
137 input [1:0] tcu_dmu_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_dmu_mbist_start";
138 input tcu_l2t7_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t7_mbist_start";
139 input tcu_l2t6_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t6_mbist_start";
140 input tcu_l2t5_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t5_mbist_start";
141 input tcu_l2t4_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t4_mbist_start";
142 input tcu_l2t3_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t3_mbist_start";
143 input tcu_l2t2_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t2_mbist_start";
144 input tcu_l2t1_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t1_mbist_start";
145 input tcu_l2t0_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t0_mbist_start";
146 input tcu_l2b7_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b7_mbist_start";
147 input tcu_l2b6_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b6_mbist_start";
148 input tcu_l2b5_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b5_mbist_start";
149 input tcu_l2b4_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b4_mbist_start";
150 input tcu_l2b3_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b3_mbist_start";
151 input tcu_l2b2_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b2_mbist_start";
152 input tcu_l2b1_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b1_mbist_start";
153 input tcu_l2b0_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b0_mbist_start";
154 input tcu_mcu3_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu3_mbist_start";
155 input tcu_mcu2_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu2_mbist_start";
156 input tcu_mcu1_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu1_mbist_start";
157 input tcu_mcu0_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu0_mbist_start";
158 input [1:0] tcu_ncu_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ncu_mbist_start";
159 input [1:0] tcu_sio_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sio_mbist_start";
160 input [1:0] tcu_sii_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sii_mbist_start";
161 input [7:0] tcu_spc_mbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_mbist_start";
162 inout rdp_rdmc_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rdp_rdmc_tcu_mbist_done";
163 inout rtx_rxc_ipp0_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rtx_rxc_ipp0_tcu_mbist_done";
164 inout rtx_rxc_ipp1_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rtx_rxc_ipp1_tcu_mbist_done";
165 inout rtx_rxc_mb5_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rtx_rxc_mb5_tcu_mbist_done";
166 inout rtx_rxc_mb6_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rtx_rxc_mb6_tcu_mbist_done";
167 inout rtx_rxc_zcp0_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rtx_rxc_zcp0_tcu_mbist_done";
168 inout rtx_rxc_zcp1_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rtx_rxc_zcp1_tcu_mbist_done";
169 inout rtx_txc_txe0_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rtx_txc_txe0_tcu_mbist_done";
170 inout rtx_txc_txe1_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rtx_txc_txe1_tcu_mbist_done";
171 inout tds_smx_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tds_smx_tcu_mbist_done";
172 inout tds_tdmc_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tds_tdmc_tcu_mbist_done";
173 inout peu_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.peu_tcu_mbist_done";
174 inout [1:0] dmu_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.dmu_tcu_mbist_done";
175 inout l2t7_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2t7_tcu_mbist_done";
176 inout l2t6_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2t6_tcu_mbist_done";
177 inout l2t5_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2t5_tcu_mbist_done";
178 inout l2t4_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2t4_tcu_mbist_done";
179 inout l2t3_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2t3_tcu_mbist_done";
180 inout l2t2_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2t2_tcu_mbist_done";
181 inout l2t1_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2t1_tcu_mbist_done";
182 inout l2t0_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2t0_tcu_mbist_done";
183 inout l2b7_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2b7_tcu_mbist_done";
184 inout l2b6_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2b6_tcu_mbist_done";
185 inout l2b5_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2b5_tcu_mbist_done";
186 inout l2b4_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2b4_tcu_mbist_done";
187 inout l2b3_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2b3_tcu_mbist_done";
188 inout l2b2_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2b2_tcu_mbist_done";
189 inout l2b1_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2b1_tcu_mbist_done";
190 inout l2b0_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.l2b0_tcu_mbist_done";
191 inout mcu3_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mcu3_tcu_mbist_done";
192 inout mcu2_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mcu2_tcu_mbist_done";
193 inout mcu1_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mcu1_tcu_mbist_done";
194 inout mcu0_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mcu0_tcu_mbist_done";
195 inout [1:0] ncu_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.ncu_tcu_mbist_done";
196 inout [1:0] sio_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sio_tcu_mbist_done";
197 inout [1:0] sii_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sii_tcu_mbist_done";
198 inout spc7_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc7_tcu_mbist_done";
199 inout spc6_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc6_tcu_mbist_done";
200 inout spc5_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc5_tcu_mbist_done";
201 inout spc4_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc4_tcu_mbist_done";
202 inout spc3_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc3_tcu_mbist_done";
203 inout spc2_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc2_tcu_mbist_done";
204 inout spc1_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc1_tcu_mbist_done";
205 inout spc0_tcu_mbist_done OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc0_tcu_mbist_done";
206 output rdp_rdmc_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.rdp_rdmc_tcu_mbist_fail";
207 output rtx_rxc_ipp0_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.rtx_rxc_ipp0_tcu_mbist_fail";
208 output rtx_rxc_ipp1_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.rtx_rxc_ipp1_tcu_mbist_fail";
209 output rtx_rxc_mb5_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.rtx_rxc_mb5_tcu_mbist_fail";
210 output rtx_rxc_mb6_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.rtx_rxc_mb6_tcu_mbist_fail";
211 output rtx_rxc_zcp0_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.rtx_rxc_zcp0_tcu_mbist_fail";
212 output rtx_rxc_zcp1_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.rtx_rxc_zcp1_tcu_mbist_fail";
213 output rtx_txc_txe0_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.rtx_txc_txe0_tcu_mbist_fail";
214 output rtx_txc_txe1_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.rtx_txc_txe1_tcu_mbist_fail";
215 output tds_smx_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.tds_smx_tcu_mbist_fail";
216 output tds_tdmc_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.tds_tdmc_tcu_mbist_fail";
217 output peu_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.peu_tcu_mbist_fail";
218 output [1:0] dmu_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.dmu_tcu_mbist_fail";
219 output l2t7_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2t7_tcu_mbist_fail";
220 output l2t6_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2t6_tcu_mbist_fail";
221 output l2t5_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2t5_tcu_mbist_fail";
222 output l2t4_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2t4_tcu_mbist_fail";
223 output l2t3_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2t3_tcu_mbist_fail";
224 output l2t2_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2t2_tcu_mbist_fail";
225 output l2t1_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2t1_tcu_mbist_fail";
226 output l2t0_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2t0_tcu_mbist_fail";
227 output l2b7_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2b7_tcu_mbist_fail";
228 output l2b6_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2b6_tcu_mbist_fail";
229 output l2b5_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2b5_tcu_mbist_fail";
230 output l2b4_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2b4_tcu_mbist_fail";
231 output l2b3_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2b3_tcu_mbist_fail";
232 output l2b2_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2b2_tcu_mbist_fail";
233 output l2b1_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2b1_tcu_mbist_fail";
234 output l2b0_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.l2b0_tcu_mbist_fail";
235 output mcu3_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.mcu3_tcu_mbist_fail";
236 output mcu2_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.mcu2_tcu_mbist_fail";
237 output mcu1_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.mcu1_tcu_mbist_fail";
238 output mcu0_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.mcu0_tcu_mbist_fail";
239 output [1:0] ncu_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.ncu_tcu_mbist_fail";
240 output [1:0] sio_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.sio_tcu_mbist_fail";
241 output [1:0] sii_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.sii_tcu_mbist_fail";
242 output spc7_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.spc7_tcu_mbist_fail";
243 output spc6_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.spc6_tcu_mbist_fail";
244 output spc5_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.spc5_tcu_mbist_fail";
245 output spc4_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.spc4_tcu_mbist_fail";
246 output spc3_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.spc3_tcu_mbist_fail";
247 output spc2_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.spc2_tcu_mbist_fail";
248 output spc1_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.spc1_tcu_mbist_fail";
249 output spc0_tcu_mbist_fail OUTPUT_EDGE_N verilog_node "`TCU.spc0_tcu_mbist_fail";
250 input tcu_spc0_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_scan_en";
251 input tcu_spc1_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_scan_en";
252 input tcu_spc2_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_scan_en";
253 input tcu_spc3_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_scan_en";
254 input tcu_spc4_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_scan_en";
255 input tcu_spc5_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_scan_en";
256 input tcu_spc6_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_scan_en";
257 input tcu_spc7_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_scan_en";
258 input tap_spc0_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc0_mb_scan_en";
259 input tap_spc1_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc1_mb_scan_en";
260 input tap_spc2_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc2_mb_scan_en";
261 input tap_spc3_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc3_mb_scan_en";
262 input tap_spc4_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc4_mb_scan_en";
263 input tap_spc5_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc5_mb_scan_en";
264 input tap_spc6_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc6_mb_scan_en";
265 input tap_spc7_mb_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc7_mb_scan_en";
266 input tcu_mbist_bisi_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mbist_bisi_en";
267 input tcu_spc0_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_aclk";
268 input tcu_spc1_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_aclk";
269 input tcu_spc2_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_aclk";
270 input tcu_spc3_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_aclk";
271 input tcu_spc4_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_aclk";
272 input tcu_spc5_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_aclk";
273 input tcu_spc6_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_aclk";
274 input tcu_spc7_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_aclk";
275 input tcu_spc0_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_bclk";
276 input tcu_spc1_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_bclk";
277 input tcu_spc2_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_bclk";
278 input tcu_spc3_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_bclk";
279 input tcu_spc4_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_bclk";
280 input tcu_spc5_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_bclk";
281 input tcu_spc6_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_bclk";
282 input tcu_spc7_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_bclk";
283 input tap_spc0_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc0_mb_aclk";
284 input tap_spc1_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc1_mb_aclk";
285 input tap_spc2_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc2_mb_aclk";
286 input tap_spc3_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc3_mb_aclk";
287 input tap_spc4_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc4_mb_aclk";
288 input tap_spc5_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc5_mb_aclk";
289 input tap_spc6_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc6_mb_aclk";
290 input tap_spc7_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc7_mb_aclk";
291 input tap_spc0_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc0_mb_bclk";
292 input tap_spc1_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc1_mb_bclk";
293 input tap_spc2_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc2_mb_bclk";
294 input tap_spc3_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc3_mb_bclk";
295 input tap_spc4_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc4_mb_bclk";
296 input tap_spc5_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc5_mb_bclk";
297 input tap_spc6_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc6_mb_bclk";
298 input tap_spc7_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc7_mb_bclk";
299 input tap_spc0_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc0_mb_clk_stop";
300 input tap_spc1_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc1_mb_clk_stop";
301 input tap_spc2_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc2_mb_clk_stop";
302 input tap_spc3_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc3_mb_clk_stop";
303 input tap_spc4_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc4_mb_clk_stop";
304 input tap_spc5_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc5_mb_clk_stop";
305 input tap_spc6_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc6_mb_clk_stop";
306 input tap_spc7_mb_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tap_spc7_mb_clk_stop";
307 input tcu_spc0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_clk_stop";
308 input tcu_spc1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_clk_stop";
309 input tcu_spc2_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_clk_stop";
310 input tcu_spc3_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_clk_stop";
311 input tcu_spc4_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_clk_stop";
312 input tcu_spc5_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_clk_stop";
313 input tcu_spc6_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_clk_stop";
314 input tcu_spc7_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_clk_stop";
315 input tcu_spc0_mbist_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_mbist_scan_out";
316 input tcu_spc1_mbist_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_mbist_scan_out";
317 input tcu_spc2_mbist_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_mbist_scan_out";
318 input tcu_spc3_mbist_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_mbist_scan_out";
319 input tcu_spc4_mbist_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_mbist_scan_out";
320 input tcu_spc5_mbist_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_mbist_scan_out";
321 input tcu_spc6_mbist_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_mbist_scan_out";
322 input tcu_spc7_mbist_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_mbist_scan_out";
323 output spc0_tcu_mbist_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc0_tcu_mbist_scan_in";
324 output spc1_tcu_mbist_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc1_tcu_mbist_scan_in";
325 output spc2_tcu_mbist_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc2_tcu_mbist_scan_in";
326 output spc3_tcu_mbist_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc3_tcu_mbist_scan_in";
327 output spc4_tcu_mbist_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc4_tcu_mbist_scan_in";
328 output spc5_tcu_mbist_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc5_tcu_mbist_scan_in";
329 output spc6_tcu_mbist_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc6_tcu_mbist_scan_in";
330 output spc7_tcu_mbist_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc7_tcu_mbist_scan_in";
331 // non-spc mbist engines
332 input tcu_se_scancollar_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_se_scancollar_in";
333 input tcu_se_scancollar_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_se_scancollar_out";
334 input tcu_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_aclk";
335 input tcu_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_bclk";
336 input tcu_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_scan_en";
337 input tcu_sii_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sii_clk_stop";
338 input tcu_sii_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sii_io_clk_stop";
339 input tcu_sio_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sio_clk_stop";
340 input tcu_sio_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sio_io_clk_stop";
341 input tcu_ncu_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ncu_clk_stop";
342 input tcu_ncu_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ncu_io_clk_stop";
343 input tcu_mcu0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu0_clk_stop";
344 input tcu_mcu0_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu0_io_clk_stop";
345 input tcu_mcu0_dr_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu0_dr_clk_stop";
346 input tcu_mcu0_fbd_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu0_fbd_clk_stop";
347 input tcu_mcu1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu1_clk_stop";
348 input tcu_mcu1_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu1_io_clk_stop";
349 input tcu_mcu1_dr_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu1_dr_clk_stop";
350 input tcu_mcu1_fbd_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu1_fbd_clk_stop";
351 input tcu_mcu2_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu2_clk_stop";
352 input tcu_mcu2_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu2_io_clk_stop";
353 input tcu_mcu2_dr_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu2_dr_clk_stop";
354 input tcu_mcu2_fbd_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu2_fbd_clk_stop";
355 input tcu_mcu3_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu3_clk_stop";
356 input tcu_mcu3_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu3_io_clk_stop";
357 input tcu_mcu3_dr_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu3_dr_clk_stop";
358 input tcu_mcu3_fbd_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu3_fbd_clk_stop";
359 input tcu_l2b0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b0_clk_stop";
360 input tcu_l2b1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b1_clk_stop";
361 input tcu_l2b2_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b2_clk_stop";
362 input tcu_l2b3_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b3_clk_stop";
363 input tcu_l2b4_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b4_clk_stop";
364 input tcu_l2b5_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b5_clk_stop";
365 input tcu_l2b6_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b6_clk_stop";
366 input tcu_l2b7_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b7_clk_stop";
367 input tcu_l2t0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t0_clk_stop";
368 input tcu_l2t1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t1_clk_stop";
369 input tcu_l2t2_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t2_clk_stop";
370 input tcu_l2t3_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t3_clk_stop";
371 input tcu_l2t4_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t4_clk_stop";
372 input tcu_l2t5_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t5_clk_stop";
373 input tcu_l2t6_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t6_clk_stop";
374 input tcu_l2t7_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t7_clk_stop";
375 input tcu_dmu_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_dmu_io_clk_stop";
376 input tcu_peu_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_peu_io_clk_stop";
377 input tcu_peu_pc_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_peu_pc_clk_stop";
378 input tcu_tds_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_tds_io_clk_stop";
379 input tcu_rtx_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rtx_io_clk_stop";
380 input tcu_rdp_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rdp_io_clk_stop";
381
382 input tcu_sii_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sii_mbist_scan_in";
383 input tcu_sio_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sio_mbist_scan_in";
384 input tcu_ncu_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ncu_mbist_scan_in";
385 input tcu_mcu0_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu0_mbist_scan_in";
386 input tcu_mcu1_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu1_mbist_scan_in";
387 input tcu_mcu2_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu2_mbist_scan_in";
388 input tcu_mcu3_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu3_mbist_scan_in";
389 input tcu_l2b0_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b0_mbist_scan_in";
390 input tcu_l2b1_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b1_mbist_scan_in";
391 input tcu_l2b2_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b2_mbist_scan_in";
392 input tcu_l2b3_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b3_mbist_scan_in";
393 input tcu_l2b4_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b4_mbist_scan_in";
394 input tcu_l2b5_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b5_mbist_scan_in";
395 input tcu_l2b6_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b6_mbist_scan_in";
396 input tcu_l2b7_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b7_mbist_scan_in";
397 input tcu_l2t0_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t0_mbist_scan_in";
398 input tcu_l2t1_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t1_mbist_scan_in";
399 input tcu_l2t2_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t2_mbist_scan_in";
400 input tcu_l2t3_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t3_mbist_scan_in";
401 input tcu_l2t4_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t4_mbist_scan_in";
402 input tcu_l2t5_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t5_mbist_scan_in";
403 input tcu_l2t6_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t6_mbist_scan_in";
404 input tcu_l2t7_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t7_mbist_scan_in";
405 input tcu_dmu_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_peu_mbist_scan_in";
406 input tcu_peu_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_peu_mbist_scan_in";
407 input tds_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tds_mbist_scan_in";
408 input rtx_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rtx_mbist_scan_in";
409 input rdp_rdmc_mbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.rdp_rdmc_mbist_scan_in";
410 output sii_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.sii_tcu_mbist_scan_out";
411 output sio_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.sio_tcu_mbist_scan_out";
412 output ncu_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.ncu_tcu_mbist_scan_out";
413 output mcu0_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.mcu0_tcu_mbist_scan_out";
414 output mcu1_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.mcu1_tcu_mbist_scan_out";
415 output mcu2_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.mcu2_tcu_mbist_scan_out";
416 output mcu3_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.mcu3_tcu_mbist_scan_out";
417 output l2b0_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2b0_tcu_mbist_scan_out";
418 output l2b1_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2b1_tcu_mbist_scan_out";
419 output l2b2_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2b2_tcu_mbist_scan_out";
420 output l2b3_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2b3_tcu_mbist_scan_out";
421 output l2b4_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2b4_tcu_mbist_scan_out";
422 output l2b5_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2b5_tcu_mbist_scan_out";
423 output l2b6_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2b6_tcu_mbist_scan_out";
424 output l2b7_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2b7_tcu_mbist_scan_out";
425 output l2t0_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2t0_tcu_mbist_scan_out";
426 output l2t1_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2t1_tcu_mbist_scan_out";
427 output l2t2_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2t2_tcu_mbist_scan_out";
428 output l2t3_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2t3_tcu_mbist_scan_out";
429 output l2t4_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2t4_tcu_mbist_scan_out";
430 output l2t5_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2t5_tcu_mbist_scan_out";
431 output l2t6_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2t6_tcu_mbist_scan_out";
432 output l2t7_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.l2t7_tcu_mbist_scan_out";
433 output dmu_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.dmu_tcu_mbist_scan_out";
434 output peu_tcu_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.peu_tcu_mbist_scan_out";
435 output tds_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.tds_mbist_scan_out";
436 output rtx_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.rtx_mbist_scan_out";
437 output rdp_rdmc_mbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.rdp_rdmc_mbist_scan_out";
438 input tcu_mio_mbist_fail INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mio_mbist_fail";
439 input tcu_mio_mbist_done INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mio_mbist_done";
440 input [165:0] DBG_DQ INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.DBG_DQ";
441#ifdef TCU_GATE
442 input [47:0] tcu_mb_start INPUT_EDGE INPUT_SKEW verilog_node "{`TCU.tcu_rdp_rdmc_mbist_start, `TCU.tcu_rtx_rxc_ipp0_mbist_start, `TCU.tcu_rtx_rxc_ipp1_mbist_start, `TCU.tcu_rtx_rxc_mb5_mbist_start, `TCU.tcu_rtx_rxc_mb6_mbist_start, `TCU.tcu_rtx_rxc_zcp0_mbist_start, `TCU.tcu_rtx_rxc_zcp1_mbist_start, `TCU.tcu_rtx_txc_txe0_mbist_start, `TCU.tcu_rtx_txc_txe1_mbist_start, `TCU.tcu_tds_smx_mbist_start, `TCU.tcu_tds_tdmc_mbist_start, `TCU.tcu_peu_mbist_start, `TCU.tcu_dmu_mbist_start[1:0], `TCU.tcu_l2t7_mbist_start, `TCU.tcu_l2t6_mbist_start, `TCU.tcu_l2t5_mbist_start, `TCU.tcu_l2t4_mbist_start, `TCU.tcu_l2t3_mbist_start, `TCU.tcu_l2t2_mbist_start, `TCU.tcu_l2t1_mbist_start, `TCU.tcu_l2t0_mbist_start, `TCU.tcu_l2b7_mbist_start, `TCU.tcu_l2b6_mbist_start, `TCU.tcu_l2b5_mbist_start, `TCU.tcu_l2b4_mbist_start, `TCU.tcu_l2b3_mbist_start, `TCU.tcu_l2b2_mbist_start, `TCU.tcu_l2b1_mbist_start, `TCU.tcu_l2b0_mbist_start, `TCU.tcu_mcu3_mbist_start, `TCU.tcu_mcu2_mbist_start, `TCU.tcu_mcu1_mbist_start, `TCU.tcu_mcu0_mbist_start, `TCU.tcu_ncu_mbist_start[1:0], `TCU.tcu_sio_mbist_start[1:0], `TCU.tcu_sii_mbist_start[1:0], `TCU.tcu_spc_mbist_start[7:0]}";
443 input jtag_dmo_enable INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_dmo_enable";
444 input [31:0] jtag_dmo_control INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_dmo_control[31:0]";
445 input [15:0] sr_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_dmo_control[47:32]";
446 input tcu_mbist_loop_mode INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_ctl__csr_mbist_mode_3_";
447#else
448
449 input [47:0] tcu_mb_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_ctl.tcu_mb_start";
450 input jtag_dmo_enable INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_ctl.jtag_dmo_enable";
451 input [31:0] jtag_dmo_control INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_ctl.jtag_dmo_control";
452 input [15:0] sr_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_ctl.dmo_ctl.sr_out";
453 input tcu_mbist_loop_mode INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_ctl.tcu_mbist_loop_mode";
454#endif
455//Add interface
456#ifdef FC_SCAN_BENCH
457#ifdef GATESIM
458 input mbist_l2tag_read_l2t0 INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t0.mbist_l2t_read";
459#else
460 input mbist_l2tag_read_l2t0 INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t0.mbist.mbist_l2tag_read";
461#endif // GATESIM
462#endif // FC_SCAN_BENCH
463#ifdef TCU_GATE
464 input [31:0] bisx_counter INPUT_EDGE INPUT_SKEW verilog_node "{`TCU.mbist_ctl__bisx_counter_31_, `TCU.mbist_ctl__bisx_counter_30_, `TCU.mbist_ctl__bisx_counter_29_, `TCU.mbist_ctl__bisx_counter_28_, `TCU.mbist_ctl__bisx_counter_27_, `TCU.mbist_ctl__bisx_counter_26_, `TCU.mbist_ctl__bisx_counter_25_, `TCU.mbist_ctl__bisx_counter_24_, `TCU.mbist_ctl__bisx_counter_23_, `TCU.mbist_ctl__bisx_counter_22_, `TCU.mbist_ctl__bisx_counter_21_, `TCU.mbist_ctl__bisx_counter_20_, `TCU.mbist_ctl__bisx_counter_19_, `TCU.mbist_ctl__bisx_counter_18_, `TCU.mbist_ctl__bisx_counter_17_, `TCU.mbist_ctl__bisx_counter_16_, `TCU.mbist_ctl__bisx_counter_15_, `TCU.mbist_ctl__bisx_counter_14_, `TCU.mbist_ctl__bisx_counter_13_, `TCU.mbist_ctl__bisx_counter_12_, `TCU.mbist_ctl__bisx_counter_11_, `TCU.mbist_ctl__bisx_counter_10_, `TCU.mbist_ctl__bisx_counter_9_, `TCU.mbist_ctl__bisx_counter_8_, `TCU.mbist_ctl__bisx_counter_7_, `TCU.mbist_ctl__bisx_counter_6_, `TCU.mbist_ctl__bisx_counter_5_, `TCU.mbist_ctl__bisx_counter_4_, `TCU.mbist_ctl__bisx_counter_3_, `TCU.mbist_ctl__bisx_counter_2_, `TCU.mbist_ctl__bisx_counter_1_, `TCU.mbist_ctl__bisx_counter_0_} ";
465#else
466 input [31:0] bisx_counter INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mbist_ctl.bisx_counter[31:0]";
467#endif
468}
469
470interface lbist {
471 input clk CLOCK verilog_node "`TCU.gclk";
472 input [(`NUM_LBIST_ENGINES-1):0] lbist_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_lbist_start";
473 input [(`NUM_LBIST_ENGINES-1):0] lbist_scan_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_lbist_scan_in";
474 input lbist_pgm INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_lbist_pgm";
475 input test_mode INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_test_mode";
476 output spc0_tcu_lbist_done OUTPUT_EDGE_N verilog_node "`TCU.spc0_tcu_lbist_done";
477 output spc1_tcu_lbist_done OUTPUT_EDGE_N verilog_node "`TCU.spc1_tcu_lbist_done";
478 output spc2_tcu_lbist_done OUTPUT_EDGE_N verilog_node "`TCU.spc2_tcu_lbist_done";
479 output spc3_tcu_lbist_done OUTPUT_EDGE_N verilog_node "`TCU.spc3_tcu_lbist_done";
480 output spc4_tcu_lbist_done OUTPUT_EDGE_N verilog_node "`TCU.spc4_tcu_lbist_done";
481 output spc5_tcu_lbist_done OUTPUT_EDGE_N verilog_node "`TCU.spc5_tcu_lbist_done";
482 output spc6_tcu_lbist_done OUTPUT_EDGE_N verilog_node "`TCU.spc6_tcu_lbist_done";
483 output spc7_tcu_lbist_done OUTPUT_EDGE_N verilog_node "`TCU.spc7_tcu_lbist_done";
484 output spc0_tcu_lbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.spc0_tcu_lbist_scan_out";
485 output spc1_tcu_lbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.spc1_tcu_lbist_scan_out";
486 output spc2_tcu_lbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.spc2_tcu_lbist_scan_out";
487 output spc3_tcu_lbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.spc3_tcu_lbist_scan_out";
488 output spc4_tcu_lbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.spc4_tcu_lbist_scan_out";
489 output spc5_tcu_lbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.spc5_tcu_lbist_scan_out";
490 output spc6_tcu_lbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.spc6_tcu_lbist_scan_out";
491 output spc7_tcu_lbist_scan_out OUTPUT_EDGE_N verilog_node "`TCU.spc7_tcu_lbist_scan_out";
492}
493
494interface scan {
495 input TCK CLOCK verilog_node "`TOP.tck"; // Using pos/neg edge for AB clock
496 input tcu_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_scan_en";
497 //input tcu_srdes_scancfg INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_srdes_scancfg";
498 input tcu_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_aclk"; // For scan flush check
499 input tcu_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_bclk"; // For scan flush check
500 //input tcu_scan_cclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_scan_cclk";
501 //input tcu_pllbypass INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_pllbypass";
502 input tcu_pce_ov INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_pce_ov";
503// input [31:0] SCAN_OUT INPUT_EDGE INPUT_SKEW verilog_node "`TOP.SCAN_OUT";
504 input SCAN_OUT31 INPUT_EDGE INPUT_SKEW verilog_node "`CPU.DBG_DQ[159]";
505 input [30:0] SCAN_OUT30_0 INPUT_EDGE INPUT_SKEW verilog_node "`CPU.DBG_DQ[73:43]";
506 input [1:0] tcu_spc0_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_scan_out";
507 input [1:0] tcu_spc1_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_scan_out";
508 input [1:0] tcu_spc2_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_scan_out";
509 input [1:0] tcu_spc3_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_scan_out";
510 input [1:0] tcu_spc4_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_scan_out";
511 input [1:0] tcu_spc5_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_scan_out";
512 input [1:0] tcu_spc6_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_scan_out";
513 input [1:0] tcu_spc7_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_scan_out";
514 input tcu_soca_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soca_scan_out";
515 input tcu_socb_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_socb_scan_out";
516 input tcu_socc_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_socc_scan_out";
517 input tcu_socd_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_socd_scan_out";
518 input tcu_soce_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soce_scan_out";
519 input tcu_socf_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_socf_scan_out";
520 input tcu_socg_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_socg_scan_out";
521 input tcu_soch_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soch_scan_out";
522 input tcu_soc0_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc0_scan_out";
523 input tcu_soc1_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc1_scan_out";
524 input tcu_soc2_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc2_scan_out";
525 input tcu_soc3_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc3_scan_out";
526 input tcu_soc4_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc4_scan_out";
527 input tcu_soc5_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc5_scan_out";
528 input tcu_soc6_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_soc6_scan_out";
529 //input tcu_srdes_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_srdes_scan_out";
530 input tcu_se_scancollar_in INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_se_scancollar_in";
531 input tcu_se_scancollar_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_se_scancollar_out";
532 input tcu_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_array_wr_inhibit";
533 input tcu_rst_flush_init_ack INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rst_flush_init_ack";
534 input tcu_array_bypass INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_array_bypass";
535 input tcu_dectest INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_dectest";
536 input tcu_muxtest INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_muxtest";
537 //output AC_TEST_MODE OUTPUT_EDGE_N verilog_node "`CPU.DBG_DQ[137]"; // moved it to pkg.*.vri
538 //output SCAN_EN OUTPUT_EDGE_N verilog_node "`CPU.DBG_DQ[74]"; // moved it to pkg.*.vri
539 //output [31:0] SCAN_IN OUTPUT_EDGE_N verilog_node "`CPU.DBG_DQ[133:103]"; // moved it to pkg.*.vri
540 //output SRDES_SCANCFG OUTPUT_EDGE_N verilog_node "`TOP.SRDES_SCANCFG";
541 //output SRDES_SCANCFG OUTPUT_EDGE_N verilog_node "`TOP.SRDES_SCANCFG";
542 output [1:0] spc0_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc0_tcu_scan_in";
543 output [1:0] spc1_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc1_tcu_scan_in";
544 output [1:0] spc2_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc2_tcu_scan_in";
545 output [1:0] spc3_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc3_tcu_scan_in";
546 output [1:0] spc4_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc4_tcu_scan_in";
547 output [1:0] spc5_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc5_tcu_scan_in";
548 output [1:0] spc6_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc6_tcu_scan_in";
549 output [1:0] spc7_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.spc7_tcu_scan_in";
550 output soca_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.soca_tcu_scan_in";
551 output socb_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.socb_tcu_scan_in";
552 output socc_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.socc_tcu_scan_in";
553 output socd_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.socd_tcu_scan_in";
554 output soce_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.soce_tcu_scan_in";
555 output socf_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.socf_tcu_scan_in";
556 output socg_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.socg_tcu_scan_in";
557 output soch_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.soch_tcu_scan_in";
558 output soc0_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.soc0_tcu_scan_in";
559 output soc1_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.soc1_tcu_scan_in";
560 output soc2_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.soc2_tcu_scan_in";
561 output soc3_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.soc3_tcu_scan_in";
562 output soc4_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.soc4_tcu_scan_in";
563 output soc5_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.soc5_tcu_scan_in";
564 output soc6_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.soc6_tcu_scan_in";
565 //output srdes_tcu_scan_in OUTPUT_EDGE_N verilog_node "`TCU.srdes_tcu_scan_in";
566}
567
568interface efuse {
569 input TCK CLOCK verilog_node "`TOP.tck";
570 input [6:0] tcu_efu_rowaddr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_rowaddr";
571 input [4:0] tcu_efu_coladdr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_coladdr";
572 input tcu_efu_read_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_read_en";
573 input [2:0] tcu_efu_read_mode INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_read_mode";
574 input tcu_efu_read_start INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_read_start";
575 input tcu_efu_fuse_bypass INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_fuse_bypass";
576 input tcu_efu_dest_sample INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_dest_sample";
577 input tcu_efu_updatedr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_updatedr";
578 input tcu_efu_shiftdr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_shiftdr";
579 input tcu_efu_capturedr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_capturedr";
580 input efu_local_fuse_bypass INPUT_EDGE INPUT_SKEW verilog_node "`EFU.local_fuse_bypass";
581 input [4:0] sbc_efa_bit_addr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.sbc_efa_bit_addr";
582 input [6:0] sbc_efa_word_addr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.sbc_efa_word_addr";
583#ifdef EFU_GATE
584 input sbc_efa_margin0_rd INPUT_EDGE INPUT_SKEW verilog_node "`EFU.sbc_efa_margin0_rd";
585 input sbc_efa_margin1_rd INPUT_EDGE INPUT_SKEW verilog_node "`EFU.sbc_efa_margin1_rd";
586#else
587 input sbc_efa_margin0_rd INPUT_EDGE INPUT_SKEW verilog_node "`EFU.u_efa_stdc.sbc_efa_margin0_rd";
588 input sbc_efa_margin1_rd INPUT_EDGE INPUT_SKEW verilog_node "`EFU.u_efa_stdc.sbc_efa_margin1_rd";
589#endif
590 input sbc_efa_power_down INPUT_EDGE INPUT_SKEW verilog_node "`EFU.sbc_efa_power_down";
591 input pwr_ok INPUT_EDGE INPUT_SKEW verilog_node "`EFU.u_efa.pwr_ok";
592
593#ifdef EFU_GATE
594 input por_l INPUT_EDGE INPUT_SKEW verilog_node "`EFU.io_por_l";
595#else
596 input por_l INPUT_EDGE INPUT_SKEW verilog_node "`EFU.por_l";
597#endif
598
599 input por_n INPUT_EDGE INPUT_SKEW verilog_node "`EFU.u_efa.por_n";
600 input pi_efa_prog_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.u_efa.pi_efa_prog_en";
601 input vpp INPUT_EDGE INPUT_SKEW verilog_node "`EFU.u_efa.vpp";
602 input [31:0] efuse_row INPUT_EDGE INPUT_SKEW verilog_node "`EFU.u_efa.efuse_row";
603 input sbc_efa_read_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.sbc_efa_read_en";
604 input [31:0] efa_read_data INPUT_EDGE INPUT_SKEW verilog_node "`EFU.u_efa.efa_read_data";
605
606#ifdef EFU_GATE
607 input [31:0] efa_out_data INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efa_sbc_data";
608#else
609 input [31:0] efa_out_data INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efa_out_data";
610#endif
611
612 input [31:0] read_data_ff INPUT_EDGE INPUT_SKEW verilog_node "`EFU.read_data_ff";
613
614#ifdef EFU_GATE
615
616 input [31:0] tck_shft_data_ff INPUT_EDGE INPUT_SKEW verilog_node "{`EFU.efu_tcu_data_out, `SHFT_DATA_30, `SHFT_DATA_29, `SHFT_DATA_28, `SHFT_DATA_27, `SHFT_DATA_26, `SHFT_DATA_25, `SHFT_DATA_24, `SHFT_DATA_23, `SHFT_DATA_22, `SHFT_DATA_21, `SHFT_DATA_20, `SHFT_DATA_19, `SHFT_DATA_18, `SHFT_DATA_17, `SHFT_DATA_16, `SHFT_DATA_15, `SHFT_DATA_14, `SHFT_DATA_13, `SHFT_DATA_12, `SHFT_DATA_11, `SHFT_DATA_10, `SHFT_DATA_9, `SHFT_DATA_8, `SHFT_DATA_7, `SHFT_DATA_6, `SHFT_DATA_5, `SHFT_DATA_4, `SHFT_DATA_3, `SHFT_DATA_2, `SHFT_DATA_1, `SHFT_DATA_0}";
617
618#else
619
620 input [31:0] tck_shft_data_ff INPUT_EDGE INPUT_SKEW verilog_node "`EFU.u_efa_stdc.tck_shft_data_ff";
621
622#endif
623
624 input efu_dmu_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_dmu_xfer_en";
625 input efu_niu_ram1_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_ram1_xfer_en";
626 input efu_niu_ram0_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_ram0_xfer_en";
627 input efu_niu_ram_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_ram_xfer_en";
628 input efu_niu_4k_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_4k_xfer_en";
629 input efu_niu_cfifo1_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_cfifo1_xfer_en";
630 input efu_niu_cfifo0_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_cfifo0_xfer_en";
631 input efu_niu_ipp1_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_ipp1_xfer_en";
632 input efu_niu_ipp0_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_ipp0_xfer_en";
633 input efu_niu_mac0_ro_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_mac0_ro_xfer_en";
634 input efu_niu_mac0_sf_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_mac0_sf_xfer_en";
635 input efu_niu_mac1_ro_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_mac1_ro_xfer_en";
636 input efu_niu_mac1_sf_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_mac1_sf_xfer_en";
637 input efu_ncu_srlnum2_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_ncu_srlnum2_xfer_en";
638 input efu_ncu_srlnum1_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_ncu_srlnum1_xfer_en";
639 input efu_ncu_srlnum0_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_ncu_srlnum0_xfer_en";
640 input efu_ncu_bankavl_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_ncu_bankavl_xfer_en";
641 input efu_ncu_coreavl_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_ncu_coreavl_xfer_en";
642 input efu_l2d7_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b7_fuse_xfer_en";
643 input efu_l2d6_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b6_fuse_xfer_en";
644 input efu_l2d5_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b5_fuse_xfer_en";
645 input efu_l2d4_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b4_fuse_xfer_en";
646 input efu_l2d3_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b3_fuse_xfer_en";
647 input efu_l2d2_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b2_fuse_xfer_en";
648 input efu_l2d1_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b1_fuse_xfer_en";
649 input efu_l2d0_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b0_fuse_xfer_en";
650 input efu_l2t7_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t7_fuse_xfer_en";
651 input efu_l2t6_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t6_fuse_xfer_en";
652 input efu_l2t5_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t5_fuse_xfer_en";
653 input efu_l2t4_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t4_fuse_xfer_en";
654 input efu_l2t3_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t3_fuse_xfer_en";
655 input efu_l2t2_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t2_fuse_xfer_en";
656 input efu_l2t1_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t1_fuse_xfer_en";
657 input efu_l2t0_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t0_fuse_xfer_en";
658 input efu_spc7_fuse_dxfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc7_fuse_dxfer_en";
659 input efu_spc7_fuse_ixfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc7_fuse_ixfer_en";
660 input efu_spc6_fuse_dxfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc6_fuse_dxfer_en";
661 input efu_spc6_fuse_ixfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc6_fuse_ixfer_en";
662 input efu_spc5_fuse_dxfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc5_fuse_dxfer_en";
663 input efu_spc5_fuse_ixfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc5_fuse_ixfer_en";
664 input efu_spc4_fuse_dxfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc4_fuse_dxfer_en";
665 input efu_spc4_fuse_ixfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc4_fuse_ixfer_en";
666 input efu_spc3_fuse_dxfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc3_fuse_dxfer_en";
667 input efu_spc3_fuse_ixfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc3_fuse_ixfer_en";
668 input efu_spc2_fuse_dxfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc2_fuse_dxfer_en";
669 input efu_spc2_fuse_ixfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc2_fuse_ixfer_en";
670 input efu_spc1_fuse_dxfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc1_fuse_dxfer_en";
671 input efu_spc1_fuse_ixfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc1_fuse_ixfer_en";
672 input efu_spc0_fuse_dxfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc0_fuse_dxfer_en";
673 input efu_spc0_fuse_ixfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc0_fuse_ixfer_en";
674 output dmu_efu_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.dmu_efu_xfer_en";
675 output niu_efu_ram1_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_ram1_xfer_en";
676 output niu_efu_ram0_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_ram0_xfer_en";
677 output niu_efu_ram_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_ram_xfer_en";
678 output niu_efu_4k_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_4k_xfer_en";
679 output niu_efu_cfifo1_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_cfifo1_xfer_en";
680 output niu_efu_cfifo0_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_cfifo0_xfer_en";
681 output niu_efu_ipp1_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_ipp1_xfer_en";
682 output niu_efu_ipp0_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_ipp0_xfer_en";
683 output niu_efu_mac0_ro_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_mac0_ro_xfer_en";
684 output niu_efu_mac0_sf_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_mac0_sf_xfer_en";
685 output niu_efu_mac1_ro_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_mac1_ro_xfer_en";
686 output niu_efu_mac1_sf_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.niu_efu_mac1_sf_xfer_en";
687 output l2d7_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2b7_efu_fuse_xfer_en";
688 output l2d6_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2b6_efu_fuse_xfer_en";
689 output l2d5_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2b5_efu_fuse_xfer_en";
690 output l2d4_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2b4_efu_fuse_xfer_en";
691 output l2d3_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2b3_efu_fuse_xfer_en";
692 output l2d2_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2b2_efu_fuse_xfer_en";
693 output l2d1_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2b1_efu_fuse_xfer_en";
694 output l2d0_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2b0_efu_fuse_xfer_en";
695 output l2t7_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2t7_efu_fuse_xfer_en";
696 output l2t6_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2t6_efu_fuse_xfer_en";
697 output l2t5_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2t5_efu_fuse_xfer_en";
698 output l2t4_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2t4_efu_fuse_xfer_en";
699 output l2t3_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2t3_efu_fuse_xfer_en";
700 output l2t2_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2t2_efu_fuse_xfer_en";
701 output l2t1_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2t1_efu_fuse_xfer_en";
702 output l2t0_efu_fuse_xfer_en OUTPUT_EDGE_N verilog_node "`EFU.l2t0_efu_fuse_xfer_en";
703 output spc7_efu_fuse_dxfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc7_efu_fuse_dxfer_en";
704 output spc7_efu_fuse_ixfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc7_efu_fuse_ixfer_en";
705 output spc6_efu_fuse_dxfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc6_efu_fuse_dxfer_en";
706 output spc6_efu_fuse_ixfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc6_efu_fuse_ixfer_en";
707 output spc5_efu_fuse_dxfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc5_efu_fuse_dxfer_en";
708 output spc5_efu_fuse_ixfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc5_efu_fuse_ixfer_en";
709 output spc4_efu_fuse_dxfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc4_efu_fuse_dxfer_en";
710 output spc4_efu_fuse_ixfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc4_efu_fuse_ixfer_en";
711 output spc3_efu_fuse_dxfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc3_efu_fuse_dxfer_en";
712 output spc3_efu_fuse_ixfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc3_efu_fuse_ixfer_en";
713 output spc2_efu_fuse_dxfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc2_efu_fuse_dxfer_en";
714 output spc2_efu_fuse_ixfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc2_efu_fuse_ixfer_en";
715 output spc1_efu_fuse_dxfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc1_efu_fuse_dxfer_en";
716 output spc1_efu_fuse_ixfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc1_efu_fuse_ixfer_en";
717 output spc0_efu_fuse_dxfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc0_efu_fuse_dxfer_en";
718 output spc0_efu_fuse_ixfer_en OUTPUT_EDGE_N verilog_node "`EFU.spc0_efu_fuse_ixfer_en";
719 input efu_l2b1_fuse_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b1_fuse_xfer_en";
720 input efu_ncu_fusestat_xfer_en INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.ncu.efu_ncu_fusestat_xfer_en";
721 input [7:0] ncu_tcu_bank_avail INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.ncu.ncu_tcu_bank_avail";
722 input tcu_efu_data_in INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.tcu_efu_data_in";
723 input efu_tcu_data_out INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.tcu.efu_tcu_data_out";
724
725#ifdef NCU_GATE
726
727 input [63:0] creg_fusestat INPUT_EDGE INPUT_SKEW verilog_node "{`FUSE_STAT_63 ,`FUSE_STAT_62 ,`FUSE_STAT_61 ,`FUSE_STAT_60 ,`FUSE_STAT_59 ,`FUSE_STAT_58 ,`FUSE_STAT_57 ,`FUSE_STAT_56 ,`FUSE_STAT_55 ,`FUSE_STAT_54 ,`FUSE_STAT_53 ,`FUSE_STAT_52 ,`FUSE_STAT_51,`FUSE_STAT_50, `FUSE_STAT_49 ,`FUSE_STAT_48 ,`FUSE_STAT_47 ,`FUSE_STAT_46 ,`FUSE_STAT_45 ,`FUSE_STAT_44 ,`FUSE_STAT_43 ,`FUSE_STAT_42 ,`FUSE_STAT_41 ,`FUSE_STAT_40 ,`FUSE_STAT_39 ,`FUSE_STAT_38 ,`FUSE_STAT_37 ,`FUSE_STAT_36 ,`FUSE_STAT_35 ,`FUSE_STAT_34 ,`FUSE_STAT_33 ,`FUSE_STAT_32 ,`FUSE_STAT_31 ,`FUSE_STAT_30, `FUSE_STAT_29 ,`FUSE_STAT_28 ,`FUSE_STAT_27 ,`FUSE_STAT_26 ,`FUSE_STAT_25 ,`FUSE_STAT_24 ,`FUSE_STAT_23 ,`FUSE_STAT_22 ,`FUSE_STAT_21 ,`FUSE_STAT_20, `FUSE_STAT_19 ,`FUSE_STAT_18 ,`FUSE_STAT_17 ,`FUSE_STAT_16 ,`FUSE_STAT_15 ,`FUSE_STAT_14 ,`FUSE_STAT_13 ,`FUSE_STAT_12 ,`FUSE_STAT_11 ,`FUSE_STAT_10, `FUSE_STAT_9 ,`FUSE_STAT_8 ,`FUSE_STAT_7 ,`FUSE_STAT_6 ,`FUSE_STAT_5 ,`FUSE_STAT_4 ,`FUSE_STAT_3 ,`FUSE_STAT_2 ,`FUSE_STAT_1 ,`FUSE_STAT_0 }";
728
729#else
730
731 input [63:0] creg_fusestat INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.creg_fusestat";
732
733#endif
734
735 output io_vpp OUTPUT_EDGE_N verilog_node "`EFU.io_vpp";
736 output io_pgrm_en OUTPUT_EDGE_N verilog_node "`EFU.io_pgrm_en";
737 output VPP OUTPUT_EDGE_N verilog_node "`TOP.cpu.VPP";
738 output PGRM_EN OUTPUT_EDGE_N verilog_node "`TOP.cpu.PGRM_EN";
739
740#ifdef NCU_GATE
741 input [7:0] coreavail INPUT_EDGE INPUT_SKEW verilog_node "{`TOP.cpu.ncu.ncu_spc7_core_available,`TOP.cpu.ncu.ncu_spc6_core_available,`TOP.cpu.ncu.ncu_spc5_core_available,`TOP.cpu.ncu.ncu_spc4_core_available,`TOP.cpu.ncu.ncu_spc3_core_available,`TOP.cpu.ncu.ncu_spc2_core_available,`TOP.cpu.ncu.ncu_spc1_core_available,`TOP.cpu.ncu.ncu_spc0_core_available}";
742 input [7:0] bankavail INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_tcu_bank_avail";
743 input [21:0] sernum0 INPUT_EDGE INPUT_SKEW verilog_node "{`NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_21_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_20_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_19_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_18_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_17_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_16_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_15_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_14_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_13_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_12_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_11_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_10_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_9_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_8_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_7_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_6_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_5_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_4_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_3_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_2_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_1_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum0_0_}";
744 input [21:0] sernum1 INPUT_EDGE INPUT_SKEW verilog_node "{`NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_21_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_20_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_19_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_18_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_17_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_16_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_15_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_14_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_13_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_12_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_11_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_10_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_9_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_8_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_7_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_6_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_5_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_4_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_3_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_2_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_1_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum1_0_}";
745 input [21:0] sernum2 INPUT_EDGE INPUT_SKEW verilog_node "{`NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_19_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_18_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_17_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_16_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_15_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_14_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_13_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_12_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_11_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_10_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_9_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_8_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_7_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_6_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_5_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_4_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_3_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_2_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_1_, `NCU.ncu_scd_ctl__ncu_c2iscd_ctl_ncu_ctrl_ctl_sernum2_0_}";
746#else
747 inout [7:0] coreavail OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.coreavail";
748 inout [7:0] bankavail OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.bankavail";
749 input [21:0] sernum0 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.sernum0";
750 input [21:0] sernum1 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.sernum1";
751 input [19:0] sernum2 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.sernum2";
752
753#endif
754
755#ifdef TCU_GATE
756 input [14:0] efcnt_dout INPUT_EDGE INPUT_SKEW verilog_node "{`TCU.sigmux_ctl__efcnt_dout_14_,`TCU.sigmux_ctl__efcnt_dout_13_,`TCU.sigmux_ctl__efcnt_dout_12_,`TCU.sigmux_ctl__efcnt_dout_11_,`TCU.sigmux_ctl__efcnt_dout_10_,`TCU.sigmux_ctl__efcnt_dout_9_,`TCU.sigmux_ctl__efcnt_dout_8_,`TCU.sigmux_ctl__efcnt_dout_7_,`TCU.sigmux_ctl__efcnt_dout_6_,`TCU.sigmux_ctl__efcnt_dout_5_,`TCU.sigmux_ctl__efcnt_dout_4_,`TCU.sigmux_ctl__efcnt_dout_3_,`TCU.sigmux_ctl__efcnt_dout_2_,`TCU.sigmux_ctl__efcnt_dout_1_,`TCU.sigmux_ctl__efcnt_dout_0_}";
757 input efu_done_int INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rst_efu_done";
758#else
759 input [14:0] efcnt_dout INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.efcnt_dout";
760 input efu_done_int INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.efu_done_int";
761#endif
762}
763
764interface efuse_gclk_if {
765 input GCLK CLOCK verilog_node "`EFU.gclk";
766 input efu_niu_fclrz INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_fclrz";
767 input efu_psr_fclrz INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_psr_fclrz";
768 input efu_mcu_fclrz INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_mcu_fclrz";
769 input efu_dmu_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_dmu_clr";
770 input efu_niu_ipp0_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_ipp0_clr";
771 input efu_niu_ipp1_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_ipp1_clr";
772 input efu_niu_mac0_ro_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_mac0_ro_clr";
773 input efu_niu_mac0_sf_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_mac0_sf_clr";
774 input efu_niu_mac1_ro_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_mac1_ro_clr";
775 input efu_niu_mac1_sf_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_mac1_sf_clr";
776 input efu_niu_cfifo0_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_cfifo0_clr";
777 input efu_niu_cfifo1_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_cfifo1_clr";
778 input efu_niu_ram1_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_ram1_clr";
779 input efu_niu_ram0_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_ram0_clr";
780 input efu_niu_ram_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_ram_clr";
781 input efu_niu_4k_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_niu_4k_clr";
782 input efu_l2b7_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b7_fuse_clr";
783 input efu_l2b6_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b6_fuse_clr";
784 input efu_l2b5_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b5_fuse_clr";
785 input efu_l2b4_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b4_fuse_clr";
786 input efu_l2b3_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b3_fuse_clr";
787 input efu_l2b2_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b2_fuse_clr";
788 input efu_l2b1_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b1_fuse_clr";
789 input efu_l2b0_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2b0_fuse_clr";
790 input efu_l2t7_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t7_fuse_clr";
791 input efu_l2t6_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t6_fuse_clr";
792 input efu_l2t5_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t5_fuse_clr";
793 input efu_l2t4_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t4_fuse_clr";
794 input efu_l2t3_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t3_fuse_clr";
795 input efu_l2t2_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t2_fuse_clr";
796 input efu_l2t1_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t1_fuse_clr";
797 input efu_l2t0_fuse_clr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_l2t0_fuse_clr";
798 input efu_spc7_fuse_dclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc7_fuse_dclr";
799 input efu_spc7_fuse_iclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc7_fuse_iclr";
800 input efu_spc6_fuse_dclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc6_fuse_dclr";
801 input efu_spc6_fuse_iclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc6_fuse_iclr";
802 input efu_spc5_fuse_dclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc5_fuse_dclr";
803 input efu_spc5_fuse_iclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc5_fuse_iclr";
804 input efu_spc4_fuse_dclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc4_fuse_dclr";
805 input efu_spc4_fuse_iclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc4_fuse_iclr";
806 input efu_spc3_fuse_dclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc3_fuse_dclr";
807 input efu_spc3_fuse_iclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc3_fuse_iclr";
808 input efu_spc2_fuse_dclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc2_fuse_dclr";
809 input efu_spc2_fuse_iclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc2_fuse_iclr";
810 input efu_spc1_fuse_dclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc1_fuse_dclr";
811 input efu_spc1_fuse_iclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc1_fuse_iclr";
812 input efu_spc0_fuse_dclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc0_fuse_dclr";
813 input efu_spc0_fuse_iclr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.efu_spc0_fuse_iclr";
814}
815
816#ifndef FC_SCAN_BENCH
817interface cmp_spc {
818#ifdef TCU_GATE
819 input CLK CLOCK verilog_node "`TCU.clkgen_tcu_io__cclk";
820#else
821 input CLK CLOCK verilog_node "`TCU.clkgen_tcu_io.l2clk";
822#endif
823 input core_available_0 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc0_core_available" ;
824 input core_enable_status_0 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc0_core_enable_status" ;
825 input core_running_0 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc0_core_running" ;
826 input core_running_status_0 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc0_ncu_core_running_status" ;
827 input core_available_1 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc1_core_available" ;
828 input core_enable_status_1 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc1_core_enable_status" ;
829 input core_running_1 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc1_core_running" ;
830 input core_running_status_1 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc1_ncu_core_running_status" ;
831 input core_available_2 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc2_core_available" ;
832 input core_enable_status_2 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc2_core_enable_status" ;
833 input core_running_2 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc2_core_running" ;
834 input core_running_status_2 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc2_ncu_core_running_status" ;
835 input core_available_3 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc3_core_available" ;
836 input core_enable_status_3 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc3_core_enable_status" ;
837 input core_running_3 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc3_core_running" ;
838 input core_running_status_3 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc3_ncu_core_running_status" ;
839 input core_available_4 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc4_core_available" ;
840 input core_enable_status_4 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc4_core_enable_status" ;
841 input core_running_4 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc4_core_running" ;
842 input core_running_status_4 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc4_ncu_core_running_status" ;
843 input core_available_5 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc5_core_available" ;
844 input core_enable_status_5 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc5_core_enable_status" ;
845 input core_running_5 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc5_core_running" ;
846 input core_running_status_5 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc5_ncu_core_running_status" ;
847 input core_available_6 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc6_core_available" ;
848 input core_enable_status_6 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc6_core_enable_status" ;
849 input core_running_6 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc6_core_running" ;
850 input core_running_status_6 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc6_ncu_core_running_status" ;
851 input core_available_7 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc7_core_available" ;
852 input core_enable_status_7 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc7_core_enable_status" ;
853 input core_running_7 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc7_core_running" ;
854 input core_running_status_7 INPUT_EDGE INPUT_SKEW verilog_node "`NCU.spc7_ncu_core_running_status" ;
855 output [21:0] tb_fusedata_init OUTPUT_EDGE_N verilog_node "`MONTCU.tb_fusedata_init"; // Set core testbench core available
856}
857
858interface spc_debug {
859 input CLK CLOCK verilog_node "`TCU.gclk";
860 input [7:0] tcu_ss_mode INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ss_mode";
861 input [7:0] tcu_do_mode INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_do_mode";
862 input [7:0] tcu_ss_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ss_request";
863 input [7:0] ncu_spc7_core_running INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc7_core_running";
864 input [7:0] ncu_spc6_core_running INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc6_core_running";
865 input [7:0] ncu_spc5_core_running INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc5_core_running";
866 input [7:0] ncu_spc4_core_running INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc4_core_running";
867 input [7:0] ncu_spc3_core_running INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc3_core_running";
868 input [7:0] ncu_spc2_core_running INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc2_core_running";
869 input [7:0] ncu_spc1_core_running INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc1_core_running";
870 input [7:0] ncu_spc0_core_running INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_spc0_core_running";
871 output spc7_ss_complete OUTPUT_EDGE_N verilog_node "`TCU.spc7_ss_complete";
872 output spc6_ss_complete OUTPUT_EDGE_N verilog_node "`TCU.spc6_ss_complete";
873 output spc5_ss_complete OUTPUT_EDGE_N verilog_node "`TCU.spc5_ss_complete";
874 output spc4_ss_complete OUTPUT_EDGE_N verilog_node "`TCU.spc4_ss_complete";
875 output spc3_ss_complete OUTPUT_EDGE_N verilog_node "`TCU.spc3_ss_complete";
876 output spc2_ss_complete OUTPUT_EDGE_N verilog_node "`TCU.spc2_ss_complete";
877 output spc1_ss_complete OUTPUT_EDGE_N verilog_node "`TCU.spc1_ss_complete";
878 output spc0_ss_complete OUTPUT_EDGE_N verilog_node "`TCU.spc0_ss_complete";
879 output [7:0] spc7_ncu_core_running_status OUTPUT_EDGE_N verilog_node "`NCU.spc7_ncu_core_running_status";
880 output [7:0] spc6_ncu_core_running_status OUTPUT_EDGE_N verilog_node "`NCU.spc6_ncu_core_running_status";
881 output [7:0] spc5_ncu_core_running_status OUTPUT_EDGE_N verilog_node "`NCU.spc5_ncu_core_running_status";
882 output [7:0] spc4_ncu_core_running_status OUTPUT_EDGE_N verilog_node "`NCU.spc4_ncu_core_running_status";
883 output [7:0] spc3_ncu_core_running_status OUTPUT_EDGE_N verilog_node "`NCU.spc3_ncu_core_running_status";
884 output [7:0] spc2_ncu_core_running_status OUTPUT_EDGE_N verilog_node "`NCU.spc2_ncu_core_running_status";
885 output [7:0] spc1_ncu_core_running_status OUTPUT_EDGE_N verilog_node "`NCU.spc1_ncu_core_running_status";
886 output [7:0] spc0_ncu_core_running_status OUTPUT_EDGE_N verilog_node "`NCU.spc0_ncu_core_running_status";
887}
888
889interface tcu_siu {
890 input CLK CLOCK verilog_node "`TCU.l2clk"; // changed from `TCU.gclk
891 input tcu_sii_data INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sii_data";
892 input tcu_sii_vld INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sii_vld";
893 output sio_tcu_data OUTPUT_EDGE_N verilog_node "`TCU.sio_tcu_data";
894 output sio_tcu_vld OUTPUT_EDGE_N verilog_node "`TCU.sio_tcu_vld";
895 input sio_tcu_data__in PSAMPLE #-1 verilog_node "`TCU.sio_tcu_data"; // __in: input to vera
896 input sio_tcu_vld__in PSAMPLE #-1 verilog_node "`TCU.sio_tcu_vld"; // __in: input to vera
897}
898#endif //FC_SCAN_BENCH
899
900interface internalcmp {
901 input CLK CLOCK verilog_node "`TOP.cpu.ccu.gclk";
902}
903
904//interface eful2clk {
905// input CLK CLOCK verilog_node "`TOP.cpu.efu.l2clk"; // this sig will be removed from the new rtl
906//}
907
908interface shscan {
909 input TCK CLOCK verilog_node "`TOP.tck";
910 input tcu_spc0_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_shscan_clk_stop" ;
911 input tcu_spc1_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_shscan_clk_stop" ;
912 input tcu_spc2_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_shscan_clk_stop" ;
913 input tcu_spc3_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_shscan_clk_stop" ;
914 input tcu_spc4_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_shscan_clk_stop" ;
915 input tcu_spc5_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_shscan_clk_stop" ;
916 input tcu_spc6_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_shscan_clk_stop" ;
917 input tcu_spc7_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_shscan_clk_stop" ;
918 input tcu_spc_shscan_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_shscan_aclk" ;
919 input tcu_spc_shscan_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_shscan_bclk" ;
920 input tcu_spc_shscan_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_shscan_scan_en" ;
921 input tcu_spc_shscan_pce_ov INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_shscan_pce_ov" ;
922 input [2:0] tcu_spc_shscanid INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_shscanid" ;
923 input tcu_l2t0_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t0_shscan_clk_stop" ;
924 input tcu_l2t1_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t1_shscan_clk_stop" ;
925 input tcu_l2t2_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t2_shscan_clk_stop" ;
926 input tcu_l2t3_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t3_shscan_clk_stop" ;
927 input tcu_l2t4_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t4_shscan_clk_stop" ;
928 input tcu_l2t5_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t5_shscan_clk_stop" ;
929 input tcu_l2t6_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t6_shscan_clk_stop" ;
930 input tcu_l2t7_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t7_shscan_clk_stop" ;
931 input tcu_l2t_shscan_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t_shscan_aclk" ;
932 input tcu_l2t_shscan_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t_shscan_bclk" ;
933 input tcu_l2t_shscan_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t_shscan_scan_en" ;
934 input tcu_l2t_shscan_pce_ov INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t_shscan_pce_ov" ;
935 input tcu_spc0_shscan_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_shscan_scan_out";
936 input tcu_spc1_shscan_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_shscan_scan_out";
937 input tcu_spc2_shscan_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_shscan_scan_out";
938 input tcu_spc3_shscan_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_shscan_scan_out";
939 input tcu_spc4_shscan_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_shscan_scan_out";
940 input tcu_spc5_shscan_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_shscan_scan_out";
941 input tcu_spc6_shscan_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_shscan_scan_out";
942 input tcu_spc7_shscan_scan_out INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_shscan_scan_out";
943 inout spc0_tcu_shscan_scan_in OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc0_tcu_shscan_scan_in";
944 inout spc1_tcu_shscan_scan_in OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc1_tcu_shscan_scan_in";
945 inout spc2_tcu_shscan_scan_in OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc2_tcu_shscan_scan_in";
946 inout spc3_tcu_shscan_scan_in OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc3_tcu_shscan_scan_in";
947 inout spc4_tcu_shscan_scan_in OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc4_tcu_shscan_scan_in";
948 inout spc5_tcu_shscan_scan_in OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc5_tcu_shscan_scan_in";
949 inout spc6_tcu_shscan_scan_in OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc6_tcu_shscan_scan_in";
950 inout spc7_tcu_shscan_scan_in OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc7_tcu_shscan_scan_in";
951}
952
953//==========================================================================
954// WHAT: clock stop signals from TCU (ie. tcu_*_clk_stop)
955// NOTE: listed in the same order as "stop number" specified by Clock Domain Register
956//==========================================================================
957
958interface tcu_clkstop_if {
959 input clk CLOCK verilog_node "`TCU.l2clk";
960
961 //--- clk stop to spc cores ---
962 input tcu_spc0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_clk_stop";
963 input tcu_spc1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_clk_stop";
964 input tcu_spc2_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_clk_stop";
965 input tcu_spc3_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_clk_stop";
966 input tcu_spc4_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_clk_stop";
967 input tcu_spc5_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_clk_stop";
968 input tcu_spc6_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_clk_stop";
969 input tcu_spc7_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_clk_stop";
970 input tcu_spc0_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_shscan_clk_stop";
971 input tcu_spc1_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_shscan_clk_stop";
972 input tcu_spc2_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_shscan_clk_stop";
973 input tcu_spc3_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_shscan_clk_stop";
974 input tcu_spc4_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_shscan_clk_stop";
975 input tcu_spc5_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_shscan_clk_stop";
976 input tcu_spc6_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_shscan_clk_stop";
977 input tcu_spc7_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_shscan_clk_stop";
978
979 //--- clk stop to L2 banks ---
980 input tcu_l2b0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b0_clk_stop";
981 input tcu_l2b1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b1_clk_stop";
982 input tcu_l2b2_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b2_clk_stop";
983 input tcu_l2b3_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b3_clk_stop";
984 input tcu_l2b4_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b4_clk_stop";
985 input tcu_l2b5_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b5_clk_stop";
986 input tcu_l2b6_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b6_clk_stop";
987 input tcu_l2b7_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2b7_clk_stop";
988 input tcu_l2d0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2d0_clk_stop";
989 input tcu_l2d1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2d1_clk_stop";
990 input tcu_l2d2_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2d2_clk_stop";
991 input tcu_l2d3_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2d3_clk_stop";
992 input tcu_l2d4_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2d4_clk_stop";
993 input tcu_l2d5_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2d5_clk_stop";
994 input tcu_l2d6_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2d6_clk_stop";
995 input tcu_l2d7_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2d7_clk_stop";
996 input tcu_l2t0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t0_clk_stop";
997 input tcu_l2t1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t1_clk_stop";
998 input tcu_l2t2_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t2_clk_stop";
999 input tcu_l2t3_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t3_clk_stop";
1000 input tcu_l2t4_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t4_clk_stop";
1001 input tcu_l2t5_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t5_clk_stop";
1002 input tcu_l2t6_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t6_clk_stop";
1003 input tcu_l2t7_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t7_clk_stop";
1004 input tcu_l2t0_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t0_shscan_clk_stop";
1005 input tcu_l2t1_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t1_shscan_clk_stop";
1006 input tcu_l2t2_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t2_shscan_clk_stop";
1007 input tcu_l2t3_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t3_shscan_clk_stop";
1008 input tcu_l2t4_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t4_shscan_clk_stop";
1009 input tcu_l2t5_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t5_shscan_clk_stop";
1010 input tcu_l2t6_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t6_shscan_clk_stop";
1011 input tcu_l2t7_shscan_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t7_shscan_clk_stop";
1012
1013 //--- clk stop to MCU ---
1014 input tcu_mcu0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu0_clk_stop";
1015 input tcu_mcu1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu1_clk_stop";
1016 input tcu_mcu2_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu2_clk_stop";
1017 input tcu_mcu3_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu3_clk_stop";
1018 input tcu_mcu0_dr_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu0_dr_clk_stop";
1019 input tcu_mcu1_dr_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu1_dr_clk_stop";
1020 input tcu_mcu2_dr_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu2_dr_clk_stop";
1021 input tcu_mcu3_dr_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu3_dr_clk_stop";
1022 input tcu_mcu0_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu0_io_clk_stop";
1023 input tcu_mcu1_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu1_io_clk_stop";
1024 input tcu_mcu2_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu2_io_clk_stop";
1025 input tcu_mcu3_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu3_io_clk_stop";
1026 input tcu_mcu0_fbd_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu0_fbd_clk_stop";
1027 input tcu_mcu1_fbd_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu1_fbd_clk_stop";
1028 input tcu_mcu2_fbd_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu2_fbd_clk_stop";
1029 input tcu_mcu3_fbd_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mcu3_fbd_clk_stop";
1030
1031 //--- clk stop to SOC0: ccx, db0, db1, efu, mio, ncu, ssi, sio ---
1032 input tcu_ccx_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ccx_clk_stop";
1033 input tcu_db0_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_db0_clk_stop";
1034 input tcu_db1_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_db1_clk_stop";
1035 input tcu_efu_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_clk_stop";
1036 input tcu_mio_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mio_clk_stop";
1037 input tcu_ncu_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ncu_clk_stop";
1038 input tcu_sii_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sii_clk_stop";
1039 input tcu_sio_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sio_clk_stop";
1040 //--- IO clk stop to SOC0: efu, mio, ncu, ssi, sio ---
1041 input tcu_efu_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_efu_io_clk_stop";
1042 input tcu_ncu_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ncu_io_clk_stop";
1043 input tcu_sii_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sii_io_clk_stop";
1044 input tcu_sio_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_sio_io_clk_stop";
1045
1046 //--- clk stop to SOC1: mac, rdp, rtx, and tds ---
1047 input tcu_mac_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mac_io_clk_stop";
1048 input tcu_rdp_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rdp_io_clk_stop";
1049 input tcu_rtx_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rtx_io_clk_stop";
1050 input tcu_tds_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_tds_io_clk_stop";
1051
1052 //--- clk stop to SOC2: dmu ---
1053 input tcu_dmu_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_dmu_io_clk_stop";
1054
1055 //--- clk stop to SOC3: peu ---
1056 input tcu_peu_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_peu_io_clk_stop";
1057 input tcu_peu_pc_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_peu_pc_clk_stop";
1058
1059 //--- special cases: clk stop to ccu and rst---
1060 input tcu_ccu_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ccu_clk_stop";
1061 input tcu_ccu_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_ccu_io_clk_stop";
1062 input tcu_rst_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rst_clk_stop";
1063 input tcu_rst_io_clk_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_rst_io_clk_stop";
1064}
1065
1066//==========================================================================
1067// WHAT: debug event signals from spc cores and SOC to TCU
1068//==========================================================================
1069
1070interface tcu_dbg_event_if {
1071#ifdef TCU_GATE
1072 input l2clk CLOCK verilog_node "`TCU.clkgen_tcu_cmp__cclk";
1073#else
1074 input l2clk CLOCK verilog_node "`TCU.clkgen_tcu_cmp.l2clk";
1075#endif
1076
1077 //--- debug events from spc cores to TCU ---
1078 input spc0_hardstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc0_hardstop_request";
1079 input spc1_hardstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc1_hardstop_request";
1080 input spc2_hardstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc2_hardstop_request";
1081 input spc3_hardstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc3_hardstop_request";
1082 input spc4_hardstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc4_hardstop_request";
1083 input spc5_hardstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc5_hardstop_request";
1084 input spc6_hardstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc6_hardstop_request";
1085 input spc7_hardstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc7_hardstop_request";
1086 input spc0_softstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc0_softstop_request";
1087 input spc1_softstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc1_softstop_request";
1088 input spc2_softstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc2_softstop_request";
1089 input spc3_softstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc3_softstop_request";
1090 input spc4_softstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc4_softstop_request";
1091 input spc5_softstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc5_softstop_request";
1092 input spc6_softstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc6_softstop_request";
1093 input spc7_softstop_request INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc7_softstop_request";
1094 input spc0_trigger_pulse INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc0_trigger_pulse";
1095 input spc1_trigger_pulse INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc1_trigger_pulse";
1096 input spc2_trigger_pulse INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc2_trigger_pulse";
1097 input spc3_trigger_pulse INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc3_trigger_pulse";
1098 input spc4_trigger_pulse INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc4_trigger_pulse";
1099 input spc5_trigger_pulse INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc5_trigger_pulse";
1100 input spc6_trigger_pulse INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc6_trigger_pulse";
1101 input spc7_trigger_pulse INPUT_EDGE INPUT_SKEW verilog_node "`TCU.spc7_trigger_pulse";
1102
1103 //--- debug events from SOC (ie. dbg1) to TCU---
1104 //--- WARNING: they are in IO clk domain ----
1105 input dbg1_tcu_soc_hard_stop INPUT_EDGE INPUT_SKEW verilog_node "`TCU.dbg1_tcu_soc_hard_stop";
1106 input dbg1_tcu_soc_asrt_trigout INPUT_EDGE INPUT_SKEW verilog_node "`TCU.dbg1_tcu_soc_asrt_trigout";
1107
1108 //---trigger out to package pin. WARNING: clocked by IO2X clock---
1109 input tcu_mio_trigout INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_mio_trigout";
1110
1111 //---triger in from package pin. WARNING: async signal and is synchronized by TCU---
1112 input mio_tcu_trigin INPUT_EDGE INPUT_SKEW verilog_node "`TCU.mio_tcu_trigin";
1113}
1114
1115//==========================================================================
1116// WHAT: debug event signals from spc cores to TCU (output from Vera)
1117// WARN: no dbg1_tcu_soc_hard_stop and dbg1_tcu_soc_asrt_trigout. They're internal signals
1118//==========================================================================
1119
1120interface tcu_dbg_event_out_if {
1121#ifdef TCU_GATE
1122 input l2clk CLOCK verilog_node "`TCU.clkgen_tcu_cmp__cclk";
1123#else
1124 input l2clk CLOCK verilog_node "`TCU.clkgen_tcu_cmp.l2clk";
1125#endif
1126 output spc0_hardstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc0_hardstop_request";
1127 output spc1_hardstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc1_hardstop_request";
1128 output spc2_hardstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc2_hardstop_request";
1129 output spc3_hardstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc3_hardstop_request";
1130 output spc4_hardstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc4_hardstop_request";
1131 output spc5_hardstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc5_hardstop_request";
1132 output spc6_hardstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc6_hardstop_request";
1133 output spc7_hardstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc7_hardstop_request";
1134 output spc0_softstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc0_softstop_request";
1135 output spc1_softstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc1_softstop_request";
1136 output spc2_softstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc2_softstop_request";
1137 output spc3_softstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc3_softstop_request";
1138 output spc4_softstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc4_softstop_request";
1139 output spc5_softstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc5_softstop_request";
1140 output spc6_softstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc6_softstop_request";
1141 output spc7_softstop_request OUTPUT_EDGE_N verilog_node "`TCU.spc7_softstop_request";
1142 output spc0_trigger_pulse OUTPUT_EDGE_N verilog_node "`TCU.spc0_trigger_pulse";
1143 output spc1_trigger_pulse OUTPUT_EDGE_N verilog_node "`TCU.spc1_trigger_pulse";
1144 output spc2_trigger_pulse OUTPUT_EDGE_N verilog_node "`TCU.spc2_trigger_pulse";
1145 output spc3_trigger_pulse OUTPUT_EDGE_N verilog_node "`TCU.spc3_trigger_pulse";
1146 output spc4_trigger_pulse OUTPUT_EDGE_N verilog_node "`TCU.spc4_trigger_pulse";
1147 output spc5_trigger_pulse OUTPUT_EDGE_N verilog_node "`TCU.spc5_trigger_pulse";
1148 output spc6_trigger_pulse OUTPUT_EDGE_N verilog_node "`TCU.spc6_trigger_pulse";
1149 output spc7_trigger_pulse OUTPUT_EDGE_N verilog_node "`TCU.spc7_trigger_pulse";
1150}
1151
1152//// CLOCK is required in some global testbench files (ie: std_display_class.vr).
1153//// Deleting this causes the simulation to hang in std_display_class on all dispmon calls with the MON_ERR parameter
1154//// CLOCK below has no other purpose than this in the TCU testbench.
1155//// verilog_node CLOCK "`TOP.tck";
1156
1157interface stci {
1158 input TCK CLOCK verilog_node "`CPU.TCK";
1159 input [1:0] tcu_stcicfg INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_stcicfg";
1160 input tcu_stcid INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_stcid";
1161 input STCIQ INPUT_EDGE INPUT_SKEW verilog_node "`TOP.cpu.STCIQ";
1162#ifdef TCU_GATE
1163 input update_dr_state INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl__n2408";
1164 input capture_dr_state INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl__N2870";
1165 input shift_dr_state INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl__tcu_jtag_tap_ctl_N55";
1166#else
1167 input update_dr_state INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl.update_dr_state";
1168 input capture_dr_state INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl.capture_dr_state";
1169 input shift_dr_state INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl.shift_dr_state";
1170#endif
1171#ifndef TCU_GATE
1172 input clockdr INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl.clockdr";
1173#endif
1174 inout tcu_stciclk OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_stciclk";
1175 inout io_tdi OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.io_tdi";
1176 inout stciq_tcu OUTPUT_EDGE_N INPUT_EDGE INPUT_SKEW verilog_node "`TCU.stciq_tcu";
1177 output STCICLK OUTPUT_EDGE_N verilog_node "`TOP.cpu.STCICLK";
1178 output[1:0] STCICFG OUTPUT_EDGE_N verilog_node "`TOP.cpu.STCICFG";
1179 output STCID OUTPUT_EDGE_N verilog_node "`TOP.cpu.STCID";
1180#ifdef TCU_GATE
1181 input stci_acc_mode INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl__n2620";
1182 input [3:0] tap_state INPUT_EDGE INPUT_SKEW verilog_node "{`TCU.jtag_ctl__tcu_jtag_tap_ctl_tap_state_l_3_,`TCU.jtag_ctl__tcu_jtag_tap_ctl_tap_state_l_2_,`TCU.jtag_ctl__tcu_jtag_tap_ctl_tap_state_l_1_,`TCU.jtag_ctl__tcu_jtag_tap_ctl_tap_state_l_0_}";
1183#else
1184 input stci_acc_mode INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl.stci_acc_mode";
1185 input [3:0] tap_state INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl.tap_state";
1186#endif
1187 output signal_to_disable_checker OUTPUT_EDGE_N verilog_node "`TOP.signal_to_disable_checker";
1188
1189}
1190
1191interface ncu_sck {
1192#ifdef NCU_GATE
1193 input [17:0]sck_cnt INPUT_EDGE INPUT_SKEW verilog_node "{`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_17_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_16_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_15_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_14_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_13_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_12_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_11_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_10_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_9_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_8_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_7_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_6_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_5_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_4_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_3_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_2_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_1_,`NCU.ncu_ssitop_ctl__ncu_ssisif_ctl_sck_cnt_0_ }" ;
1194#else
1195 input [17:0]sck_cnt INPUT_EDGE INPUT_SKEW verilog_node "`NCU.ncu_ssitop_ctl.ncu_ssisif_ctl.sck_cnt" ;
1196#endif
1197}
1198
1199interface jt_sy_clk {
1200 input jt_scan_aclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jt_scan_aclk" ;
1201 input jt_scan_bclk INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jt_scan_bclk" ;
1202 input io_test_mode INPUT_EDGE INPUT_SKEW verilog_node "`TCU.io_test_mode" ;
1203#ifdef TCU_GATE
1204 input mtaccess INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl__mtaccess" ;
1205#else
1206 input mtaccess INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl.mtaccess" ;
1207#endif
1208#ifndef TCU_GATE
1209 input instr_ser_scan INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jtag_ctl.instr_ser_scan";
1210#endif
1211 input jt_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.jt_scan_en";
1212#ifdef TCU_GATE
1213 input tcu_asic_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_asic_array_wr_inhibit";
1214 input tcu_spc0_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc0_array_wr_inhibit";
1215 input tcu_spc1_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc1_array_wr_inhibit";
1216 input tcu_spc2_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc2_array_wr_inhibit";
1217 input tcu_spc3_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc3_array_wr_inhibit";
1218 input tcu_spc4_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc4_array_wr_inhibit";
1219 input tcu_spc5_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc5_array_wr_inhibit";
1220 input tcu_spc6_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc6_array_wr_inhibit";
1221 input tcu_spc7_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc7_array_wr_inhibit";
1222#else
1223 input tcu_asic_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.tcu_asic_array_wr_inhibit";
1224 input tcu_spc0_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.tcu_spc0_array_wr_inhibit";
1225 input tcu_spc1_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.tcu_spc1_array_wr_inhibit";
1226 input tcu_spc2_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.tcu_spc2_array_wr_inhibit";
1227 input tcu_spc3_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.tcu_spc3_array_wr_inhibit";
1228 input tcu_spc4_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.tcu_spc4_array_wr_inhibit";
1229 input tcu_spc5_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.tcu_spc5_array_wr_inhibit";
1230 input tcu_spc6_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.tcu_spc6_array_wr_inhibit";
1231 input tcu_spc7_array_wr_inhibit INPUT_EDGE INPUT_SKEW verilog_node "`TCU.sigmux_ctl.tcu_spc7_array_wr_inhibit";
1232#endif
1233
1234}
1235
1236
1237interface sys {
1238 input SYSCLK CLOCK verilog_node "`TOP.SYSCLK";
1239}
1240
1241interface cmp {
1242 input CMP CLOCK verilog_node "`TOP.cpu.l2clk";
1243}
1244
1245#endif
Full OpenSPARC design & verification tarball including full HDL.