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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: amb_top.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module amb_top ( ps , // Primary Southbound | |
36 | ps_bar, // Primary Southbound Complement | |
37 | sn , // Secondary Northbound | |
38 | sn_bar, // Secondary Northbound Complement | |
39 | pn, // Primary Northbound | |
40 | pn_bar, // Primary Northbound Complement | |
41 | ss , // Secondary Southbound | |
42 | ss_bar , // Secondary Southbound Complement | |
43 | link_clk, // Link Clock | |
44 | link_clk_bar, // Link clock complement | |
45 | reset, // Reset | |
46 | frm_boundary, // Frame Boundary Signal | |
47 | command_in, | |
48 | command_rdy, | |
49 | command_type, | |
50 | data_in, // Dram data in | |
51 | data_out, // Dram data out | |
52 | get_wbuffer_data, // Get write buffer data signal | |
53 | put_rbuffer_data, // Put read buffer data signal | |
54 | dcalcsr, | |
55 | dcaladdr, | |
56 | clear_dcalcsr31, | |
57 | drc, | |
58 | dram_clk, | |
59 | dram_2x_clk, | |
60 | frm_start, | |
61 | ref_2x_clk, | |
62 | sclk, // system clock | |
63 | clk_int, // Internal clock | |
64 | dram_cmd_vld_delayed, | |
65 | ddrio_nbencode_rd, | |
66 | cke_reg_delayed, | |
67 | sb_crc_error, | |
68 | ch_state | |
69 | ); // system interface | |
70 | ||
71 | // Module parameters | |
72 | parameter NB_LINK = 14; | |
73 | parameter SB_LINK = 10; | |
74 | parameter DS = 0; | |
75 | ||
76 | // Interface signals | |
77 | output [NB_LINK-1:0] pn,pn_bar; // primary northbound | |
78 | input [NB_LINK-1:0] sn,sn_bar; // secondary southbound | |
79 | output [SB_LINK-1:0] ss,ss_bar; // secondary southbound | |
80 | input [SB_LINK-1:0] ps,ps_bar; // primary southbound | |
81 | output sb_crc_error; | |
82 | ||
83 | input link_clk; | |
84 | input sclk; | |
85 | input link_clk_bar; | |
86 | input reset; | |
87 | input clear_dcalcsr31; | |
88 | input ref_2x_clk; | |
89 | input clk_int; | |
90 | output [3:0] ch_state; | |
91 | output frm_boundary; | |
92 | output [23:0] command_in; | |
93 | output command_rdy; | |
94 | output [1:0] command_type; | |
95 | output [71:0] data_in; | |
96 | input [71:0] data_out; | |
97 | input get_wbuffer_data; | |
98 | input ddrio_nbencode_rd; | |
99 | input put_rbuffer_data; | |
100 | inout [31:0] dcalcsr,dcaladdr,drc; | |
101 | input dram_clk,dram_2x_clk; | |
102 | input dram_cmd_vld_delayed,cke_reg_delayed; | |
103 | output frm_start; | |
104 | ||
105 | //internal registers | |
106 | real time1,time2,dram_clk_period; | |
107 | real time1_2x,time2_2x,dram_2x_clk_period; | |
108 | wire rbuf_rd,rbuf_empty; | |
109 | wire [71:0] rbuf_rdata; | |
110 | wire init; | |
111 | wire frm_boundary_nb; | |
112 | wire [NB_LINK-1:0] init_pn,init_pn_bar; | |
113 | wire [NB_LINK-1:0] pn_crc_err; | |
114 | wire frm_begin; | |
115 | wire frm_begin_nb; | |
116 | wire sb_decode_clk; | |
117 | wire dtm_enabled; | |
118 | wire [NB_LINK-1:0] nb_encode_pn,nb_encode_pn_bar,pn_fsr; | |
119 | wire cfg_rd; | |
120 | wire [31:0] cfg_data; | |
121 | wire send_status_frm; | |
122 | wire [31:0] l0sdur_reg; | |
123 | wire [7:0] fbdreg_mtr; | |
124 | wire [31:0] recalibdur_reg,fbdreg_dareftc,fbdreg_synctrainint; | |
125 | wire [23:0] sync_cmd; | |
126 | wire disable_state; | |
127 | wire init_seq_started; | |
128 | wire [31:0] dcalcsr,dcaladdr,drc; | |
129 | wire [7:0] fbds0,fbds1,fbds2,fbds3; | |
130 | wire [7:0] fbdreg_curr_cmd_to_data,fbdreg_curr_cmd_to_data_inc; | |
131 | wire [7:0] fbdreg_next_cmd_to_data,fbdreg_next_cmd_to_data_inc; | |
132 | wire [3:0] nb_config,sb_config; | |
133 | wire [31:0] fbdreg_emask,fbdreg_ferr,fbdreg_nerr; | |
134 | wire write_fifo_empty; | |
135 | wire enter_los,enter_recalibrate; | |
136 | wire soft_channel_reset; | |
137 | wire dtm_tr_complete; | |
138 | wire nop_frame_detected; | |
139 | wire [9:0] ps0_out,ps1_out,ps2_out,ps3_out,ps4_out,ps5_out,ps6_out,ps7_out,ps8_out,ps9_out,ps10_out,ps11_out; | |
140 | wire [9:0] ps0_out_bar,ps1_out_bar,ps2_out_bar; | |
141 | wire [13:0] pn_out; | |
142 | wire [13:0] pn0_fsr,pn1_fsr,pn2_fsr,pn3_fsr,pn4_fsr,pn5_fsr,pn6_fsr,pn7_fsr,pn8_fsr,pn9_fsr; | |
143 | wire [13:0] pn0,pn1,pn2,pn3,pn4,pn5,pn6,pn7,pn8,pn9,pn10,pn11; | |
144 | wire [13:0] init_pn0,init_pn1,init_pn2,init_pn3,init_pn4,init_pn5,init_pn6,init_pn7,init_pn8,init_pn9,init_pn10,init_pn11; | |
145 | wire serdes_data_rdy; | |
146 | ||
147 | ||
148 | `ifdef FBDIMM_FAST_NB | |
149 | assign pn = pn_fsr ; | |
150 | assign pn_bar = ~pn_fsr; | |
151 | `else | |
152 | ||
153 | assign pn = init ? pn_fsr : nb_encode_pn ; | |
154 | assign pn_bar = (init & (disable_state ) & !dtm_enabled) ? pn_fsr : | |
155 | (init & (!disable_state) & !dtm_enabled ) ? ~pn_fsr : | |
156 | (init & !dtm_tr_complete & dtm_enabled ) ? ~pn_fsr : | |
157 | nb_encode_pn_bar; | |
158 | `endif | |
159 | ||
160 | // SouthBound Decoder and CRC checker | |
161 | sb_decode_crc #(SB_LINK,DS) sb_decoder ( .ps_in (ps) , | |
162 | .ps_bar_in (ps_bar), | |
163 | .ss (ss), | |
164 | .ss_bar (ss_bar), | |
165 | .rbuffer_rd_data (rbuf_rdata), | |
166 | .rbuffer_rd (rbuf_rd), | |
167 | .rbuffer_empty (rbuf_empty), | |
168 | .config_reg_rd (cfg_rd), | |
169 | .config_reg_data (cfg_data), | |
170 | .send_status_frm (send_status_frm), | |
171 | .sync_cmd (sync_cmd), | |
172 | .fbdreg_dcalcsr (dcalcsr), | |
173 | .clear_dcalcsr31 (clear_dcalcsr31), | |
174 | .fbdreg_dcaladdr (dcaladdr), | |
175 | .fbdreg_drc (drc), | |
176 | .fbdreg_dareftc (fbdreg_dareftc), | |
177 | .fbdreg_synctrainint (fbdreg_synctrainint), | |
178 | .fbdreg_mtr (fbdreg_mtr), | |
179 | .fbdreg_curr_cmd_to_data (fbdreg_curr_cmd_to_data), | |
180 | .fbdreg_curr_cmd_to_data_inc (fbdreg_curr_cmd_to_data_inc), | |
181 | .fbdreg_next_cmd_to_data (fbdreg_next_cmd_to_data), | |
182 | .fbdreg_next_cmd_to_data_inc (fbdreg_next_cmd_to_data_inc), | |
183 | .fbds0 (fbds0), | |
184 | .fbds1 (fbds1), | |
185 | .fbds2 (fbds2), | |
186 | .fbds3 (fbds3), | |
187 | .fbdreg_emask (fbdreg_emask), | |
188 | .fbdreg_ferr (fbdreg_ferr), | |
189 | .fbdreg_nerr (fbdreg_nerr), | |
190 | `ifdef AXIS_FBDIMM_NO_FSR | |
191 | `else | |
192 | .link_clk (link_clk ), | |
193 | .link_clk_bar (link_clk_bar), | |
194 | `endif | |
195 | .dram_clk (dram_clk), | |
196 | .dram_2x_clk (dram_2x_clk), | |
197 | .write_fifo_empty (write_fifo_empty), | |
198 | .soft_channel_reset (soft_channel_reset), | |
199 | .sb_crc_error (sb_crc_error ), | |
200 | .nop_frame_detected ( nop_frame_detected ), | |
201 | .ref_2x_clk (ref_2x_clk), | |
202 | .sb_config (sb_config), | |
203 | .command_in (command_in), | |
204 | .command_rdy (command_rdy), | |
205 | .command_type (command_type), | |
206 | .frm_boundary (frm_boundary), | |
207 | .data_in (data_in), | |
208 | .data_out (data_out), | |
209 | .reset (reset), | |
210 | .get_wbuffer_data (get_wbuffer_data), | |
211 | .put_rbuffer_data (put_rbuffer_data), | |
212 | .init (init), | |
213 | .l0sdur_reg (l0sdur_reg), | |
214 | .recalibdur_reg (recalibdur_reg), | |
215 | .dram_cmd_vld_delayed (dram_cmd_vld_delayed), | |
216 | .cke_reg_delayed (cke_reg_delayed), | |
217 | .enter_recalibrate (enter_recalibrate), | |
218 | .enter_los (enter_los), | |
219 | .clk_int (sb_decode_clk), | |
220 | .frm_begin (frm_begin), | |
221 | .ps0_in (ps0_out), | |
222 | .ps1_in (ps1_out), | |
223 | .ps2_in (ps2_out), | |
224 | .ps3_in (ps3_out), | |
225 | .ps4_in (ps4_out), | |
226 | .ps5_in (ps5_out), | |
227 | .ps6_in (ps6_out), | |
228 | .ps7_in (ps7_out), | |
229 | .ps8_in (ps8_out), | |
230 | .ps9_in (ps9_out), | |
231 | .ps10_in (ps10_out), | |
232 | .ps11_in (ps11_out) | |
233 | ||
234 | ); | |
235 | ||
236 | // NorthBound Encoder and CRC generator | |
237 | nb_encode_crc #(NB_LINK,DS) nb_encoder ( .pn_shft_map_out (nb_encode_pn) , | |
238 | .pn_bar_map_out (nb_encode_pn_bar), | |
239 | .sn_in (sn), | |
240 | .sn_bar_in (sn_bar), | |
241 | .rbuffer_rd_data_in (rbuf_rdata), | |
242 | .rbuffer_rd_out (rbuf_rd), | |
243 | .config_reg_rd (cfg_rd), | |
244 | .config_reg_data (cfg_data), | |
245 | .send_status_frm (send_status_frm), | |
246 | .sync_cmd (sync_cmd), | |
247 | .frm_begin (frm_begin ), | |
248 | .frm_boundary (frm_boundary_nb), | |
249 | .frm_boundary_sb (frm_boundary), | |
250 | .drc (drc), | |
251 | .fbds0 (fbds0), | |
252 | .fbds1 (fbds1), | |
253 | .fbds2 (fbds2), | |
254 | .fbds3 (fbds3), | |
255 | .rbuffer_empty (rbuf_empty), | |
256 | .fbdreg_mtr (fbdreg_mtr), | |
257 | .reset (reset), | |
258 | .disable_state (disable_state), | |
259 | .dram_clk (dram_clk), | |
260 | .dram_2x_clk (dram_2x_clk), | |
261 | .ddrio_nbencode_rd (ddrio_nbencode_rd ), | |
262 | .clk_int (sb_decode_clk), | |
263 | `ifdef AXIS_FBDIMM_NO_FSR | |
264 | `else | |
265 | .link_clk (link_clk), | |
266 | .link_clk_bar (link_clk_bar), | |
267 | `endif | |
268 | .fbdreg_curr_cmd_to_data (fbdreg_curr_cmd_to_data), | |
269 | .fbdreg_curr_cmd_to_data_inc (fbdreg_curr_cmd_to_data_inc), | |
270 | .fbdreg_next_cmd_to_data (fbdreg_next_cmd_to_data), | |
271 | .fbdreg_next_cmd_to_data_inc (fbdreg_next_cmd_to_data_inc), | |
272 | .soft_channel_reset ( soft_channel_reset), | |
273 | .send_alert_frame_in ( sb_crc_error ), | |
274 | .nb_config (nb_config), | |
275 | .init (init), | |
276 | .ref_clk (sclk), | |
277 | .pn0_out (pn0), | |
278 | .pn1_out (pn1), | |
279 | .pn2_out (pn2), | |
280 | .pn3_out (pn3), | |
281 | .pn4_out (pn4), | |
282 | .pn5_out (pn5), | |
283 | .pn6_out (pn6), | |
284 | .pn7_out (pn7), | |
285 | .pn8_out (pn8), | |
286 | .pn9_out (pn9), | |
287 | .pn10_out (pn10), | |
288 | .pn11_out (pn11), | |
289 | .electrical_idle ( ps == ps_bar), | |
290 | .serdes_data_rdy (serdes_data_rdy), | |
291 | .sb_crc_error (sb_crc_error) | |
292 | ); | |
293 | ||
294 | ||
295 | reg sequence_start; | |
296 | `ifdef DTM_ENABLED | |
297 | initial sequence_start=1'b1; | |
298 | `else | |
299 | initial sequence_start=1'b0; | |
300 | ||
301 | always@(posedge frm_boundary) | |
302 | sequence_start <= 1'b1; | |
303 | ||
304 | `endif | |
305 | ||
306 | amb_init #(NB_LINK,SB_LINK,DS) ambinit (.init ( init), | |
307 | .ps ( ps), | |
308 | .ps0_in ( ps0_out), | |
309 | .ps0_in_bar ( ps0_out_bar), | |
310 | .ps1_in ( ps1_out), | |
311 | .ps2_in ( ps2_out), | |
312 | .ps3_in ( ps3_out), | |
313 | .ps4_in ( ps4_out), | |
314 | .ps5_in ( ps5_out), | |
315 | .ps6_in ( ps6_out), | |
316 | .ps7_in ( ps7_out), | |
317 | .ps8_in ( ps8_out), | |
318 | .ps9_in ( ps9_out), | |
319 | .ps10_in ( ps10_out), | |
320 | .ps11_in ( ps11_out), | |
321 | .pn0_out ( init_pn0), | |
322 | .pn1_out ( init_pn1), | |
323 | .pn2_out ( init_pn2), | |
324 | .pn3_out ( init_pn3), | |
325 | .pn4_out ( init_pn4), | |
326 | .pn5_out ( init_pn5), | |
327 | .pn6_out ( init_pn6), | |
328 | .pn7_out ( init_pn7), | |
329 | .pn8_out ( init_pn8), | |
330 | .pn9_out ( init_pn9), | |
331 | .pn10_out ( init_pn10), | |
332 | .pn11_out ( init_pn11), | |
333 | `ifdef DTM_ENABLED | |
334 | .clk_int ( !sequence_start ? clk_int: sb_decode_clk ), | |
335 | `else | |
336 | .clk_int ( !init_seq_started ? clk_int: sb_decode_clk ), | |
337 | `endif | |
338 | .ps_bar ( ps_bar), | |
339 | .pn ( init_pn), | |
340 | .pn_bar ( init_pn_bar), | |
341 | .drc ( drc), | |
342 | .frm_start ( frm_start), | |
343 | .link_clk ( link_clk), | |
344 | .sclk ( sclk), | |
345 | .dram_clk ( dram_clk), | |
346 | .ch_state ( ch_state), | |
347 | .disable_state ( disable_state), | |
348 | .enter_recalibrate ( enter_recalibrate), | |
349 | .enter_los ( enter_los), | |
350 | .dtm_tr_complete ( dtm_tr_complete), | |
351 | .frm_boundary_fast ( frm_boundary ), //& init_seq_started), | |
352 | .init_seq_started ( init_seq_started), | |
353 | .l0sdur_reg ( l0sdur_reg), | |
354 | .sb_config ( sb_config), | |
355 | .nb_config ( nb_config), | |
356 | .recalibdur_reg ( recalibdur_reg), | |
357 | .rst ( reset)); | |
358 | ||
359 | // SERDES BEHAVIORAL MODELS for FBDIMM | |
360 | ||
361 | fbdimm_sb_fsr fbdimm_sb_fsr(.ps_in (ps), | |
362 | .ps_in_bar (ps_bar), | |
363 | .frm_begin (frm_begin), | |
364 | .frm_begin_nb (frm_begin_nb), | |
365 | .reset (reset), | |
366 | .init_seq_started (init_seq_started), | |
367 | .ps0_out_bar ( ps0_out_bar), | |
368 | .ps0_out ( ps0_out), | |
369 | .ps1_out ( ps1_out), | |
370 | .ps1_out_bar ( ps1_out_bar), | |
371 | .ps2_out ( ps2_out), | |
372 | .ps2_out_bar ( ps2_out_bar), | |
373 | .ps3_out ( ps3_out), | |
374 | .ps4_out ( ps4_out), | |
375 | .ps5_out ( ps5_out), | |
376 | .ps6_out ( ps6_out), | |
377 | .ps7_out ( ps7_out), | |
378 | .ps8_out ( ps8_out), | |
379 | .ps9_out ( ps9_out), | |
380 | .ps10_out ( ps10_out), | |
381 | .ps11_out ( ps11_out), | |
382 | .link_clk ( link_clk), | |
383 | .dtm_tr_complete ( dtm_tr_complete), | |
384 | .dtm_enabled_out ( dtm_enabled), | |
385 | .nop_frame_detected ( nop_frame_detected ), | |
386 | .ref_clk ( frm_boundary), | |
387 | .frm_boundary_nb ( frm_boundary_nb), | |
388 | .sb_decode_clk ( sb_decode_clk)); | |
389 | ||
390 | ||
391 | ||
392 | fbdimm_nb_fsr #(DS) fbdimm_nb_fsr( .reset (reset), | |
393 | .pn0_in ( !init ? pn0 : init_pn0 ), | |
394 | .pn1_in ( !init ? pn1 : init_pn1), | |
395 | .pn2_in ( !init ? pn2 : init_pn2), | |
396 | .pn3_in ( !init ? pn3 : init_pn3), | |
397 | .pn4_in ( !init ? pn4 : init_pn4), | |
398 | .pn5_in ( !init ? pn5 : init_pn5), | |
399 | .pn6_in ( !init ? pn6 : init_pn6), | |
400 | .pn7_in ( !init ? pn7 : init_pn7), | |
401 | .pn8_in ( !init ? pn8 : init_pn8), | |
402 | .pn9_in ( !init ? pn9 : init_pn9), | |
403 | .pn10_in ( !init ? pn10 : init_pn10), | |
404 | .pn11_in ( !init ? pn11 : init_pn11), | |
405 | .pn_out ( pn_fsr), | |
406 | .link_clk (link_clk), | |
407 | .serdes_data_rdy (serdes_data_rdy), | |
408 | .ref_clk (frm_boundary)); | |
409 | ||
410 | ||
411 | ||
412 | endmodule |