Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ddr_io.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifdef STINGRAY | |
36 | `timescale 1ns/1ps | |
37 | `endif // STINGRAY | |
38 | ||
39 | module ddr_io ( | |
40 | `ifdef AXIS_FBDIMM_NO_FSR | |
41 | `else | |
42 | link_clk, // link clock | |
43 | `endif // AXIS_FBDIMM_NO_FSR | |
44 | dram_clk, // dram clock | |
45 | dram_2x_clk, // 2x dram clock | |
46 | clk_int, //internal clock | |
47 | command_in, // 24bit command register | |
48 | command_rdy, // command ready signal | |
49 | command_type, // A. B or C | |
50 | data_in, // dram data IN | |
51 | data_out, // dram data OUT | |
52 | reset, // reset | |
53 | dcalcsr, // fbdimm register | |
54 | clear_dcalcsr31, // to clear bit 31 | |
55 | dcaladdr, // fbdimm register | |
56 | drc, // fbdimm register | |
57 | frm_boundary, // frame boundary signal | |
58 | get_wbuffer_data, // get write buffer data | |
59 | put_rbuffer_data, // put read buffer data | |
60 | init, // initialization signal | |
61 | cke_rank0, // dram IO | |
62 | cke_rank1, // dram IO | |
63 | bcs, // dram IO | |
64 | bras, // dram IO | |
65 | bcas, // dram IO | |
66 | bwe, // dram IO | |
67 | ba, // dram IO | |
68 | addr, // dram IO | |
69 | dq, // dram IO | |
70 | dqs, // dram IO | |
71 | bdqs, // dram IO | |
72 | dm_rdqs, // dram IO | |
73 | brdqs, // dram IO | |
74 | odt, // dram IO | |
75 | areset, // dram IO | |
76 | term, // dram IO | |
77 | rs, // dram IO | |
78 | dqs_in, // dram IO | |
79 | ddrio_nbencode_rd, | |
80 | drams_on_out, // special signal | |
81 | sb_crc_error, | |
82 | ch_state | |
83 | ); | |
84 | // parameters | |
85 | parameter DS=0; | |
86 | ||
87 | // dram interface | |
88 | output [18:0] cke_rank0,cke_rank1,bcs,bras,bcas,bwe,dqs,bdqs,dm_rdqs,brdqs,odt,areset,term; | |
89 | output [2:0] ba; | |
90 | output [15:0] addr; | |
91 | inout [71:0] dq; | |
92 | output rs; | |
93 | output clear_dcalcsr31; | |
94 | input dqs_in; | |
95 | input clk_int; | |
96 | input [3:0] ch_state; | |
97 | input sb_crc_error; | |
98 | ||
99 | // Interface signals | |
100 | input frm_boundary; | |
101 | `ifdef AXIS_FBDIMM_NO_FSR | |
102 | `else | |
103 | input link_clk; | |
104 | `endif // AXIS_FBDIMM_NO_FSR | |
105 | input dram_clk; | |
106 | input dram_2x_clk; | |
107 | input [23:0] command_in; | |
108 | input command_rdy; | |
109 | input [1:0] command_type; | |
110 | input [71:0] data_in; | |
111 | output [71:0] data_out; | |
112 | output get_wbuffer_data; | |
113 | output put_rbuffer_data; | |
114 | input reset; | |
115 | input init; | |
116 | inout [31:0] dcalcsr,dcaladdr,drc; | |
117 | output drams_on_out; | |
118 | output ddrio_nbencode_rd; | |
119 | ||
120 | // Internal registers/wires | |
121 | reg dram_cmd_vld; | |
122 | wire [23:0] cmd_fifo_rd_data ; | |
123 | wire [23:0] cmd_fifo_rd_data_bc ; | |
124 | wire cmd_fifo_full; | |
125 | wire cmd_fifo_full_bc; | |
126 | wire cmd_fifo_empty; | |
127 | wire cmd_fifo_empty_bc; | |
128 | wire [23:0] command=cmd_fifo_rd_data; | |
129 | wire [23:0] command_bc=cmd_fifo_rd_data_bc; | |
130 | wire [23:0] write_cycle,read_cycle; | |
131 | reg write_cycle_start,read_cycle_start; | |
132 | wire dqs_cycle; | |
133 | reg dram_dqs_clk; | |
134 | wire dqs_driver = get_wbuffer_data & dram_dqs_clk ; | |
135 | reg drams_on; | |
136 | reg stall_pipe; | |
137 | reg [4:0] debug_level; | |
138 | reg dcalcsr_complete; | |
139 | reg [18:0] cke_rank0_reg,cke_rank1_reg,bcs_reg,bdqs_reg,bras_reg,bcas_reg,bwe_reg,dqs_reg; | |
140 | reg [18:0] dm_rdqs_reg,brdqs_reg,odt_reg,term_reg,areset_reg; | |
141 | reg [2:0] ba_reg; | |
142 | reg [15:0] addr_reg; | |
143 | reg RS,RS_pre; | |
144 | reg first_dram_cmd; | |
145 | reg sng_channel; | |
146 | reg [3:0] prev_ch_state; | |
147 | reg [4:0] self_refresh_fsm_state; | |
148 | reg issue_pre_all_cmd; | |
149 | reg issue_auto_refresh_cmd; | |
150 | reg issue_enter_self_refresh_cmd; | |
151 | reg issue_exit_self_refresh_cmd; | |
152 | reg [10:0] dram_clk_counter; | |
153 | reg dram_clk_counter_en; | |
154 | ||
155 | wire [18:0] bcs = bcs_reg; | |
156 | wire [18:0] bras = bras_reg; | |
157 | wire [18:0] bcas = bcas_reg; | |
158 | wire [18:0] bwe = bwe_reg; | |
159 | wire [18:0] dqs; | |
160 | wire [18:0] bdqs; | |
161 | wire [18:0] dm_rdqs = dm_rdqs_reg ; | |
162 | wire [18:0] brdqs = brdqs_reg; | |
163 | wire [18:0] odt = odt_reg; | |
164 | wire [18:0] term = term_reg; | |
165 | wire [2:0] ba = ba_reg; | |
166 | wire [15:0] addr = addr_reg; | |
167 | wire [18:0] areset= { 10 { init } }; | |
168 | wire dram_bl; | |
169 | wire cke_reg_1,cke_reg_delayed,dram_cmd_vld_1,dram_cmd_vld_delayed; | |
170 | wire [18:0] cke_rank0; | |
171 | wire [18:0] cke_rank1; | |
172 | reg write_command; | |
173 | wire write_cycle_shft; | |
174 | ||
175 | ||
176 | ||
177 | // assignments | |
178 | ||
179 | assign ddrio_nbencode_rd = read_cycle_start; | |
180 | assign cke_rank0 = cke_rank0_reg ; | |
181 | assign cke_rank1 = cke_rank1_reg; | |
182 | assign drams_on_out = drams_on; | |
183 | assign dram_bl = drc[8]; | |
184 | assign rs = issue_pre_all_cmd | issue_auto_refresh_cmd | issue_enter_self_refresh_cmd | issue_exit_self_refresh_cmd ? RS_pre : RS ; | |
185 | ||
186 | assign dqs[0]= (dqs_cycle) ? dqs_driver: 1'bz; | |
187 | assign dqs[1]= (dqs_cycle) ? dqs_driver: 1'bz; | |
188 | assign dqs[2]= (dqs_cycle) ? dqs_driver: 1'bz; | |
189 | assign dqs[3]= (dqs_cycle) ? dqs_driver: 1'bz; | |
190 | assign dqs[4]= (dqs_cycle) ? dqs_driver: 1'bz; | |
191 | assign dqs[5]= (dqs_cycle) ? dqs_driver: 1'bz; | |
192 | assign dqs[6]= (dqs_cycle) ? dqs_driver: 1'bz; | |
193 | assign dqs[7]= (dqs_cycle) ? dqs_driver: 1'bz; | |
194 | assign dqs[8]= (dqs_cycle) ? dqs_driver: 1'bz; | |
195 | assign dqs[9]= (dqs_cycle) ? dqs_driver: 1'bz; | |
196 | assign dqs[10]= (dqs_cycle) ? dqs_driver: 1'bz; | |
197 | assign dqs[11]= (dqs_cycle) ? dqs_driver: 1'bz; | |
198 | assign dqs[12]= (dqs_cycle) ? dqs_driver: 1'bz; | |
199 | assign dqs[13]= (dqs_cycle) ? dqs_driver: 1'bz; | |
200 | assign dqs[14]= (dqs_cycle) ? dqs_driver: 1'bz; | |
201 | assign dqs[15]= (dqs_cycle) ? dqs_driver: 1'bz; | |
202 | assign dqs[16]= (dqs_cycle) ? dqs_driver: 1'bz; | |
203 | assign dqs[17]= (dqs_cycle) ? dqs_driver: 1'bz; | |
204 | assign dqs[18]= (dqs_cycle) ? dqs_driver: 1'bz; | |
205 | ||
206 | assign bdqs[0] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
207 | assign bdqs[1] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
208 | assign bdqs[2] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
209 | assign bdqs[3] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
210 | assign bdqs[4] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
211 | assign bdqs[5] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
212 | assign bdqs[6] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
213 | assign bdqs[7] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
214 | assign bdqs[8] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
215 | assign bdqs[9] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
216 | assign bdqs[10] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
217 | assign bdqs[11] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
218 | assign bdqs[12] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
219 | assign bdqs[13] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
220 | assign bdqs[14] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
221 | assign bdqs[15] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
222 | assign bdqs[16] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
223 | assign bdqs[17] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
224 | assign bdqs[18] = ( dqs_cycle ) ? ~dqs_driver : 1'bz; | |
225 | ||
226 | ||
227 | assign clear_dcalcsr31 = dcalcsr_complete; | |
228 | ||
229 | ||
230 | // Create a race free clock for driving dqs signals | |
231 | always@(dram_clk) | |
232 | begin | |
233 | if ( dram_clk ) | |
234 | dram_dqs_clk <= #1 1; | |
235 | else | |
236 | dram_dqs_clk <= #1 0; | |
237 | end | |
238 | ||
239 | // Read/Write pipleline stages | |
240 | dff_p #(2) wc1( .signal_in ({write_cycle_start,read_cycle_start}), | |
241 | .signal_out ({write_cycle[1],read_cycle[1]}), | |
242 | .clk (dram_clk & drams_on )); | |
243 | dff_p #(2) wc2( .signal_in ({write_cycle[1],read_cycle[1]}), | |
244 | .signal_out ({write_cycle[2],read_cycle[2]}), | |
245 | .clk (dram_clk)); | |
246 | dff_p #(2) wc3( .signal_in ({write_cycle[2],read_cycle[2]}), | |
247 | .signal_out ({write_cycle[3],read_cycle[3]}), | |
248 | .clk (dram_clk)); | |
249 | dff_p #(2) wc4( .signal_in ({write_cycle[3],read_cycle[3]}), | |
250 | .signal_out ({write_cycle[4],read_cycle[4]}), | |
251 | .clk (dram_clk)); | |
252 | dff_p #(2) wc5( .signal_in ({write_cycle[4],read_cycle[4]}), | |
253 | .signal_out ({write_cycle[5],read_cycle[5]}), | |
254 | .clk (dram_clk)); | |
255 | dff_p #(2) wc6( .signal_in ({write_cycle[5],read_cycle[5]}), | |
256 | .signal_out ({write_cycle[6],read_cycle[6]}), | |
257 | .clk (dram_clk)); | |
258 | dff_p #(2) wc7( .signal_in ({write_cycle[6],read_cycle[6]}), | |
259 | .signal_out ({write_cycle[7],read_cycle[7]}), | |
260 | .clk (dram_clk)); | |
261 | dff_p #(2) wc8( .signal_in ({write_cycle[7],read_cycle[7]}), | |
262 | .signal_out ({write_cycle[8],read_cycle[8]}), | |
263 | .clk (dram_clk)); | |
264 | dff_p #(2) wc9( .signal_in ({write_cycle[8],read_cycle[8]}), | |
265 | .signal_out ({write_cycle[9],read_cycle[9]}), | |
266 | .clk (dram_clk)); | |
267 | dff_p #(2) wc10( .signal_in ({write_cycle[8],read_cycle[9]}), | |
268 | .signal_out ({write_cycle[9],read_cycle[10]}), | |
269 | .clk (dram_clk)); | |
270 | dff_p #(2) wc11( .signal_in ({write_cycle[8],read_cycle[10]}), | |
271 | .signal_out ({write_cycle[9],read_cycle[11]}), | |
272 | .clk (dram_clk)); | |
273 | dff_p #(2) wc12( .signal_in ({write_cycle[8],read_cycle[11]}), | |
274 | .signal_out ({write_cycle[9],read_cycle[12]}), | |
275 | .clk (dram_clk)); | |
276 | dff_p #(2) wc13( .signal_in ({write_cycle[8],read_cycle[12]}), | |
277 | .signal_out ({write_cycle[9],read_cycle[13]}), | |
278 | .clk (dram_clk)); | |
279 | dff_p #(2) wc14( .signal_in ({write_cycle[8],read_cycle[13]}), | |
280 | .signal_out ({write_cycle[9],read_cycle[14]}), | |
281 | .clk (dram_clk)); | |
282 | dff_p #(2) wc15( .signal_in ({write_cycle[8],read_cycle[14]}), | |
283 | .signal_out ({write_cycle[9],read_cycle[15]}), | |
284 | .clk (dram_clk)); | |
285 | dff_p #(2) wc16( .signal_in ({write_cycle[8],read_cycle[15]}), | |
286 | .signal_out ({write_cycle[9],read_cycle[16]}), | |
287 | .clk (dram_clk)); | |
288 | ||
289 | wire [9:0] delay_reg=((drc[7:4]+drc[3:0]))-10'h1; | |
290 | ||
291 | ||
292 | ||
293 | wire write_cycle_pre = (delay_reg[7:0] == 7'h5 ) ? write_cycle[5] : | |
294 | (delay_reg[7:0] == 7'h4 ) ? write_cycle[4] : | |
295 | (delay_reg[7:0] == 7'h3 ) ? write_cycle[3] : | |
296 | (delay_reg[7:0] == 7'h2 ) ? write_cycle[2] : 1'b0; | |
297 | ||
298 | wire write_cycle0 = (delay_reg[7:0] == 7'h5 ) ? write_cycle[6] : | |
299 | (delay_reg[7:0] == 7'h4 ) ? write_cycle[5] : | |
300 | (delay_reg[7:0] == 7'h3 ) ? write_cycle[4] : | |
301 | (delay_reg[7:0] == 7'h2 ) ? write_cycle[3] : 1'b0; | |
302 | ||
303 | wire write_cycle1 = (delay_reg[7:0] == 7'h5 ) ? write_cycle[7] : | |
304 | (delay_reg[7:0] == 7'h4 ) ? write_cycle[6] : | |
305 | (delay_reg[7:0] == 7'h3 ) ? write_cycle[5] : | |
306 | (delay_reg[7:0] == 7'h2 ) ? write_cycle[4] : 1'b0; | |
307 | ||
308 | wire write_cycle2 = (delay_reg[7:0] == 7'h5 ) ? write_cycle[8] : | |
309 | (delay_reg[7:0] == 7'h4 ) ? write_cycle[7] : | |
310 | (delay_reg[7:0] == 7'h3 ) ? write_cycle[6] : | |
311 | (delay_reg[7:0] == 7'h2 ) ? write_cycle[5] : 1'b0; | |
312 | ||
313 | wire write_cycle3 = (delay_reg[7:0] == 7'h5 ) ? write_cycle[9] : | |
314 | (delay_reg[7:0] == 7'h4 ) ? write_cycle[8] : | |
315 | (delay_reg[7:0] == 7'h3 ) ? write_cycle[7] : | |
316 | (delay_reg[7:0] == 7'h2 ) ? write_cycle[6] : 1'b0; | |
317 | ||
318 | // Signal to get data from write fifo | |
319 | assign get_wbuffer_data = ( write_cycle0 & dram_clk) | | |
320 | ( write_cycle0 & ~dram_clk) | | |
321 | ( write_cycle1 & dram_clk) | | |
322 | ( write_cycle1 & ~dram_clk) | | |
323 | ( write_cycle2 & dram_clk & ( sng_channel | dram_bl ) ) | | |
324 | ( write_cycle2 & ~dram_clk & ( sng_channel | dram_bl ) ) | | |
325 | ( write_cycle3 & dram_clk & ( sng_channel | dram_bl ) ) | | |
326 | ( write_cycle3 & ~dram_clk & ( sng_channel | dram_bl ) ) ; | |
327 | ||
328 | ||
329 | // Signal to put data into read fifo | |
330 | ||
331 | reg dqs_in_shft; | |
332 | reg prev_dqs_in; | |
333 | reg curr_dqs_in; | |
334 | reg [3:0] dqs_curr_state; | |
335 | reg put_rbuffer_data_alt; | |
336 | `ifdef AXIS_DDR2_MODEL | |
337 | wire axis_ddr2_dram_model; | |
338 | `else | |
339 | reg put_rbuffer_data; // RALI | |
340 | `endif // AXIS_DDR2_MODEL | |
341 | reg [71:0] dq_shft; | |
342 | reg dqs_prev_val; | |
343 | ||
344 | `ifdef AXIS_DDR2_MODEL | |
345 | assign put_rbuffer_data = put_rbuffer_data_alt; // RALI | |
346 | `endif // AXIS_DDR2_MODEL | |
347 | ||
348 | initial begin | |
349 | dqs_curr_state = 4'b0; | |
350 | first_dram_cmd=1'b0; | |
351 | `ifdef AXIS_DDR2_MODEL | |
352 | `else | |
353 | put_rbuffer_data=1'b0; //RALI | |
354 | `endif // AXIS_DDR2_MODEL | |
355 | end | |
356 | ||
357 | always@(posedge dram_cmd_vld) | |
358 | first_dram_cmd<=1'b1; | |
359 | ||
360 | `ifdef AXIS_DDR2_MODEL | |
361 | always@(negedge dram_2x_clk) //RALI | |
362 | `else | |
363 | always@(posedge dram_2x_clk) //RALI | |
364 | `endif // AXIS_DDR2_MODEL | |
365 | begin | |
366 | dq_shft <= dq; | |
367 | case(dqs_curr_state) | |
368 | 4'h0: begin | |
369 | dqs_prev_val<=dqs_in; | |
370 | if ( (dqs_in == 1 ) & !( get_wbuffer_data ) ) begin | |
371 | put_rbuffer_data_alt<=1; | |
372 | dqs_curr_state<=4'h1; | |
373 | end | |
374 | else | |
375 | put_rbuffer_data_alt<=0; | |
376 | end | |
377 | 4'h1: begin | |
378 | dqs_prev_val<=dqs_in; | |
379 | dqs_curr_state<=4'h2; | |
380 | end | |
381 | 4'h2: begin | |
382 | dqs_curr_state<=4'h3; | |
383 | end | |
384 | 4'h3: begin | |
385 | dqs_curr_state<=4'h4; | |
386 | end | |
387 | 4'h4: begin | |
388 | if ( dqs_in == 1 ) | |
389 | dqs_curr_state<=4'h1; | |
390 | else begin | |
391 | put_rbuffer_data_alt<=0; | |
392 | dqs_curr_state<=4'h0; | |
393 | end | |
394 | end | |
395 | 4'h5: begin | |
396 | dqs_curr_state<=4'h6; | |
397 | end | |
398 | 4'h6: begin | |
399 | dqs_curr_state<=4'h7; | |
400 | end | |
401 | 4'h7: begin | |
402 | dqs_curr_state<=4'h8; | |
403 | end | |
404 | 4'h8: begin | |
405 | put_rbuffer_data_alt<=0; | |
406 | dqs_curr_state<=4'h0; | |
407 | end | |
408 | ||
409 | endcase | |
410 | ||
411 | end | |
412 | ||
413 | always@(negedge dram_2x_clk) | |
414 | begin | |
415 | dqs_in_shft <= dqs_in; | |
416 | end | |
417 | ||
418 | assign dqs_cycle = ( write_cycle_pre & dram_clk ) | | |
419 | ( write_cycle_pre & ~dram_clk ) | | |
420 | ( write_cycle0 & dram_clk) | | |
421 | ( write_cycle0 & ~dram_clk) | | |
422 | ( write_cycle1 & dram_clk) | | |
423 | ( write_cycle1 & ~dram_clk) | | |
424 | ( write_cycle2 & dram_clk) | | |
425 | ( write_cycle2 & ~dram_clk & ( sng_channel | dram_bl ) ) | | |
426 | ( write_cycle3 & dram_clk & ( sng_channel | dram_bl ) ) | | |
427 | ( write_cycle3 & ~dram_clk & ( sng_channel | dram_bl ) ); | |
428 | ||
429 | ||
430 | wire [71:0] dq = get_wbuffer_data ? data_in : 72'bz; | |
431 | ||
432 | ||
433 | reg [71:0] dq_shift_half_cycle; | |
434 | ||
435 | initial begin | |
436 | dq_shift_half_cycle = 72'h0; //RALI | |
437 | if ( $test$plusargs("SNG_CHANNEL") ) | |
438 | sng_channel=1; | |
439 | else | |
440 | sng_channel=0; | |
441 | ||
442 | end | |
443 | ||
444 | ||
445 | `ifdef AXIS_DDR2_MODEL | |
446 | assign data_out = dq_shft; //RALI | |
447 | `else | |
448 | assign data_out = dq_shift_half_cycle; //RALI | |
449 | `endif // AXIS_DDR2_MODEL | |
450 | ||
451 | ||
452 | `ifdef AXIS_DDR2_MODEL | |
453 | always@(posedge dram_2x_clk) begin // RALI | |
454 | dq_shift_half_cycle <= dq_shft; | |
455 | end | |
456 | `else | |
457 | always@(negedge dram_2x_clk) begin // RALI | |
458 | dq_shift_half_cycle <= dq_shft; | |
459 | put_rbuffer_data <= put_rbuffer_data_alt; | |
460 | end | |
461 | ||
462 | `endif // AXIS_DDR2_MODEL | |
463 | ||
464 | // drive DQS and strobes | |
465 | always@(dram_clk or write_cycle0) | |
466 | begin | |
467 | if ( write_cycle0 ) | |
468 | begin | |
469 | `ifdef X8 | |
470 | dqs_reg[18:0] <= 19'h0; | |
471 | bdqs_reg[18:0] <= 19'h1ff; | |
472 | `else | |
473 | dqs_reg[18:0] <= 19'h0; | |
474 | bdqs_reg[18:0] <= 19'h7ffff; | |
475 | `endif | |
476 | ||
477 | end | |
478 | else begin | |
479 | if ( dram_clk ) begin | |
480 | `ifdef X8 | |
481 | dqs_reg[18:0] <= 19'h1ff; | |
482 | bdqs_reg[18:0] <= 19'h0; | |
483 | `else | |
484 | dqs_reg[18:0] <= 19'h7ffff; | |
485 | bdqs_reg[18:0] <= 19'h0; | |
486 | `endif | |
487 | ||
488 | end else begin | |
489 | `ifdef X8 | |
490 | dqs_reg[18:0] <= 19'h0; | |
491 | bdqs_reg[18:0] <= 19'h1ff; | |
492 | `else | |
493 | dqs_reg[18:0] <= 19'h0; | |
494 | bdqs_reg[18:0] <= 19'h7ffff; | |
495 | `endif | |
496 | end | |
497 | end | |
498 | end | |
499 | ||
500 | // Command decoder | |
501 | ||
502 | ||
503 | wire enter_self_refresh_fsm = (( ch_state == `AMB_INIT_DISABLE ) | ( ch_state == `AMB_INIT_TRAIN )) ; | |
504 | ||
505 | initial self_refresh_fsm_state = 1; | |
506 | ||
507 | always@(posedge dram_clk) if ( dram_clk_counter_en ) | |
508 | dram_clk_counter <= dram_clk_counter + 11'h1; | |
509 | else | |
510 | dram_clk_counter <= 11'h0; | |
511 | ||
512 | // taken from fbdimm spec oct 2004 | |
513 | always@(posedge dram_clk) if ( drams_on ) | |
514 | begin | |
515 | case ( self_refresh_fsm_state ) | |
516 | 5'h1: begin | |
517 | issue_pre_all_cmd <= 1'b0; | |
518 | issue_auto_refresh_cmd <= 1'b0; | |
519 | issue_enter_self_refresh_cmd <= 1'b0; | |
520 | issue_exit_self_refresh_cmd <= 1'b0; | |
521 | if (enter_self_refresh_fsm ) | |
522 | self_refresh_fsm_state <= 5'h2; | |
523 | //if ( ch_state == `AMB_INIT_TRAIN ) | |
524 | // self_refresh_fsm_state <= 5'h2; | |
525 | ||
526 | //`ifdef FBDIMM_ENABLE_SELF_REF_FSM | |
527 | `ifdef AXIS_FBDIMM_HW | |
528 | `else | |
529 | cke_rank0_reg[18:0] <= 19'h7ffff; | |
530 | cke_rank1_reg[18:0] <= 19'h7ffff; | |
531 | `endif | |
532 | end | |
533 | 5'h2: begin self_refresh_fsm_state <= 5'h3; end | |
534 | 5'h3: begin self_refresh_fsm_state <= 5'h4; end | |
535 | 5'h4: begin self_refresh_fsm_state <= 5'h5; end | |
536 | 5'h5: begin | |
537 | // self_refresh_fsm_state <= 5'h6; | |
538 | ||
539 | dram_clk_counter_en <=1'b1; | |
540 | ||
541 | if ( dram_clk_counter == 11'd30 ) begin | |
542 | self_refresh_fsm_state <= 5'h6; | |
543 | dram_clk_counter_en <= 1'b0; | |
544 | `ifdef AXIS_FBDIMM_HW | |
545 | `else | |
546 | cke_rank0_reg[18:0] <= 19'h7ffff; | |
547 | cke_rank1_reg[18:0] <= 19'h7ffff; | |
548 | `endif | |
549 | end | |
550 | ||
551 | end | |
552 | 5'h6: begin | |
553 | self_refresh_fsm_state <= 5'h7; | |
554 | issue_pre_all_cmd <= 1'b1; | |
555 | RS_pre<=0; | |
556 | end | |
557 | 5'h7: begin | |
558 | self_refresh_fsm_state <= 5'h8; | |
559 | `ifdef STACK_DIMM | |
560 | RS_pre<=1; | |
561 | `else | |
562 | issue_pre_all_cmd <= 1'b0; | |
563 | `endif | |
564 | end | |
565 | 5'h8: begin | |
566 | self_refresh_fsm_state <= 5'h9; | |
567 | `ifdef STACK_DIMM | |
568 | issue_pre_all_cmd <= 1'b0; | |
569 | `endif | |
570 | end | |
571 | 5'h9: begin | |
572 | RS_pre<=0; | |
573 | self_refresh_fsm_state <= 5'ha; | |
574 | end | |
575 | 5'ha: begin self_refresh_fsm_state <= 5'hb; end | |
576 | 5'hb: begin | |
577 | `ifdef FBDIMM_ENABLE_SELF_REF_FSM | |
578 | issue_auto_refresh_cmd <= 1'b1; | |
579 | self_refresh_fsm_state <= 5'hc; | |
580 | `else | |
581 | self_refresh_fsm_state <= 5'h16; | |
582 | `endif | |
583 | end | |
584 | 5'hc: begin | |
585 | ||
586 | `ifdef STACK_DIMM | |
587 | RS_pre<=1; | |
588 | `else | |
589 | issue_auto_refresh_cmd <= 1'b0; | |
590 | `endif | |
591 | self_refresh_fsm_state <= 5'hd; | |
592 | ||
593 | end | |
594 | 5'hd: begin | |
595 | `ifdef STACK_DIMM | |
596 | issue_auto_refresh_cmd <= 1'b0; | |
597 | `endif | |
598 | RS_pre<=0; | |
599 | ||
600 | ||
601 | dram_clk_counter_en <=1'b1; | |
602 | ||
603 | if ( dram_clk_counter == 11'd30 ) begin | |
604 | self_refresh_fsm_state <= 5'he; | |
605 | dram_clk_counter_en <= 1'b0; | |
606 | end | |
607 | ||
608 | end | |
609 | ||
610 | 5'he: begin | |
611 | `ifdef FBDIMM_ENABLE_SELF_REF_FSM | |
612 | issue_enter_self_refresh_cmd <= 1'b1; | |
613 | `endif | |
614 | self_refresh_fsm_state <= 5'hf; | |
615 | end | |
616 | 5'hf: begin | |
617 | ||
618 | `ifdef STACK_DIMM | |
619 | RS_pre<=1; | |
620 | `else | |
621 | issue_enter_self_refresh_cmd <= 1'b0; | |
622 | `endif | |
623 | ||
624 | self_refresh_fsm_state <= 5'h10; | |
625 | end | |
626 | 5'h10: begin | |
627 | issue_enter_self_refresh_cmd <= 1'b0; | |
628 | self_refresh_fsm_state <= 5'h11; | |
629 | end | |
630 | 5'h11: begin | |
631 | self_refresh_fsm_state <= 5'h12; | |
632 | end | |
633 | 5'h12: begin | |
634 | self_refresh_fsm_state <= 5'h13; | |
635 | end | |
636 | 5'h13: begin | |
637 | RS_pre<=1'b0; | |
638 | if ( ch_state == `AMB_INIT_TRAIN ) begin | |
639 | `ifdef FBDIMM_ENABLE_SELF_REF_FSM | |
640 | issue_exit_self_refresh_cmd <= 1'b1; | |
641 | `endif | |
642 | self_refresh_fsm_state <= 5'h14; | |
643 | end | |
644 | end | |
645 | 5'h14: begin | |
646 | RS_pre<=1'b1; | |
647 | self_refresh_fsm_state <= 5'h15; | |
648 | end | |
649 | 5'h15: begin | |
650 | issue_exit_self_refresh_cmd <= 1'b0; | |
651 | self_refresh_fsm_state <= 5'h16; | |
652 | end | |
653 | 5'h16: begin | |
654 | if ( ch_state == `AMB_INIT_LO ) | |
655 | self_refresh_fsm_state <= 5'h1; | |
656 | end | |
657 | endcase | |
658 | ||
659 | end | |
660 | else begin | |
661 | self_refresh_fsm_state <=1; | |
662 | issue_pre_all_cmd <= 1'b0; | |
663 | end | |
664 | ||
665 | always@(negedge dram_clk) | |
666 | begin | |
667 | ||
668 | ||
669 | // precharge all command | |
670 | if ( issue_pre_all_cmd ) | |
671 | begin | |
672 | dram_cmd_vld <= 1'b1; | |
673 | bcs_reg[18:0] <= 19'h0; | |
674 | bcas_reg[18:0] <= 19'h7ffff; | |
675 | bwe_reg[18:0] <= 19'h0; | |
676 | bras_reg[18:0] <= 19'h0; | |
677 | addr_reg[15:0] <= 16'h400; | |
678 | cke_rank0_reg[18:0] <= 19'h7ffff; | |
679 | cke_rank1_reg[18:0] <= 19'h7ffff; | |
680 | end | |
681 | else if ( issue_auto_refresh_cmd) begin | |
682 | dram_cmd_vld <= 1'b1; | |
683 | bcs_reg[18:0] <= 19'h0; | |
684 | bcas_reg[18:0] <= 19'h0; | |
685 | bwe_reg[18:0] <= 19'h7ffff; | |
686 | bras_reg[18:0] <= 19'h0; | |
687 | cke_rank0_reg[18:0] <= 19'h7ffff; | |
688 | cke_rank1_reg[18:0] <= 19'h7ffff; | |
689 | end | |
690 | else if ( issue_enter_self_refresh_cmd ) begin | |
691 | dram_cmd_vld <= 1'b1; | |
692 | bcs_reg[18:0] <= 19'h0; | |
693 | bcas_reg[18:0] <= 19'h0; | |
694 | bras_reg[18:0] <= 19'h0; | |
695 | bwe_reg[18:0] <= 19'h7ffff; | |
696 | end | |
697 | else if ( issue_exit_self_refresh_cmd ) begin | |
698 | dram_cmd_vld <= 1'b1; | |
699 | bcs_reg[18:0] <= 19'h0; | |
700 | bcas_reg[18:0] <= 19'h7ffff; | |
701 | bras_reg[18:0] <= 19'h7ffff; | |
702 | bwe_reg[18:0] <= 19'h7ffff; | |
703 | ||
704 | end | |
705 | else if ( drams_on ) begin | |
706 | bcs_reg[18:0] <= 18'h0; | |
707 | bcas_reg[18:0] <= 19'h7ffff; | |
708 | bwe_reg[18:0] <= 19'h7ffff; | |
709 | bras_reg[18:0] <= 19'h7ffff; | |
710 | odt_reg[18:0] <= 18'h0; | |
711 | write_cycle_start <= 1'b0; | |
712 | read_cycle_start <= 1'b0; | |
713 | dram_cmd_vld <= 1'b0; | |
714 | write_command<=0; | |
715 | end | |
716 | ||
717 | ||
718 | ||
719 | if ( drams_on ) begin | |
720 | ||
721 | ||
722 | if ( !cmd_fifo_empty & !sb_crc_error ) begin | |
723 | ||
724 | if ( command[23:0] == 24'h0 ) // NOP | |
725 | begin | |
726 | bcs_reg[18:0] <= 19'h0; | |
727 | bcas_reg[18:0] <= 19'h7ffff; | |
728 | bwe_reg[18:0] <= 19'h7ffff; | |
729 | bras_reg[18:0] <= 19'h7ffff; | |
730 | end | |
731 | ||
732 | if ( command[23:0] != 24'h0 ) // command is not a NOP | |
733 | begin | |
734 | // all commands have the Rank Select bit at the same position | |
735 | RS<=command[17]; | |
736 | ||
737 | // write command | |
738 | `ifdef AXIS_FBDIMM_1AMB | |
739 | if (( command[20:18] == 3'b011 ) ) | |
740 | `else | |
741 | if (( command[20:18] == 3'b011 ) && ( command[23:21] == DS ) ) | |
742 | `endif // AXIS_FBDIMM_1AMB | |
743 | begin | |
744 | stall_pipe <= 1'b0; | |
745 | dram_cmd_vld <= 1'b1; | |
746 | bcs_reg[18:0] <= 19'h0; | |
747 | bcas_reg[18:0] <= 19'h0; | |
748 | bwe_reg[18:0] <= 19'h0; | |
749 | bras_reg[18:0] <= 19'h7ffff; | |
750 | dm_rdqs_reg[18:0] <= 0; | |
751 | ba_reg[2:0] <= command[15:13]; | |
752 | // For read/write, in 2GB(512MB X 4) config: | |
753 | // we use a11-a0 | |
754 | addr_reg[15:0] <= {4'h0,command[11:0]}; | |
755 | //addr_reg[15:0] <= {4'h0,command[11],command[9:0]}; | |
756 | ||
757 | write_cycle_start <= 1'b1; | |
758 | `ifdef AXIS_FBDIMM_HW | |
759 | `else | |
760 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Write command sent to DRAM - Address = %h BA=%h DS=%h RS=%h\n",addr_reg,ba_reg,command[23:21],RS); | |
761 | `endif // AXIS_FBDIMM_HW | |
762 | ||
763 | end // write command | |
764 | ||
765 | // Read command | |
766 | `ifdef AXIS_FBDIMM_1AMB | |
767 | if (( command[20:18] == 3'b010 ) ) | |
768 | `else | |
769 | if (( command[20:18] == 3'b010 ) && ( command[23:21] == DS ) ) | |
770 | `endif // AXIS_FBDIMM_1AMB | |
771 | begin | |
772 | read_cycle_start <= 1'b1; | |
773 | dram_cmd_vld <= 1'b1; | |
774 | bcs_reg[18:0] <= 19'h0; | |
775 | bcas_reg[18:0] <= 19'h0; | |
776 | bwe_reg[18:0] <= 19'h7ffff; | |
777 | bras_reg[18:0] <= 19'h7ffff; | |
778 | ba_reg[2:0] <= command[15:13]; | |
779 | ||
780 | // For read/write, in 2GB(512MB X 4) config: | |
781 | // we use a11-a0 | |
782 | addr_reg[15:0] <= {4'h0,command[11:0]}; | |
783 | ||
784 | end | |
785 | // Read command | |
786 | ||
787 | // precharge all command | |
788 | `ifdef AXIS_FBDIMM_1AMB | |
789 | if (( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b111) ) || issue_pre_all_cmd ) | |
790 | `else | |
791 | if (( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b111) && ( command[23:21] == DS )) || issue_pre_all_cmd ) | |
792 | `endif // AXIS_FBDIMM_1AMB | |
793 | begin | |
794 | `ifdef AXIS_FBDIMM_HW | |
795 | `else | |
796 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Precharge All command sent to DRAM\n"); | |
797 | `endif // AXIS_FBDIMM_HW | |
798 | dram_cmd_vld <= 1'b1; | |
799 | bcs_reg[18:0] <= 19'h0; | |
800 | bcas_reg[18:0] <= 19'h7ffff; | |
801 | bwe_reg[18:0] <= 19'h0; | |
802 | bras_reg[18:0] <= 19'h0; | |
803 | addr_reg[10] <= 1'b1; | |
804 | end | |
805 | // precharge all command | |
806 | ||
807 | // precharge single command | |
808 | `ifdef AXIS_FBDIMM_1AMB | |
809 | if ( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b110)) | |
810 | `else | |
811 | if ( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b110) && ( command[23:21] == DS )) | |
812 | `endif // AXIS_FBDIMM_1AMB | |
813 | begin | |
814 | `ifdef AXIS_FBDIMM_HW | |
815 | `else | |
816 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Precharge Single command sent to DRAM bank = %h\n",command[16:13]); | |
817 | `endif // AXIS_FBDIMM_HW | |
818 | dram_cmd_vld <= 1'b1; | |
819 | bcs_reg[18:0] <= 19'h0; | |
820 | bcas_reg[18:0] <= 19'h7fff; | |
821 | bwe_reg[18:0] <= 19'h0; | |
822 | bras_reg[18:0] <= 19'h0; | |
823 | addr_reg[10] <= 1'b0; | |
824 | ba_reg[2:0] <= command[16:13]; | |
825 | end | |
826 | // precharge signle command | |
827 | ||
828 | // Auto refresh command | |
829 | `ifdef AXIS_FBDIMM_1AMB | |
830 | if ( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b101) ) | |
831 | `else | |
832 | if ( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b101) && ( command[23:21] == DS )) | |
833 | `endif // AXIS_FBDIMM_1AMB | |
834 | begin | |
835 | `ifdef AXIS_FBDIMM_HW | |
836 | `else | |
837 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: AutoRefresh command sent to DRAM\n"); | |
838 | `endif // AXIS_FBDIMM_HW | |
839 | dram_cmd_vld <= 1'b1; | |
840 | bcs_reg[18:0] <= 19'h0; | |
841 | bcas_reg[18:0] <= 19'h0; | |
842 | bwe_reg[18:0] <= 19'h7ffff; | |
843 | bras_reg[18:0] <= 19'h0; | |
844 | end | |
845 | // Auto Refresh command | |
846 | ||
847 | // Self refresh entry command | |
848 | `ifdef AXIS_FBDIMM_1AMB | |
849 | if ( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b100)) | |
850 | `else | |
851 | if ( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b100) && ( command[23:21] == DS )) | |
852 | `endif // AXIS_FBDIMM_1AMB | |
853 | begin | |
854 | `ifdef AXIS_FBDIMM_HW | |
855 | `else | |
856 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Self Refresh Entry command sent to DRAM\n"); | |
857 | `endif // AXIS_FBDIMM_HW | |
858 | dram_cmd_vld <= 1'b1; | |
859 | if ( command[17] ) | |
860 | cke_rank1_reg[18:0] <= 19'h0; | |
861 | else | |
862 | cke_rank0_reg[18:0] <= 19'h0; | |
863 | ||
864 | bcs_reg[18:0] <= 19'h0; | |
865 | bcas_reg[18:0] <= 19'h0; | |
866 | bras_reg[18:0] <= 19'h0; | |
867 | bwe_reg[18:0] <= 19'h7ffff; | |
868 | end | |
869 | // Self refresh entry command | |
870 | ||
871 | // Power Down entry command | |
872 | `ifdef AXIS_FBDIMM_1AMB | |
873 | if ( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b0-10) ) | |
874 | `else | |
875 | if ( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b0-10) && ( command[23:21] == DS )) | |
876 | `endif // AXIS_FBDIMM_1AMB | |
877 | begin | |
878 | `ifdef AXIS_FBDIMM_HW | |
879 | `else | |
880 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Power Down Entry command sent to DRAM\n"); | |
881 | `endif // AXIS_FBDIMM_HW | |
882 | dram_cmd_vld <= 1'b1; | |
883 | if ( command[17] ) | |
884 | cke_rank1_reg[18:0] <= 19'h0; | |
885 | else | |
886 | cke_rank0_reg[18:0] <= 19'h0; | |
887 | ||
888 | ||
889 | bcs_reg[18:0] <= 19'h0; | |
890 | bcas_reg[18:0] <= 19'h7ffff; | |
891 | bras_reg[18:0] <= 19'h7ffff; | |
892 | bwe_reg[18:0] <= 19'h7ffff; | |
893 | end | |
894 | // Power Down entry command | |
895 | ||
896 | // Self refresh exit / power down exit command | |
897 | `ifdef AXIS_FBDIMM_1AMB | |
898 | if ( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b011) ) | |
899 | `else | |
900 | if ( ( command[20:18] == 3'b001) && ( command[12:10] == 3'b011) && ( command[23:21] == DS )) | |
901 | `endif // AXIS_FBDIMM_1AMB | |
902 | begin | |
903 | `ifdef AXIS_FBDIMM_HW | |
904 | `else | |
905 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Self Refresh/Power Down Exit command sent to DRAM\n"); | |
906 | `endif // AXIS_FBDIMM_HW | |
907 | dram_cmd_vld <= 1'b1; | |
908 | ||
909 | if ( command[17] ) | |
910 | cke_rank1_reg[18:0] <= 19'h7ffff; | |
911 | else | |
912 | cke_rank0_reg[18:0] <= 19'h7ffff; | |
913 | ||
914 | bcs_reg[18:0] <= 19'h0; | |
915 | bcas_reg[18:0] <= 19'h7ffff; | |
916 | bras_reg[18:0] <= 19'h7ffff; | |
917 | bwe_reg[18:0] <= 19'h7ffff; | |
918 | end | |
919 | // Self refres hexit / power down exit command | |
920 | ||
921 | ||
922 | // Activate command | |
923 | `ifdef AXIS_FBDIMM_1AMB | |
924 | if ( ( command[20] == 1'b1) ) | |
925 | `else | |
926 | if ( ( command[20] == 1'b1) && ( command[23:21] == DS )) | |
927 | `endif | |
928 | begin | |
929 | dram_cmd_vld<=1; | |
930 | bcs_reg[18:0] <= 18'h0; | |
931 | bcas_reg[18:0] <= 19'h7ffff; | |
932 | bwe_reg[18:0] <= 19'h7ffff; | |
933 | bras_reg[18:0] <= 19'h0; | |
934 | ba_reg[2:0] <= command[15:13]; | |
935 | ||
936 | // For activate, in 2GB(512MB X 4) config: | |
937 | // we use a14-a0 | |
938 | ||
939 | ||
940 | addr_reg[15:0] <= {command[19],command[18],command[16],command[12:0]}; | |
941 | `ifdef AXIS_FBDIMM_HW | |
942 | `else | |
943 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Activate command sent to DRAM - Address = %h BA =%h DS=%h RS=%h\n",addr_reg,command[15:13],command[23:21],RS); | |
944 | `endif | |
945 | end | |
946 | // Activate command | |
947 | ||
948 | ||
949 | ||
950 | // DRAM CKE per DIMM command | |
951 | if ( ( command[20:14] == 7'b0000111) ) | |
952 | begin | |
953 | `ifdef AXIS_FBDIMM_HW | |
954 | `else | |
955 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: DRAM CKE per DIMM command detected\n"); | |
956 | `endif | |
957 | dram_cmd_vld<=1; | |
958 | ||
959 | if ( command[13] == 0 ) // bcst = 0 | |
960 | begin | |
961 | `ifdef AXIS_FBDIMM_1AMB | |
962 | `else | |
963 | case(command[23:21]) | |
964 | 3'b000: begin | |
965 | cke_rank1_reg[18:0] <= {19{command[0]}}; | |
966 | cke_rank0_reg[18:0] <= {19{command[0]}}; | |
967 | end | |
968 | 3'b001: begin | |
969 | cke_rank1_reg[18:0] <= {19{command[1]}}; | |
970 | cke_rank0_reg[18:0] <= {19{command[1]}}; | |
971 | end | |
972 | 3'b010: begin | |
973 | cke_rank1_reg[18:0] <= {19{command[2]}}; | |
974 | cke_rank0_reg[18:0] <= {19{command[2]}}; | |
975 | end | |
976 | 3'b011: begin | |
977 | cke_rank1_reg[18:0] <= {19{command[3]}}; | |
978 | cke_rank0_reg[18:0] <= {19{command[3]}}; | |
979 | end | |
980 | 3'b100: begin | |
981 | cke_rank1_reg[18:0] <= {19{command[4]}}; | |
982 | cke_rank0_reg[18:0] <= {19{command[4]}}; | |
983 | end | |
984 | 3'b101: begin | |
985 | cke_rank1_reg[18:0] <= {19{command[5]}}; | |
986 | cke_rank0_reg[18:0] <= {19{command[5]}}; | |
987 | end | |
988 | 3'b110: begin | |
989 | cke_rank1_reg[18:0] <= {19{command[6]}}; | |
990 | cke_rank0_reg[18:0] <= {19{command[6]}}; | |
991 | end | |
992 | 3'b111: begin | |
993 | cke_rank1_reg[18:0] <= {19{command[7]}}; | |
994 | cke_rank0_reg[18:0] <= {19{command[7]}}; | |
995 | end | |
996 | endcase | |
997 | ||
998 | `endif | |
999 | end | |
1000 | ||
1001 | if ( command[13] == 1 ) // bcst = 1 | |
1002 | begin | |
1003 | `ifdef AXIS_FBDIMM_1AMB | |
1004 | ||
1005 | `else | |
1006 | case(DS) | |
1007 | 3'b000: begin | |
1008 | cke_rank1_reg[18:0] <= {19{command[0]}}; | |
1009 | cke_rank0_reg[18:0] <= {19{command[0]}}; | |
1010 | end | |
1011 | 3'b001: begin | |
1012 | cke_rank1_reg[18:0] <= {19{command[1]}}; | |
1013 | cke_rank0_reg[18:0] <= {19{command[1]}}; | |
1014 | end | |
1015 | 3'b010: begin | |
1016 | cke_rank1_reg[18:0] <= {19{command[2]}}; | |
1017 | cke_rank0_reg[18:0] <= {19{command[2]}}; | |
1018 | end | |
1019 | 3'b011: begin | |
1020 | cke_rank1_reg[18:0] <= {19{command[3]}}; | |
1021 | cke_rank0_reg[18:0] <= {19{command[3]}}; | |
1022 | end | |
1023 | 3'b100: begin | |
1024 | cke_rank1_reg[18:0] <= {19{command[4]}}; | |
1025 | cke_rank0_reg[18:0] <= {19{command[4]}}; | |
1026 | end | |
1027 | 3'b101: begin | |
1028 | cke_rank1_reg[18:0] <= {19{command[5]}}; | |
1029 | cke_rank0_reg[18:0] <= {19{command[5]}}; | |
1030 | end | |
1031 | 3'b110: begin | |
1032 | cke_rank1_reg[18:0] <= {19{command[6]}}; | |
1033 | cke_rank0_reg[18:0] <= {19{command[6]}}; | |
1034 | end | |
1035 | 3'b111: begin | |
1036 | cke_rank1_reg[18:0] <= {19{command[7]}}; | |
1037 | cke_rank0_reg[18:0] <= {19{command[7]}}; | |
1038 | end | |
1039 | endcase | |
1040 | ||
1041 | `endif | |
1042 | end | |
1043 | ||
1044 | end | |
1045 | // DRAM CKE per DIMM command | |
1046 | ||
1047 | ||
1048 | ||
1049 | // DRAM CKE per Rank command | |
1050 | ||
1051 | if ( ( command[20:14] == 7'b0000110) ) | |
1052 | begin | |
1053 | `ifdef AXIS_FBDIMM_HW | |
1054 | `else | |
1055 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: DRAM CKE per Rank command detected\n"); | |
1056 | `endif | |
1057 | dram_cmd_vld<=1; | |
1058 | ||
1059 | ||
1060 | if ( command[13] == 0 ) // bcst = 0 | |
1061 | begin | |
1062 | `ifdef AXIS_FBDIMM_1AMB | |
1063 | if ( command[17] ) begin | |
1064 | case(command[23:21]) | |
1065 | 3'b000: cke_rank1_reg[18:0] <= {19{command[0]}}; | |
1066 | 3'b001: cke_rank1_reg[18:0] <= {19{command[1]}}; | |
1067 | 3'b010: cke_rank1_reg[18:0] <= {19{command[2]}}; | |
1068 | 3'b011: cke_rank1_reg[18:0] <= {19{command[3]}}; | |
1069 | 3'b100: cke_rank1_reg[18:0] <= {19{command[4]}}; | |
1070 | 3'b101: cke_rank1_reg[18:0] <= {19{command[5]}}; | |
1071 | 3'b110: cke_rank1_reg[18:0] <= {19{command[6]}}; | |
1072 | 3'b111: cke_rank1_reg[18:0] <= {19{command[7]}}; | |
1073 | endcase | |
1074 | end else begin | |
1075 | case(command[23:21]) | |
1076 | 3'b000: cke_rank0_reg[18:0] <= {19{command[0]}}; | |
1077 | 3'b001: cke_rank0_reg[18:0] <= {19{command[1]}}; | |
1078 | 3'b010: cke_rank0_reg[18:0] <= {19{command[2]}}; | |
1079 | 3'b011: cke_rank0_reg[18:0] <= {19{command[3]}}; | |
1080 | 3'b100: cke_rank0_reg[18:0] <= {19{command[4]}}; | |
1081 | 3'b101: cke_rank0_reg[18:0] <= {19{command[5]}}; | |
1082 | 3'b110: cke_rank0_reg[18:0] <= {19{command[6]}}; | |
1083 | 3'b111: cke_rank0_reg[18:0] <= {19{command[7]}}; | |
1084 | endcase | |
1085 | ||
1086 | end | |
1087 | ||
1088 | `else | |
1089 | if ( command[23:21] == DS ) | |
1090 | begin | |
1091 | if ( command[17] ) begin | |
1092 | case(command[23:21]) | |
1093 | 3'b000: cke_rank1_reg[18:0] <= {19{command[0]}}; | |
1094 | 3'b001: cke_rank1_reg[18:0] <= {19{command[1]}}; | |
1095 | 3'b010: cke_rank1_reg[18:0] <= {19{command[2]}}; | |
1096 | 3'b011: cke_rank1_reg[18:0] <= {19{command[3]}}; | |
1097 | 3'b100: cke_rank1_reg[18:0] <= {19{command[4]}}; | |
1098 | 3'b101: cke_rank1_reg[18:0] <= {19{command[5]}}; | |
1099 | 3'b110: cke_rank1_reg[18:0] <= {19{command[6]}}; | |
1100 | 3'b111: cke_rank1_reg[18:0] <= {19{command[7]}}; | |
1101 | endcase | |
1102 | end else begin | |
1103 | case(command[23:21]) | |
1104 | 3'b000: cke_rank0_reg[18:0] <= {19{command[0]}}; | |
1105 | 3'b001: cke_rank0_reg[18:0] <= {19{command[1]}}; | |
1106 | 3'b010: cke_rank0_reg[18:0] <= {19{command[2]}}; | |
1107 | 3'b011: cke_rank0_reg[18:0] <= {19{command[3]}}; | |
1108 | 3'b100: cke_rank0_reg[18:0] <= {19{command[4]}}; | |
1109 | 3'b101: cke_rank0_reg[18:0] <= {19{command[5]}}; | |
1110 | 3'b110: cke_rank0_reg[18:0] <= {19{command[6]}}; | |
1111 | 3'b111: cke_rank0_reg[18:0] <= {19{command[7]}}; | |
1112 | endcase | |
1113 | end | |
1114 | ||
1115 | ||
1116 | end | |
1117 | `endif | |
1118 | end | |
1119 | ||
1120 | if ( command[13] == 1 ) // bcst = 1 | |
1121 | begin | |
1122 | if ( command[17] ) begin | |
1123 | case(DS) | |
1124 | 3'b000: cke_rank1_reg[18:0] <= {19{command[0]}}; | |
1125 | 3'b001: cke_rank1_reg[18:0] <= {19{command[1]}}; | |
1126 | 3'b010: cke_rank1_reg[18:0] <= {19{command[2]}}; | |
1127 | 3'b011: cke_rank1_reg[18:0] <= {19{command[3]}}; | |
1128 | 3'b100: cke_rank1_reg[18:0] <= {19{command[4]}}; | |
1129 | 3'b101: cke_rank1_reg[18:0] <= {19{command[5]}}; | |
1130 | 3'b110: cke_rank1_reg[18:0] <= {19{command[6]}}; | |
1131 | 3'b111: cke_rank1_reg[18:0] <= {19{command[7]}}; | |
1132 | endcase | |
1133 | end else begin | |
1134 | case(DS) | |
1135 | 3'b000: cke_rank0_reg[18:0] <= {19{command[0]}}; | |
1136 | 3'b001: cke_rank0_reg[18:0] <= {19{command[1]}}; | |
1137 | 3'b010: cke_rank0_reg[18:0] <= {19{command[2]}}; | |
1138 | 3'b011: cke_rank0_reg[18:0] <= {19{command[3]}}; | |
1139 | 3'b100: cke_rank0_reg[18:0] <= {19{command[4]}}; | |
1140 | 3'b101: cke_rank0_reg[18:0] <= {19{command[5]}}; | |
1141 | 3'b110: cke_rank0_reg[18:0] <= {19{command[6]}}; | |
1142 | 3'b111: cke_rank0_reg[18:0] <= {19{command[7]}}; | |
1143 | endcase | |
1144 | end | |
1145 | ||
1146 | end | |
1147 | ||
1148 | ||
1149 | ||
1150 | end | |
1151 | // DRAM CKE per Rank command | |
1152 | ||
1153 | ||
1154 | end // if (command[23:0] != 24'h0 ) | |
1155 | end // if ( !cmd_fifo_empty) | |
1156 | ||
1157 | ||
1158 | ||
1159 | if ( !cmd_fifo_empty_bc & !sb_crc_error ) begin | |
1160 | ||
1161 | ||
1162 | if ( command_bc[23:0] != 24'h0 ) // command is not a NOP | |
1163 | begin | |
1164 | // all commands have the Rank Select bit at the same position | |
1165 | RS<=command_bc[17]; | |
1166 | ||
1167 | // write command | |
1168 | `ifdef AXIS_FBDIMM_1AMB | |
1169 | if (( command_bc[20:18] == 3'b011 ) ) | |
1170 | `else | |
1171 | if (( command_bc[20:18] == 3'b011 ) && ( command_bc[23:21] == DS ) ) | |
1172 | `endif // AXIS_FBDIMM_1AMB | |
1173 | begin | |
1174 | stall_pipe <= 1'b0; | |
1175 | dram_cmd_vld <= 1'b1; | |
1176 | bcs_reg[18:0] <= 19'h0; | |
1177 | bcas_reg[18:0] <= 19'h0; | |
1178 | bwe_reg[18:0] <= 19'h0; | |
1179 | bras_reg[18:0] <= 19'h7ffff; | |
1180 | dm_rdqs_reg[18:0] <= 0; | |
1181 | ba_reg[2:0] <= command_bc[15:13]; | |
1182 | // For read/write, in 2GB(512MB X 4) config: | |
1183 | // we use a11-a0 | |
1184 | addr_reg[15:0] <= {4'h0,command_bc[11:0]}; | |
1185 | ||
1186 | write_cycle_start <= 1'b1; | |
1187 | `ifdef AXIS_FBDIMM_HW | |
1188 | `else | |
1189 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Write command sent to DRAM - Address = %h BA=%h DS=%h RS=%h\n",addr_reg,ba_reg,command[23:21],RS); | |
1190 | `endif // AXIS_FBDIMM_HW | |
1191 | ||
1192 | end // write command | |
1193 | ||
1194 | // Read command | |
1195 | `ifdef AXIS_FBDIMM_1AMB | |
1196 | if (( command_bc[20:18] == 3'b010 ) ) | |
1197 | `else | |
1198 | if (( command_bc[20:18] == 3'b010 ) && ( command_bc[23:21] == DS ) ) | |
1199 | `endif // AXIS_FBDIMM_1AMB | |
1200 | begin | |
1201 | read_cycle_start <= 1'b1; | |
1202 | dram_cmd_vld <= 1'b1; | |
1203 | bcs_reg[18:0] <= 19'h0; | |
1204 | bcas_reg[18:0] <= 19'h0; | |
1205 | bwe_reg[18:0] <= 19'h7ffff; | |
1206 | bras_reg[18:0] <= 19'h7ffff; | |
1207 | ba_reg[2:0] <= command_bc[15:13]; | |
1208 | ||
1209 | // For read/write, in 2GB(512MB X 4) config: | |
1210 | // we use a11-a0 | |
1211 | addr_reg[15:0] <= {4'h0,command_bc[11:0]}; | |
1212 | ||
1213 | `ifdef AXIS_FBDIMM_HW | |
1214 | `else | |
1215 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Read command sent to DRAM - Address = %h BA = %h DS=%h RS=%h\n",addr_reg, ba_reg,command[23:21],RS); | |
1216 | `endif // AXIS_FBDIMM_HW | |
1217 | end | |
1218 | // Read command | |
1219 | ||
1220 | // precharge all command | |
1221 | `ifdef AXIS_FBDIMM_1AMB | |
1222 | if (( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b111)) || issue_pre_all_cmd ) | |
1223 | `else | |
1224 | if (( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b111) && ( command_bc[23:21] == DS )) || issue_pre_all_cmd ) | |
1225 | `endif // AXIS_FBDIMM_1AMB | |
1226 | begin | |
1227 | `ifdef AXIS_FBDIMM_HW | |
1228 | `else | |
1229 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Precharge All command sent to DRAM\n"); | |
1230 | `endif // AXIS_FBDIMM_HW | |
1231 | dram_cmd_vld <= 1'b1; | |
1232 | bcs_reg[18:0] <= 19'h0; | |
1233 | bcas_reg[18:0] <= 19'h7ffff; | |
1234 | bwe_reg[18:0] <= 19'h0; | |
1235 | bras_reg[18:0] <= 19'h0; | |
1236 | addr_reg[10] <= 1'b1; | |
1237 | end | |
1238 | // precharge all command | |
1239 | ||
1240 | // precharge single command | |
1241 | `ifdef AXIS_FBDIMM_1AMB | |
1242 | if ( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b110)) | |
1243 | `else | |
1244 | if ( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b110) && ( command_bc[23:21] == DS )) | |
1245 | `endif // AXIS_FBDIMM_1AMB | |
1246 | begin | |
1247 | `ifdef AXIS_FBDIMM_HW | |
1248 | `else | |
1249 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Precharge Single command sent to DRAM bank = %h\n",command[16:13]); | |
1250 | `endif // AXIS_FBDIMM_HW | |
1251 | dram_cmd_vld <= 1'b1; | |
1252 | bcs_reg[18:0] <= 19'h0; | |
1253 | bcas_reg[18:0] <= 19'h7fff; | |
1254 | bwe_reg[18:0] <= 19'h0; | |
1255 | bras_reg[18:0] <= 19'h0; | |
1256 | addr_reg[10] <= 1'b0; | |
1257 | ba_reg[2:0] <= command_bc[16:13]; | |
1258 | end | |
1259 | // precharge signle command | |
1260 | ||
1261 | // Auto refresh command | |
1262 | `ifdef AXIS_FBDIMM_1AMB | |
1263 | if ( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b101) ) | |
1264 | `else | |
1265 | if ( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b101) && ( command_bc[23:21] == DS )) | |
1266 | `endif // AXIS_FBDIMM_1AMB | |
1267 | begin | |
1268 | `ifdef AXIS_FBDIMM_HW | |
1269 | `else | |
1270 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: AutoRefresh command sent to DRAM\n"); | |
1271 | `endif // AXIS_FBDIMM_HW | |
1272 | dram_cmd_vld <= 1'b1; | |
1273 | bcs_reg[18:0] <= 19'h0; | |
1274 | bcas_reg[18:0] <= 19'h0; | |
1275 | bwe_reg[18:0] <= 19'h7ffff; | |
1276 | bras_reg[18:0] <= 19'h0; | |
1277 | end | |
1278 | // Auto Refresh command | |
1279 | ||
1280 | // Self refresh entry command | |
1281 | `ifdef AXIS_FBDIMM_1AMB | |
1282 | if ( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b100)) | |
1283 | `else | |
1284 | if ( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b100) && ( command_bc[23:21] == DS )) | |
1285 | `endif // AXIS_FBDIMM_1AMB | |
1286 | begin | |
1287 | `ifdef AXIS_FBDIMM_HW | |
1288 | `else | |
1289 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Self Refresh Entry command sent to DRAM\n"); | |
1290 | `endif // AXIS_FBDIMM_HW | |
1291 | dram_cmd_vld <= 1'b1; | |
1292 | if ( command_bc[17] ) | |
1293 | cke_rank1_reg[18:0] <= 19'h0; | |
1294 | else | |
1295 | cke_rank0_reg[18:0] <= 19'h0; | |
1296 | ||
1297 | bcs_reg[18:0] <= 19'h0; | |
1298 | bcas_reg[18:0] <= 19'h0; | |
1299 | bras_reg[18:0] <= 19'h0; | |
1300 | bwe_reg[18:0] <= 19'h7ffff; | |
1301 | end | |
1302 | // Self refresh entry command | |
1303 | ||
1304 | // Power Down entry command | |
1305 | `ifdef AXIS_FBDIMM_1AMB | |
1306 | if ( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b010) ) | |
1307 | `else | |
1308 | if ( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b010) && ( command_bc[23:21] == DS )) | |
1309 | `endif // AXIS_FBDIMM_1AMB | |
1310 | begin | |
1311 | `ifdef AXIS_FBDIMM_HW | |
1312 | `else | |
1313 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Power Down Entry command sent to DRAM\n"); | |
1314 | `endif // AXIS_FBDIMM_HW | |
1315 | dram_cmd_vld <= 1'b1; | |
1316 | if ( command_bc[17] ) | |
1317 | cke_rank1_reg[18:0] <= 19'h0; | |
1318 | else | |
1319 | cke_rank0_reg[18:0] <= 19'h0; | |
1320 | ||
1321 | bcs_reg[18:0] <= 19'h0; | |
1322 | bcas_reg[18:0] <= 19'h7ffff; | |
1323 | bras_reg[18:0] <= 19'h7ffff; | |
1324 | bwe_reg[18:0] <= 19'h7ffff; | |
1325 | end | |
1326 | // Power Down entry command | |
1327 | ||
1328 | // Self refresh exit / power down exit command | |
1329 | `ifdef AXIS_FBDIMM_1AMB | |
1330 | if ( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b011) ) | |
1331 | `else | |
1332 | if ( ( command_bc[20:18] == 3'b001) && ( command_bc[12:10] == 3'b011) && ( command_bc[23:21] == DS )) | |
1333 | `endif // AXIS_FBDIMM_1AMB | |
1334 | begin | |
1335 | `ifdef AXIS_FBDIMM_HW | |
1336 | `else | |
1337 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Self Refresh/Power Down Exit command sent to DRAM\n"); | |
1338 | `endif // AXIS_FBDIMM_HW | |
1339 | dram_cmd_vld <= 1'b1; | |
1340 | if ( command_bc[17] ) | |
1341 | cke_rank1_reg[18:0] <= 19'h7ffff; | |
1342 | else | |
1343 | cke_rank0_reg[18:0] <= 19'h7ffff; | |
1344 | ||
1345 | bcs_reg[18:0] <= 19'h0; | |
1346 | bcas_reg[18:0] <= 19'h7ffff; | |
1347 | bras_reg[18:0] <= 19'h7ffff; | |
1348 | bwe_reg[18:0] <= 19'h7ffff; | |
1349 | end | |
1350 | // Self refres hexit / power down exit command | |
1351 | ||
1352 | ||
1353 | // Activate command | |
1354 | `ifdef AXIS_FBDIMM_1AMB | |
1355 | if ( ( command_bc[20] == 1'b1) ) | |
1356 | `else | |
1357 | if ( ( command_bc[20] == 1'b1) && ( command_bc[23:21] == DS )) | |
1358 | `endif | |
1359 | begin | |
1360 | dram_cmd_vld<=1; | |
1361 | bcs_reg[18:0] <= 18'h0; | |
1362 | bcas_reg[18:0] <= 19'h7ffff; | |
1363 | bwe_reg[18:0] <= 19'h7ffff; | |
1364 | bras_reg[18:0] <= 19'h0; | |
1365 | ba_reg[2:0] <= command_bc[15:13]; | |
1366 | ||
1367 | // For activate, in 2GB(512MB X 4) config: | |
1368 | // we use a14-a0 | |
1369 | ||
1370 | ||
1371 | addr_reg[15:0] <= {command_bc[19],command_bc[18],command_bc[16],command_bc[12:0]}; | |
1372 | `ifdef AXIS_FBDIMM_HW | |
1373 | `else | |
1374 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: Activate command sent to DRAM - Address = %h BA =%h DS=%h RS=%h\n",addr_reg,command[15:13],command[23:21],RS); | |
1375 | `endif | |
1376 | end | |
1377 | // Activate command | |
1378 | ||
1379 | ||
1380 | // DRAM CKE per DIMM command | |
1381 | if ( ( command_bc[20:14] == 7'b0000111) ) | |
1382 | begin | |
1383 | `ifdef AXIS_FBDIMM_HW | |
1384 | `else | |
1385 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: DRAM CKE per DIMM command detected\n"); | |
1386 | `endif | |
1387 | dram_cmd_vld<=1; | |
1388 | ||
1389 | if ( command_bc[13] == 0 ) // bcst = 0 | |
1390 | begin | |
1391 | `ifdef AXIS_FBDIMM_1AMB | |
1392 | `else | |
1393 | case(command_bc[23:21]) | |
1394 | 3'b000: begin | |
1395 | cke_rank1_reg[18:0] <= {19{command_bc[0]}}; | |
1396 | cke_rank0_reg[18:0] <= {19{command_bc[0]}}; | |
1397 | end | |
1398 | 3'b001: begin | |
1399 | cke_rank1_reg[18:0] <= {19{command_bc[1]}}; | |
1400 | cke_rank0_reg[18:0] <= {19{command_bc[1]}}; | |
1401 | end | |
1402 | 3'b010: begin | |
1403 | cke_rank1_reg[18:0] <= {19{command_bc[2]}}; | |
1404 | cke_rank0_reg[18:0] <= {19{command_bc[2]}}; | |
1405 | end | |
1406 | 3'b011: begin | |
1407 | cke_rank1_reg[18:0] <= {19{command_bc[3]}}; | |
1408 | cke_rank0_reg[18:0] <= {19{command_bc[3]}}; | |
1409 | end | |
1410 | 3'b100: begin | |
1411 | cke_rank1_reg[18:0] <= {19{command_bc[4]}}; | |
1412 | cke_rank0_reg[18:0] <= {19{command_bc[4]}}; | |
1413 | end | |
1414 | 3'b101: begin | |
1415 | cke_rank1_reg[18:0] <= {19{command_bc[5]}}; | |
1416 | cke_rank0_reg[18:0] <= {19{command_bc[5]}}; | |
1417 | end | |
1418 | 3'b110: begin | |
1419 | cke_rank1_reg[18:0] <= {19{command_bc[6]}}; | |
1420 | cke_rank0_reg[18:0] <= {19{command_bc[6]}}; | |
1421 | end | |
1422 | 3'b111: begin | |
1423 | cke_rank1_reg[18:0] <= {19{command_bc[7]}}; | |
1424 | cke_rank0_reg[18:0] <= {19{command_bc[7]}}; | |
1425 | end | |
1426 | endcase | |
1427 | ||
1428 | `endif | |
1429 | end | |
1430 | ||
1431 | if ( command_bc[13] == 1 ) // bcst = 1 | |
1432 | begin | |
1433 | `ifdef AXIS_FBDIMM_1AMB | |
1434 | ||
1435 | `else | |
1436 | case(DS) | |
1437 | 3'b000: begin | |
1438 | cke_rank1_reg[18:0] <= {19{command_bc[0]}}; | |
1439 | cke_rank0_reg[18:0] <= {19{command_bc[0]}}; | |
1440 | end | |
1441 | 3'b001: begin | |
1442 | cke_rank1_reg[18:0] <= {19{command_bc[1]}}; | |
1443 | cke_rank0_reg[18:0] <= {19{command_bc[1]}}; | |
1444 | end | |
1445 | 3'b010: begin | |
1446 | cke_rank1_reg[18:0] <= {19{command_bc[2]}}; | |
1447 | cke_rank0_reg[18:0] <= {19{command_bc[2]}}; | |
1448 | end | |
1449 | 3'b011: begin | |
1450 | cke_rank1_reg[18:0] <= {19{command_bc[3]}}; | |
1451 | cke_rank0_reg[18:0] <= {19{command_bc[3]}}; | |
1452 | end | |
1453 | 3'b100: begin | |
1454 | cke_rank1_reg[18:0] <= {19{command_bc[4]}}; | |
1455 | cke_rank0_reg[18:0] <= {19{command_bc[4]}}; | |
1456 | end | |
1457 | 3'b101: begin | |
1458 | cke_rank1_reg[18:0] <= {19{command_bc[5]}}; | |
1459 | cke_rank0_reg[18:0] <= {19{command_bc[5]}}; | |
1460 | end | |
1461 | 3'b110: begin | |
1462 | cke_rank1_reg[18:0] <= {19{command_bc[6]}}; | |
1463 | cke_rank0_reg[18:0] <= {19{command_bc[6]}}; | |
1464 | end | |
1465 | 3'b111: begin | |
1466 | cke_rank1_reg[18:0] <= {19{command_bc[7]}}; | |
1467 | cke_rank0_reg[18:0] <= {19{command_bc[7]}}; | |
1468 | end | |
1469 | endcase | |
1470 | ||
1471 | `endif | |
1472 | end | |
1473 | ||
1474 | end | |
1475 | // DRAM CKE per DIMM command | |
1476 | ||
1477 | ||
1478 | // DRAM CKE per Rank command | |
1479 | ||
1480 | if ( ( command_bc[20:14] == 7'b0000110) ) | |
1481 | begin | |
1482 | `ifdef AXIS_FBDIMM_HW | |
1483 | `else | |
1484 | `PR_ALWAYS ("dram",`DBG_0,"FBDIMM: DRAM CKE per Rank command detected\n"); | |
1485 | `endif | |
1486 | dram_cmd_vld<=1; | |
1487 | ||
1488 | if ( command_bc[13] == 0 ) // bcst = 0 | |
1489 | begin | |
1490 | `ifdef AXIS_FBDIMM_1AMB | |
1491 | if ( command_bc[17]) begin | |
1492 | case(command_bc[23:21]) | |
1493 | 3'b000: cke_rank1_reg[18:0] <= {19{command_bc[0]}}; | |
1494 | 3'b001: cke_rank1_reg[18:0] <= {19{command_bc[1]}}; | |
1495 | 3'b010: cke_rank1_reg[18:0] <= {19{command_bc[2]}}; | |
1496 | 3'b011: cke_rank1_reg[18:0] <= {19{command_bc[3]}}; | |
1497 | 3'b100: cke_rank1_reg[18:0] <= {19{command_bc[4]}}; | |
1498 | 3'b101: cke_rank1_reg[18:0] <= {19{command_bc[5]}}; | |
1499 | 3'b110: cke_rank1_reg[18:0] <= {19{command_bc[6]}}; | |
1500 | 3'b111: cke_rank1_reg[18:0] <= {19{command_bc[7]}}; | |
1501 | endcase | |
1502 | end else begin | |
1503 | case(command_bc[23:21]) | |
1504 | 3'b000: cke_rank0_reg[18:0] <= {19{command_bc[0]}}; | |
1505 | 3'b001: cke_rank0_reg[18:0] <= {19{command_bc[1]}}; | |
1506 | 3'b010: cke_rank0_reg[18:0] <= {19{command_bc[2]}}; | |
1507 | 3'b011: cke_rank0_reg[18:0] <= {19{command_bc[3]}}; | |
1508 | 3'b100: cke_rank0_reg[18:0] <= {19{command_bc[4]}}; | |
1509 | 3'b101: cke_rank0_reg[18:0] <= {19{command_bc[5]}}; | |
1510 | 3'b110: cke_rank0_reg[18:0] <= {19{command_bc[6]}}; | |
1511 | 3'b111: cke_rank0_reg[18:0] <= {19{command_bc[7]}}; | |
1512 | endcase | |
1513 | end | |
1514 | ||
1515 | `else | |
1516 | if ( command_bc[23:21] == DS ) | |
1517 | begin | |
1518 | if ( command_bc[17]) begin | |
1519 | case(command_bc[23:21]) | |
1520 | 3'b000: cke_rank1_reg[18:0] <= {19{command_bc[0]}}; | |
1521 | 3'b001: cke_rank1_reg[18:0] <= {19{command_bc[1]}}; | |
1522 | 3'b010: cke_rank1_reg[18:0] <= {19{command_bc[2]}}; | |
1523 | 3'b011: cke_rank1_reg[18:0] <= {19{command_bc[3]}}; | |
1524 | 3'b100: cke_rank1_reg[18:0] <= {19{command_bc[4]}}; | |
1525 | 3'b101: cke_rank1_reg[18:0] <= {19{command_bc[5]}}; | |
1526 | 3'b110: cke_rank1_reg[18:0] <= {19{command_bc[6]}}; | |
1527 | 3'b111: cke_rank1_reg[18:0] <= {19{command_bc[7]}}; | |
1528 | endcase | |
1529 | end else begin | |
1530 | case(command_bc[23:21]) | |
1531 | 3'b000: cke_rank0_reg[18:0] <= {19{command_bc[0]}}; | |
1532 | 3'b001: cke_rank0_reg[18:0] <= {19{command_bc[1]}}; | |
1533 | 3'b010: cke_rank0_reg[18:0] <= {19{command_bc[2]}}; | |
1534 | 3'b011: cke_rank0_reg[18:0] <= {19{command_bc[3]}}; | |
1535 | 3'b100: cke_rank0_reg[18:0] <= {19{command_bc[4]}}; | |
1536 | 3'b101: cke_rank0_reg[18:0] <= {19{command_bc[5]}}; | |
1537 | 3'b110: cke_rank0_reg[18:0] <= {19{command_bc[6]}}; | |
1538 | 3'b111: cke_rank0_reg[18:0] <= {19{command_bc[7]}}; | |
1539 | endcase | |
1540 | end | |
1541 | ||
1542 | end | |
1543 | `endif | |
1544 | end | |
1545 | ||
1546 | if ( command_bc[13] == 1 ) // bcst = 1 | |
1547 | begin | |
1548 | if ( command_bc[17]) begin | |
1549 | case(DS) | |
1550 | 3'b000: cke_rank1_reg[18:0] <= {19{command_bc[0]}}; | |
1551 | 3'b001: cke_rank1_reg[18:0] <= {19{command_bc[1]}}; | |
1552 | 3'b010: cke_rank1_reg[18:0] <= {19{command_bc[2]}}; | |
1553 | 3'b011: cke_rank1_reg[18:0] <= {19{command_bc[3]}}; | |
1554 | 3'b100: cke_rank1_reg[18:0] <= {19{command_bc[4]}}; | |
1555 | 3'b101: cke_rank1_reg[18:0] <= {19{command_bc[5]}}; | |
1556 | 3'b110: cke_rank1_reg[18:0] <= {19{command_bc[6]}}; | |
1557 | 3'b111: cke_rank1_reg[18:0] <= {19{command_bc[7]}}; | |
1558 | endcase | |
1559 | end else begin | |
1560 | if ( command_bc[17]) begin | |
1561 | case(DS) | |
1562 | 3'b000: cke_rank0_reg[18:0] <= {19{command_bc[0]}}; | |
1563 | 3'b001: cke_rank0_reg[18:0] <= {19{command_bc[1]}}; | |
1564 | 3'b010: cke_rank0_reg[18:0] <= {19{command_bc[2]}}; | |
1565 | 3'b011: cke_rank0_reg[18:0] <= {19{command_bc[3]}}; | |
1566 | 3'b100: cke_rank0_reg[18:0] <= {19{command_bc[4]}}; | |
1567 | 3'b101: cke_rank0_reg[18:0] <= {19{command_bc[5]}}; | |
1568 | 3'b110: cke_rank0_reg[18:0] <= {19{command_bc[6]}}; | |
1569 | 3'b111: cke_rank0_reg[18:0] <= {19{command_bc[7]}}; | |
1570 | endcase | |
1571 | end | |
1572 | end | |
1573 | ||
1574 | end | |
1575 | ||
1576 | ||
1577 | ||
1578 | end | |
1579 | // DRAM CKE per Rank command | |
1580 | ||
1581 | ||
1582 | ||
1583 | end // if (command_bc[23:0] != 24'h0 ) | |
1584 | end // if ( !cmd_fifo_empty_bc) | |
1585 | ||
1586 | ||
1587 | end // drams_on | |
1588 | ||
1589 | // DCAL CSR register needs to send a command to drams | |
1590 | if ( dcalcsr[31] ) | |
1591 | begin | |
1592 | dcalcsr_complete <= 1; | |
1593 | bcs_reg[18:0]<=0; | |
1594 | bcas_reg[18:0]<=0; | |
1595 | bras_reg[18:0]<=0; | |
1596 | bwe_reg[18:0]<=0; | |
1597 | ba_reg<=dcaladdr[2:0]; | |
1598 | addr_reg<=dcaladdr[31:16]; | |
1599 | end | |
1600 | else | |
1601 | dcalcsr_complete <= 0; | |
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | /**** Command BC ******/ | |
1608 | ||
1609 | ||
1610 | end // command decoder | |
1611 | ||
1612 | ||
1613 | ||
1614 | ||
1615 | wire write_cmd = command_rdy & ( command_in[23:0] != 24'h0); | |
1616 | ||
1617 | // This fifo gets commands from sb decoder and sends to drams | |
1618 | ||
1619 | beh_fifo #(24,9) cmd_fifo_A (.rdata (cmd_fifo_rd_data), | |
1620 | .wfull (cmd_fifo_full), | |
1621 | .rempty (cmd_fifo_empty), | |
1622 | .wdata (command_in[23:0]), | |
1623 | .winc (write_cmd & ( command_type[1:0] == 2'b11) ), | |
1624 | .wclk (clk_int), | |
1625 | .wrst_n (~reset), | |
1626 | .rinc ( 1'b1 ), | |
1627 | .rclk ( frm_boundary ), // dram_clk), | |
1628 | .rrst_n (~reset), | |
1629 | .inv ( sb_crc_error )); | |
1630 | ||
1631 | wire [23:0] command_in_bc = ( command_type[1:0] == 2'b11 ) ? 24'h0 : command_in; | |
1632 | ||
1633 | beh_fifo #(24,9) cmd_fifo_BC (.rdata (cmd_fifo_rd_data_bc), | |
1634 | .wfull (cmd_fifo_full_bc), | |
1635 | .rempty (cmd_fifo_empty_bc), | |
1636 | .wdata ( command_in_bc), | |
1637 | .winc ( write_cmd ) , | |
1638 | .wclk (clk_int), | |
1639 | .wrst_n (~reset), | |
1640 | .rinc ( 1'b1 ), | |
1641 | .rclk ( frm_boundary ), // dram_clk), | |
1642 | .rrst_n (~reset), | |
1643 | .inv ( sb_crc_error )); | |
1644 | ||
1645 | ||
1646 | `ifdef CAD_DDR2_DRAM | |
1647 | ||
1648 | // Dram devices for X8 configuration | |
1649 | ||
1650 | `ifdef X8 | |
1651 | ||
1652 | ddr2_dram dram_1 ( .CK (dram_clk), | |
1653 | .bCK (~dram_clk), | |
1654 | .CKE (cke[1]), | |
1655 | .bCS (bcs[1]), | |
1656 | .bRAS (bras[1]), | |
1657 | .bCAS (bcas[1]), | |
1658 | .bWE (bwe[1]), | |
1659 | .BA (ba), | |
1660 | .Addr (addr), | |
1661 | .DQ (dq[7:0]), | |
1662 | .DQS (dqs[1]), | |
1663 | .bDQS (bdqs[1]), | |
1664 | .DM_RDQS (dm_rdqs[1]), | |
1665 | .bRDQS (brdqs[1]), | |
1666 | .ODT (odt[1]), | |
1667 | .areset (areset[1]), | |
1668 | .term (term[1])); | |
1669 | ||
1670 | ddr2_dram dram_2 ( .CK (dram_clk), | |
1671 | .bCK (~dram_clk), | |
1672 | .CKE (cke[2]), | |
1673 | .bCS (bcs[2]), | |
1674 | .bRAS (bras[2]), | |
1675 | .bCAS (bcas[2]), | |
1676 | .bWE (bwe[2]), | |
1677 | .BA (ba), | |
1678 | .Addr (addr), | |
1679 | .DQ (dq[15:8]), | |
1680 | .DQS (dqs[2]), | |
1681 | .bDQS (bdqs[2]), | |
1682 | .DM_RDQS (dm_rdqs[2]), | |
1683 | .bRDQS (brdqs[2]), | |
1684 | .ODT (odt[2]), | |
1685 | .areset (areset[2]), | |
1686 | .term (term[2])); | |
1687 | ||
1688 | ddr2_dram dram_3 ( .CK (dram_clk), | |
1689 | .bCK (~dram_clk), | |
1690 | .CKE (cke[3]), | |
1691 | .bCS (bcs[3]), | |
1692 | .bRAS (bras[3]), | |
1693 | .bCAS (bcas[3]), | |
1694 | .bWE (bwe[3]), | |
1695 | .BA (ba), | |
1696 | .Addr (addr), | |
1697 | .DQ (dq[23:16]), | |
1698 | .DQS (dqs[3]), | |
1699 | .bDQS (bdqs[3]), | |
1700 | .DM_RDQS (dm_rdqs[3]), | |
1701 | .bRDQS (brdqs[3]), | |
1702 | .areset (areset[3]), | |
1703 | .ODT (odt[3]), | |
1704 | .term (term[3])); | |
1705 | ||
1706 | ddr2_dram dram_4 ( .CK (dram_clk), | |
1707 | .bCK (~dram_clk), | |
1708 | .CKE (cke[4]), | |
1709 | .bCS (bcs[4]), | |
1710 | .bRAS (bras[4]), | |
1711 | .bCAS (bcas[4]), | |
1712 | .bWE (bwe[4]), | |
1713 | .BA (ba), | |
1714 | .Addr (addr), | |
1715 | .DQ (dq[31:24]), | |
1716 | .DQS (dqs[4]), | |
1717 | .bDQS (bdqs[4]), | |
1718 | .DM_RDQS (dm_rdqs[4]), | |
1719 | .bRDQS (brdqs[4]), | |
1720 | .ODT (odt[4]), | |
1721 | .areset (areset[4]), | |
1722 | .term (term[4])); | |
1723 | ||
1724 | ddr2_dram dram_5 ( .CK (dram_clk), | |
1725 | .bCK (~dram_clk), | |
1726 | .CKE (cke[5]), | |
1727 | .bCS (bcs[5]), | |
1728 | .bRAS (bras[5]), | |
1729 | .bCAS (bcas[5]), | |
1730 | .bWE (bwe[5]), | |
1731 | .BA (ba), | |
1732 | .Addr (addr), | |
1733 | .DQ (dq[39:32]), | |
1734 | .DQS (dqs[5]), | |
1735 | .bDQS (bdqs[5]), | |
1736 | .DM_RDQS (dm_rdqs[5]), | |
1737 | .bRDQS (brdqs[5]), | |
1738 | .areset (areset[5]), | |
1739 | .ODT (odt[5]), | |
1740 | .term (term[5])); | |
1741 | ||
1742 | ddr2_dram dram_6 ( .CK (dram_clk), | |
1743 | .bCK (~dram_clk), | |
1744 | .CKE (cke[6]), | |
1745 | .bCS (bcs[6]), | |
1746 | .bRAS (bras[6]), | |
1747 | .bCAS (bcas[6]), | |
1748 | .bWE (bwe[6]), | |
1749 | .BA (ba), | |
1750 | .Addr (addr), | |
1751 | .DQ (dq[47:40]), | |
1752 | .DQS (dqs[6]), | |
1753 | .bDQS (bdqs[6]), | |
1754 | .DM_RDQS (dm_rdqs[6]), | |
1755 | .bRDQS (brdqs[6]), | |
1756 | .ODT (odt[6]), | |
1757 | .areset (areset[6]), | |
1758 | .term (term[6])); | |
1759 | ||
1760 | ddr2_dram dram_7 ( .CK (dram_clk), | |
1761 | .bCK (~dram_clk), | |
1762 | .CKE (cke[7]), | |
1763 | .bCS (bcs[7]), | |
1764 | .bRAS (bras[7]), | |
1765 | .bCAS (bcas[7]), | |
1766 | .bWE (bwe[7]), | |
1767 | .BA (ba), | |
1768 | .Addr (addr), | |
1769 | .DQ (dq[55:48]), | |
1770 | .DQS (dqs[7]), | |
1771 | .bDQS (bdqs[7]), | |
1772 | .DM_RDQS (dm_rdqs[7]), | |
1773 | .bRDQS (brdqs[7]), | |
1774 | .ODT (odt[7]), | |
1775 | .areset (areset[7]), | |
1776 | .term (term[7])); | |
1777 | ||
1778 | ddr2_dram dram_8 ( .CK (dram_clk), | |
1779 | .bCK (~dram_clk), | |
1780 | .CKE (cke[8]), | |
1781 | .bCS (bcs[8]), | |
1782 | .bRAS (bras[8]), | |
1783 | .bCAS (bcas[8]), | |
1784 | .bWE (bwe[8]), | |
1785 | .BA (ba), | |
1786 | .Addr (addr), | |
1787 | .DQ (dq[63:56]), | |
1788 | .DQS (dqs[8]), | |
1789 | .bDQS (bdqs[8]), | |
1790 | .DM_RDQS (dm_rdqs[8]), | |
1791 | .bRDQS (brdqs[8]), | |
1792 | .ODT (odt[8]), | |
1793 | .areset (areset[8]), | |
1794 | .term (term[8])); | |
1795 | ||
1796 | ||
1797 | ddr2_dram dram_9 ( .CK (dram_clk), | |
1798 | .bCK (~dram_clk), | |
1799 | .CKE (cke[9]), | |
1800 | .bCS (bcs[9]), | |
1801 | .bRAS (bras[9]), | |
1802 | .bCAS (bcas[9]), | |
1803 | .bWE (bwe[9]), | |
1804 | .BA (ba), | |
1805 | .Addr (addr), | |
1806 | .DQ (dq[71:64]), | |
1807 | .DQS (dqs[9]), | |
1808 | .bDQS (bdqs[9]), | |
1809 | .DM_RDQS (dm_rdqs[9]), | |
1810 | .bRDQS (brdqs[9]), | |
1811 | .ODT (odt[9]), | |
1812 | .areset (areset[9]), | |
1813 | .term (term[9])); | |
1814 | ||
1815 | `endif // X8 | |
1816 | ||
1817 | // Dram devices for X4 configuration | |
1818 | ||
1819 | `ifdef X4 | |
1820 | ||
1821 | ||
1822 | ||
1823 | `ifdef DRAM_SAT | |
1824 | `else | |
1825 | ||
1826 | ddr2_dram dram_1 ( .CK (dram_clk), | |
1827 | .bCK (~dram_clk), | |
1828 | .CKE (cke[1]), | |
1829 | .bCS (bcs[1]), | |
1830 | .bRAS (bras[1]), | |
1831 | .bCAS (bcas[1]), | |
1832 | .bWE (bwe[1]), | |
1833 | .BA (ba), | |
1834 | .Addr (addr), | |
1835 | .DQ (dq[3:0]), | |
1836 | .DQS (dqs[1]), | |
1837 | .bDQS (bdqs[1]), | |
1838 | .ODT (odt[1]), | |
1839 | .areset (areset[1]), | |
1840 | .term (term[1])); | |
1841 | ||
1842 | ddr2_dram dram_2 ( .CK (dram_clk), | |
1843 | .bCK (~dram_clk), | |
1844 | .CKE (cke[2]), | |
1845 | .bCS (bcs[2]), | |
1846 | .bRAS (bras[2]), | |
1847 | .bCAS (bcas[2]), | |
1848 | .bWE (bwe[2]), | |
1849 | .BA (ba), | |
1850 | .Addr (addr), | |
1851 | .DQ (dq[7:4]), | |
1852 | .DQS (dqs[2]), | |
1853 | .bDQS (bdqs[2]), | |
1854 | .ODT (odt[2]), | |
1855 | .areset (areset[2]), | |
1856 | .term (term[2])); | |
1857 | ||
1858 | ddr2_dram dram_3 ( .CK (dram_clk), | |
1859 | .bCK (~dram_clk), | |
1860 | .CKE (cke[3]), | |
1861 | .bCS (bcs[3]), | |
1862 | .bRAS (bras[3]), | |
1863 | .bCAS (bcas[3]), | |
1864 | .bWE (bwe[3]), | |
1865 | .BA (ba), | |
1866 | .Addr (addr), | |
1867 | .DQ (dq[11:8]), | |
1868 | .DQS (dqs[3]), | |
1869 | .bDQS (bdqs[3]), | |
1870 | .areset (areset[3]), | |
1871 | .ODT (odt[3]), | |
1872 | .term (term[3])); | |
1873 | ||
1874 | ddr2_dram dram_4 ( .CK (dram_clk), | |
1875 | .bCK (~dram_clk), | |
1876 | .CKE (cke[4]), | |
1877 | .bCS (bcs[4]), | |
1878 | .bRAS (bras[4]), | |
1879 | .bCAS (bcas[4]), | |
1880 | .bWE (bwe[4]), | |
1881 | .BA (ba), | |
1882 | .Addr (addr), | |
1883 | .DQ (dq[15:12]), | |
1884 | .DQS (dqs[4]), | |
1885 | .bDQS (bdqs[4]), | |
1886 | .ODT (odt[4]), | |
1887 | .areset (areset[4]), | |
1888 | .term (term[4])); | |
1889 | ||
1890 | ddr2_dram dram_5 ( .CK (dram_clk), | |
1891 | .bCK (~dram_clk), | |
1892 | .CKE (cke[5]), | |
1893 | .bCS (bcs[5]), | |
1894 | .bRAS (bras[5]), | |
1895 | .bCAS (bcas[5]), | |
1896 | .bWE (bwe[5]), | |
1897 | .BA (ba), | |
1898 | .Addr (addr), | |
1899 | .DQ (dq[19:16]), | |
1900 | .DQS (dqs[5]), | |
1901 | .bDQS (bdqs[5]), | |
1902 | .areset (areset[5]), | |
1903 | .ODT (odt[5]), | |
1904 | .term (term[5])); | |
1905 | ||
1906 | ddr2_dram dram_6 ( .CK (dram_clk), | |
1907 | .bCK (~dram_clk), | |
1908 | .CKE (cke[6]), | |
1909 | .bCS (bcs[6]), | |
1910 | .bRAS (bras[6]), | |
1911 | .bCAS (bcas[6]), | |
1912 | .bWE (bwe[6]), | |
1913 | .BA (ba), | |
1914 | .Addr (addr), | |
1915 | .DQ (dq[23:20]), | |
1916 | .DQS (dqs[6]), | |
1917 | .bDQS (bdqs[6]), | |
1918 | .ODT (odt[6]), | |
1919 | .areset (areset[6]), | |
1920 | .term (term[6])); | |
1921 | ||
1922 | ddr2_dram dram_7 ( .CK (dram_clk), | |
1923 | .bCK (~dram_clk), | |
1924 | .CKE (cke[7]), | |
1925 | .bCS (bcs[7]), | |
1926 | .bRAS (bras[7]), | |
1927 | .bCAS (bcas[7]), | |
1928 | .bWE (bwe[7]), | |
1929 | .BA (ba), | |
1930 | .Addr (addr), | |
1931 | .DQ (dq[27:24]), | |
1932 | .DQS (dqs[7]), | |
1933 | .bDQS (bdqs[7]), | |
1934 | .ODT (odt[7]), | |
1935 | .areset (areset[7]), | |
1936 | .term (term[7])); | |
1937 | ||
1938 | ddr2_dram dram_8 ( .CK (dram_clk), | |
1939 | .bCK (~dram_clk), | |
1940 | .CKE (cke[8]), | |
1941 | .bCS (bcs[8]), | |
1942 | .bRAS (bras[8]), | |
1943 | .bCAS (bcas[8]), | |
1944 | .bWE (bwe[8]), | |
1945 | .BA (ba), | |
1946 | .Addr (addr), | |
1947 | .DQ (dq[31:28]), | |
1948 | .DQS (dqs[8]), | |
1949 | .bDQS (bdqs[8]), | |
1950 | .ODT (odt[8]), | |
1951 | .areset (areset[8]), | |
1952 | .term (term[8])); | |
1953 | ||
1954 | ||
1955 | ddr2_dram dram_9 ( .CK (dram_clk), | |
1956 | .bCK (~dram_clk), | |
1957 | .CKE (cke[9]), | |
1958 | .bCS (bcs[9]), | |
1959 | .bRAS (bras[9]), | |
1960 | .bCAS (bcas[9]), | |
1961 | .bWE (bwe[9]), | |
1962 | .BA (ba), | |
1963 | .Addr (addr), | |
1964 | .DQ (dq[35:32]), | |
1965 | .DQS (dqs[9]), | |
1966 | .bDQS (bdqs[9]), | |
1967 | .ODT (odt[9]), | |
1968 | .areset (areset[9]), | |
1969 | .term (term[9])); | |
1970 | ||
1971 | ddr2_dram dram_10 ( .CK (dram_clk), | |
1972 | .bCK (~dram_clk), | |
1973 | .CKE (cke[10]), | |
1974 | .bCS (bcs[10]), | |
1975 | .bRAS (bras[10]), | |
1976 | .bCAS (bcas[10]), | |
1977 | .bWE (bwe[10]), | |
1978 | .BA (ba), | |
1979 | .Addr (addr), | |
1980 | .DQ (dq[39:36]), | |
1981 | .DQS (dqs[10]), | |
1982 | .bDQS (bdqs[10]), | |
1983 | .ODT (odt[10]), | |
1984 | .areset (areset[10]), | |
1985 | .term (term[10])); | |
1986 | ||
1987 | ddr2_dram dram_11 ( .CK (dram_clk), | |
1988 | .bCK (~dram_clk), | |
1989 | .CKE (cke[11]), | |
1990 | .bCS (bcs[11]), | |
1991 | .bRAS (bras[11]), | |
1992 | .bCAS (bcas[11]), | |
1993 | .bWE (bwe[11]), | |
1994 | .BA (ba), | |
1995 | .Addr (addr), | |
1996 | .DQ (dq[43:40]), | |
1997 | .DQS (dqs[11]), | |
1998 | .bDQS (bdqs[11]), | |
1999 | .ODT (odt[11]), | |
2000 | .areset (areset[11]), | |
2001 | .term (term[11])); | |
2002 | ||
2003 | ddr2_dram dram_12 ( .CK (dram_clk), | |
2004 | .bCK (~dram_clk), | |
2005 | .CKE (cke[12]), | |
2006 | .bCS (bcs[12]), | |
2007 | .bRAS (bras[12]), | |
2008 | .bCAS (bcas[12]), | |
2009 | .bWE (bwe[12]), | |
2010 | .BA (ba), | |
2011 | .Addr (addr), | |
2012 | .DQ (dq[47:44]), | |
2013 | .DQS (dqs[12]), | |
2014 | .bDQS (bdqs[12]), | |
2015 | .areset (areset[12]), | |
2016 | .ODT (odt[12]), | |
2017 | .term (term[12])); | |
2018 | ||
2019 | ddr2_dram dram_13 ( .CK (dram_clk), | |
2020 | .bCK (~dram_clk), | |
2021 | .CKE (cke[13]), | |
2022 | .bCS (bcs[13]), | |
2023 | .bRAS (bras[13]), | |
2024 | .bCAS (bcas[13]), | |
2025 | .bWE (bwe[13]), | |
2026 | .BA (ba), | |
2027 | .Addr (addr), | |
2028 | .DQ (dq[51:48]), | |
2029 | .DQS (dqs[13]), | |
2030 | .bDQS (bdqs[13]), | |
2031 | .ODT (odt[13]), | |
2032 | .areset (areset[13]), | |
2033 | .term (term[13])); | |
2034 | ||
2035 | ddr2_dram dram_14 ( .CK (dram_clk), | |
2036 | .bCK (~dram_clk), | |
2037 | .CKE (cke[14]), | |
2038 | .bCS (bcs[14]), | |
2039 | .bRAS (bras[14]), | |
2040 | .bCAS (bcas[14]), | |
2041 | .bWE (bwe[14]), | |
2042 | .BA (ba), | |
2043 | .Addr (addr), | |
2044 | .DQ (dq[55:52]), | |
2045 | .DQS (dqs[14]), | |
2046 | .bDQS (bdqs[14]), | |
2047 | .areset (areset[14]), | |
2048 | .ODT (odt[14]), | |
2049 | .term (term[14])); | |
2050 | ||
2051 | ddr2_dram dram_15 ( .CK (dram_clk), | |
2052 | .bCK (~dram_clk), | |
2053 | .CKE (cke[15]), | |
2054 | .bCS (bcs[15]), | |
2055 | .bRAS (bras[15]), | |
2056 | .bCAS (bcas[15]), | |
2057 | .bWE (bwe[15]), | |
2058 | .BA (ba), | |
2059 | .Addr (addr), | |
2060 | .DQ (dq[59:56]), | |
2061 | .DQS (dqs[15]), | |
2062 | .bDQS (bdqs[15]), | |
2063 | .ODT (odt[15]), | |
2064 | .areset (areset[15]), | |
2065 | .term (term[15])); | |
2066 | ||
2067 | ddr2_dram dram_16 ( .CK (dram_clk), | |
2068 | .bCK (~dram_clk), | |
2069 | .CKE (cke[16]), | |
2070 | .bCS (bcs[16]), | |
2071 | .bRAS (bras[16]), | |
2072 | .bCAS (bcas[16]), | |
2073 | .bWE (bwe[16]), | |
2074 | .BA (ba), | |
2075 | .Addr (addr), | |
2076 | .DQ (dq[63:60]), | |
2077 | .DQS (dqs[16]), | |
2078 | .bDQS (bdqs[16]), | |
2079 | .ODT (odt[16]), | |
2080 | .areset (areset[16]), | |
2081 | .term (term[16])); | |
2082 | ||
2083 | ddr2_dram dram_17 ( .CK (dram_clk), | |
2084 | .bCK (~dram_clk), | |
2085 | .CKE (cke[17]), | |
2086 | .bCS (bcs[17]), | |
2087 | .bRAS (bras[17]), | |
2088 | .bCAS (bcas[17]), | |
2089 | .bWE (bwe[17]), | |
2090 | .BA (ba), | |
2091 | .Addr (addr), | |
2092 | .DQ (dq[67:64]), | |
2093 | .DQS (dqs[17]), | |
2094 | .bDQS (bdqs[17]), | |
2095 | .ODT (odt[17]), | |
2096 | .areset (areset[17]), | |
2097 | .term (term[17])); | |
2098 | ||
2099 | ||
2100 | ddr2_dram dram_18 ( .CK (dram_clk), | |
2101 | .bCK (~dram_clk), | |
2102 | .CKE (cke[18]), | |
2103 | .bCS (bcs[18]), | |
2104 | .bRAS (bras[18]), | |
2105 | .bCAS (bcas[18]), | |
2106 | .bWE (bwe[18]), | |
2107 | .BA (ba), | |
2108 | .Addr (addr), | |
2109 | .DQ (dq[71:68]), | |
2110 | .DQS (dqs[18]), | |
2111 | .bDQS (bdqs[18]), | |
2112 | .ODT (odt[18]), | |
2113 | .areset (areset[18]), | |
2114 | .term (term[18])); | |
2115 | ||
2116 | `endif // DRAM_SAT | |
2117 | `endif // x4 | |
2118 | `endif // CAD_DDR2_DRAM | |
2119 | ||
2120 | // !!!!! If we run on AXIS HW, we will not need tasks to initialize the DDR2 dram | |
2121 | ||
2122 | ||
2123 | `ifdef AXIS_DDR2_MODEL | |
2124 | `else | |
2125 | ||
2126 | task update_cke; | |
2127 | input value; | |
2128 | ||
2129 | begin | |
2130 | cke_rank0_reg[18:1]={18{value}}; | |
2131 | cke_rank1_reg[18:1]={18{value}}; | |
2132 | end | |
2133 | ||
2134 | endtask | |
2135 | ||
2136 | // nop command emulation | |
2137 | task nop; | |
2138 | input dummy; | |
2139 | begin | |
2140 | bcs_reg[18:0]=19'h0; | |
2141 | bcas_reg[18:0]=19'h7ffff; | |
2142 | bras_reg[18:0]=19'h7ffff; | |
2143 | bwe_reg[18:0]=19'h7ffff; | |
2144 | end | |
2145 | endtask | |
2146 | ||
2147 | // refresh command emulation | |
2148 | task refresh; | |
2149 | input dummy; | |
2150 | begin | |
2151 | ||
2152 | bcs_reg[18:0]=19'h0; | |
2153 | bcas_reg[18:0]=19'b0; | |
2154 | bras_reg[18:0]=19'b0; | |
2155 | bwe_reg[18:0]=19'h7ffff; | |
2156 | end | |
2157 | endtask | |
2158 | ||
2159 | ||
2160 | // precharge command emulation | |
2161 | ||
2162 | task precharge; | |
2163 | ||
2164 | input a10; | |
2165 | input [2:0] ba_in; | |
2166 | ||
2167 | begin | |
2168 | bcs_reg[18:0]=19'h0; | |
2169 | bcas_reg[18:0]=19'h7ffff; | |
2170 | bras_reg[18:0]=19'b0; | |
2171 | bwe_reg[18:0]=19'b0; | |
2172 | ba_reg=ba_in; | |
2173 | ||
2174 | addr_reg[10]=a10; | |
2175 | end | |
2176 | endtask | |
2177 | ||
2178 | // simulation of delay cycles | |
2179 | task delays; | |
2180 | ||
2181 | input [9:0] cycle; | |
2182 | integer index; | |
2183 | ||
2184 | begin | |
2185 | for(index=1; index<=cycle; index=index+1) | |
2186 | begin | |
2187 | @(posedge dram_clk); | |
2188 | end | |
2189 | ||
2190 | end | |
2191 | endtask | |
2192 | ||
2193 | ||
2194 | // Self Refresh Entry by AMB | |
2195 | task Self_Refresh_Entry; | |
2196 | begin | |
2197 | `ifdef AXIS_FBDIMM_HW | |
2198 | `else | |
2199 | `PR_ALWAYS ("dram_init",`DBG_0,"FBDIMM: Self Refresh Entry Started\n"); | |
2200 | `endif | |
2201 | ||
2202 | // Step:1 Wait tCKE then take all CKE signals high | |
2203 | delays(3); | |
2204 | cke_rank0_reg[18:0]=19'h7ffff; // keep CKE high | |
2205 | cke_rank1_reg[18:0]=19'h7ffff; // keep CKE high | |
2206 | ||
2207 | // Step: 2 Wait tXSNR(tRFC + 10ns for ddr2) | |
2208 | delays(3); | |
2209 | delays(10); | |
2210 | ||
2211 | // Note: OD must be low during the previous two steps | |
2212 | ||
2213 | // Step:3 Issue precharge all to all ranks | |
2214 | precharge(1,0); | |
2215 | ||
2216 | // step:4 Wait tRFC | |
2217 | delays(1); // tRP | |
2218 | nop(0); | |
2219 | delays(1); | |
2220 | ||
2221 | // Step: 5 Assure ODT signals are low | |
2222 | odt_reg[18:1] = 0; | |
2223 | ||
2224 | // Step: 6 Issue enter self refresh | |
2225 | refresh(0); | |
2226 | delays(1); | |
2227 | ||
2228 | // step:7 Disable clocks | |
2229 | cke_rank0_reg[18:1]= 0; | |
2230 | cke_rank1_reg[18:1]= 0; | |
2231 | ||
2232 | `ifdef AXIS_FBDIMM_HW | |
2233 | `else | |
2234 | `PR_ALWAYS ("dram_init",`DBG_0,"FBDIMM: DRAMs in self refresh mode\n"); | |
2235 | `endif | |
2236 | end | |
2237 | ||
2238 | endtask | |
2239 | ||
2240 | ||
2241 | // MRS comand emulation | |
2242 | task mrs_command; | |
2243 | ||
2244 | input [2:0] ba_in; | |
2245 | input [15:0] address_in; | |
2246 | ||
2247 | begin | |
2248 | ||
2249 | ||
2250 | bcs_reg[18:1]=0; | |
2251 | bcas_reg[18:1]=0; | |
2252 | bras_reg[18:1]=0; | |
2253 | bwe_reg[18:1]=0; | |
2254 | ||
2255 | ba_reg=ba_in; | |
2256 | addr_reg=address_in; | |
2257 | end | |
2258 | endtask | |
2259 | `endif //ifdef AXIS_DDR2_MODEL | |
2260 | ||
2261 | ||
2262 | `ifdef STINGRAY | |
2263 | ||
2264 | `ifdef AXIS_DDR2_MODEL | |
2265 | `else | |
2266 | // Initialization task for DRAMs | |
2267 | task init_dram; | |
2268 | input dummy; | |
2269 | begin | |
2270 | `ifdef AXIS_FBDIMM_HW | |
2271 | `else | |
2272 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init started\n"); | |
2273 | `endif | |
2274 | // Step:1 | |
2275 | ||
2276 | `ifdef AXIS_FBDIMM_HW | |
2277 | `else | |
2278 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : CKE & ODT Driven Low\n"); | |
2279 | `endif | |
2280 | bcs_reg[18:1]=0; // disable the chip | |
2281 | odt_reg[18:1]=0; // kep ODT low | |
2282 | cke_rank0_reg[18:1]=0; // keep CKE low | |
2283 | cke_rank1_reg[18:1]=0; // keep CKE low | |
2284 | @(posedge dram_clk); | |
2285 | ||
2286 | ||
2287 | // Step: 2 | |
2288 | bcs_reg[18:0]=19'h7ffff; | |
2289 | bcas_reg[18:0]=19'h7ffff; | |
2290 | bras_reg[18:0]= 19'h7ffff; | |
2291 | bwe_reg[18:0]=19'h7ffff; | |
2292 | ba_reg[2:0]=0; | |
2293 | addr_reg=0; | |
2294 | dqs_reg[9:0]=10'h0; | |
2295 | // Step:3 | |
2296 | `ifdef AXIS_FBDIMM_HW | |
2297 | `else | |
2298 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : NOP Driven on DRAM Control Signals\n"); | |
2299 | `endif | |
2300 | nop(0); | |
2301 | ||
2302 | delays(21); | |
2303 | ||
2304 | `ifdef AXIS_FBDIMM_HW | |
2305 | `else | |
2306 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : CKE Driven High\n"); | |
2307 | `endif | |
2308 | cke_rank0_reg[18:0]= 19'h7ffff; | |
2309 | cke_rank1_reg[18:0]= 19'h7ffff; | |
2310 | ||
2311 | `ifdef AXIS_FBDIMM_HW | |
2312 | `else | |
2313 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : Waiting for Delay 1 to End\n"); | |
2314 | `endif | |
2315 | delays(45); // wait 400ns | |
2316 | ||
2317 | ||
2318 | // Step: 4 | |
2319 | `ifdef AXIS_FBDIMM_HW | |
2320 | `else | |
2321 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : Precharge All\n"); | |
2322 | `endif | |
2323 | precharge(1,0); | |
2324 | delays(1); // tRP | |
2325 | nop(0); | |
2326 | delays(7); // changed for ST | |
2327 | ||
2328 | // Step: 5 | |
2329 | `ifdef AXIS_FBDIMM_HW | |
2330 | `else | |
2331 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : Issue EMRS(2)\n"); | |
2332 | `endif | |
2333 | mrs_command(3'b010, 0); // issue mrs2 | |
2334 | delays(1); | |
2335 | nop(0); | |
2336 | delays(1); // tMRD | |
2337 | ||
2338 | ||
2339 | // Step: 6 | |
2340 | `ifdef AXIS_FBDIMM_HW | |
2341 | `else | |
2342 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : Issue EMRS(3)\n"); | |
2343 | `endif | |
2344 | mrs_command(3'b011, 0); // issue mrs3 | |
2345 | delays(1); | |
2346 | nop(0); | |
2347 | delays(1); // tMRD | |
2348 | ||
2349 | ||
2350 | // Step: 7 | |
2351 | `ifdef AXIS_FBDIMM_HW | |
2352 | `else | |
2353 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : EMRS(1) to enable DLL\n"); | |
2354 | `endif | |
2355 | mrs_command(3'b001,{drc[6:4],1'b0,1'b0,1'b0}); // emrs to enable dll | |
2356 | delays(1); | |
2357 | nop(0); | |
2358 | delays(1); // tMRD | |
2359 | ||
2360 | // Step: 8 | |
2361 | `ifdef AXIS_FBDIMM_HW | |
2362 | `else | |
2363 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : MRS for DLL Reset\n"); | |
2364 | `endif | |
2365 | ||
2366 | mrs_command(3'b000, {3'b101,1'b1,1'b0,drc[2:0],1'b0,2'b01,drc[8]}); | |
2367 | delays(1); | |
2368 | nop(0); | |
2369 | delays(1); // tMRD | |
2370 | ||
2371 | ||
2372 | // Step: 9 | |
2373 | `ifdef AXIS_FBDIMM_HW | |
2374 | `else | |
2375 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : Precharge all\n"); | |
2376 | `endif | |
2377 | precharge(1,0); | |
2378 | delays(1); // tRP | |
2379 | nop(0); | |
2380 | delays(3); | |
2381 | ||
2382 | // step: 10 | |
2383 | `ifdef AXIS_FBDIMM_HW | |
2384 | `else | |
2385 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : Refresh\n"); | |
2386 | `endif | |
2387 | refresh(0); | |
2388 | delays(1); | |
2389 | nop(0); | |
2390 | delays(42); // tRFC changed for ST | |
2391 | refresh(0); | |
2392 | delays(1); | |
2393 | nop(0); | |
2394 | delays(42); // tRFC changed for ST | |
2395 | refresh(0); | |
2396 | delays(1); | |
2397 | nop(0); | |
2398 | delays(42); // tRFC changed for ST | |
2399 | ||
2400 | // step: 11 | |
2401 | `ifdef AXIS_FBDIMM_HW | |
2402 | `else | |
2403 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : MRS to set A8 low to initialize device operation\n"); | |
2404 | `endif | |
2405 | ||
2406 | mrs_command(3'b000, {3'b101,1'b0,1'b0,drc[2:0],1'b0,2'b01,drc[8]}); | |
2407 | delays(1); // tMRD | |
2408 | nop(0); | |
2409 | ||
2410 | delays(200); // make sure 200 cycles are consumed | |
2411 | ||
2412 | ||
2413 | // Step:12 | |
2414 | `ifdef AXIS_FBDIMM_HW | |
2415 | `else | |
2416 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : EMRS1 for OCD default comand\n"); | |
2417 | `endif | |
2418 | mrs_command(3'b001, {3'b111,1'b0,drc[6:4],3'b000}); | |
2419 | delays(1); | |
2420 | nop(0); | |
2421 | delays(1); | |
2422 | `ifdef AXIS_FBDIMM_HW | |
2423 | `else | |
2424 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : EMRS1 to OCD Calibration Mode Exit\n"); | |
2425 | `endif | |
2426 | mrs_command(3'b001, {3'b000,1'b0,drc[6:4], 3'b000}); // OCD exit | |
2427 | delays(1); | |
2428 | nop(0); | |
2429 | `ifdef AXIS_FBDIMM_HW | |
2430 | `else | |
2431 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init ended\n"); | |
2432 | `endif | |
2433 | end | |
2434 | ||
2435 | endtask | |
2436 | `endif //AXIS_DDR2_MODEL | |
2437 | ||
2438 | `else | |
2439 | ||
2440 | `ifdef AXIS_DDR2_MODEL | |
2441 | `else | |
2442 | // Initialization task for DRAMs | |
2443 | task init_dram; | |
2444 | input dummy; | |
2445 | begin | |
2446 | `ifdef AXIS_FBDIMM_HW | |
2447 | `else | |
2448 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init started\n"); | |
2449 | `endif // AXIS_FBDIMM_HW | |
2450 | // Step:1 | |
2451 | `ifdef AXIS_FBDIMM_HW | |
2452 | `else | |
2453 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : St1: CKE & ODT Driven Low\n"); | |
2454 | `endif | |
2455 | bcs_reg[18:1]=0; // disable the chip | |
2456 | odt_reg[18:1]=0; // kep ODT low | |
2457 | cke_rank0_reg[18:1]=0; // keep CKE low | |
2458 | cke_rank1_reg[18:1]=0; // keep CKE low | |
2459 | @(posedge dram_clk); | |
2460 | ||
2461 | ||
2462 | // Step: 2 | |
2463 | `ifdef AXIS_FBDIMM_HW | |
2464 | `else | |
2465 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : St2: Everything high on dram interface\n"); | |
2466 | `endif | |
2467 | bcs_reg[18:0]=19'h7ffff; | |
2468 | bcas_reg[18:0]=19'h7ffff; | |
2469 | bras_reg[18:0]= 19'h7ffff; | |
2470 | bwe_reg[18:0]=19'h7ffff; | |
2471 | ba_reg[2:0]=0; | |
2472 | addr_reg=0; | |
2473 | dqs_reg[9:0]=10'h0; | |
2474 | ||
2475 | ||
2476 | // Step:3 | |
2477 | `ifdef AXIS_FBDIMM_HW | |
2478 | `else | |
2479 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : St3: NOP Driven on DRAM Control Signals\n"); | |
2480 | `endif | |
2481 | nop(0); | |
2482 | ||
2483 | delays(21); | |
2484 | ||
2485 | cke_rank0_reg[18:0]= 19'h7ffff; | |
2486 | cke_rank1_reg[18:0]= 19'h7ffff; | |
2487 | ||
2488 | delays(45); // wait 400ns | |
2489 | ||
2490 | ||
2491 | // Step: 4 | |
2492 | `ifdef AXIS_FBDIMM_HW | |
2493 | `else | |
2494 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init: St4: Precharge\n"); | |
2495 | `endif | |
2496 | precharge(1,0); | |
2497 | delays(1); // tRP | |
2498 | nop(0); | |
2499 | delays(3); | |
2500 | ||
2501 | // Step: 5 | |
2502 | `ifdef AXIS_FBDIMM_HW | |
2503 | `else | |
2504 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : St5: Mrs2\n"); | |
2505 | `endif | |
2506 | mrs_command(3'b010, 0); // issue mrs2 | |
2507 | delays(1); | |
2508 | nop(0); | |
2509 | delays(2); // tMRD | |
2510 | ||
2511 | ||
2512 | // Step: 6 | |
2513 | `ifdef AXIS_FBDIMM_HW | |
2514 | `else | |
2515 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : St6: mrs3\n"); | |
2516 | `endif | |
2517 | mrs_command(3'b011, 0); // issue mrs3 | |
2518 | delays(1); | |
2519 | nop(0); | |
2520 | delays(2); // tMRD | |
2521 | ||
2522 | ||
2523 | // Step: 7 | |
2524 | `ifdef AXIS_FBDIMM_HW | |
2525 | `else | |
2526 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : St7: Emrs1\n"); | |
2527 | `endif | |
2528 | mrs_command(3'b001,{drc[6:4],1'b0,1'b0,1'b0}); // emrs to enable dll | |
2529 | delays(1); | |
2530 | nop(0); | |
2531 | delays(2); // tMRD | |
2532 | ||
2533 | // Step: 8 | |
2534 | `ifdef AXIS_FBDIMM_HW | |
2535 | `else | |
2536 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : St8: Mrs\n"); | |
2537 | `endif | |
2538 | if ( sng_channel ) | |
2539 | mrs_command(3'b000, {3'b001,1'b1,1'b0,drc[2:0],1'b0,3'b011}); // BL = 8 | |
2540 | else | |
2541 | mrs_command(3'b000, {3'b001,1'b1,1'b0,drc[2:0],1'b0,2'b01,drc[8]}); | |
2542 | ||
2543 | delays(1); | |
2544 | nop(0); | |
2545 | delays(2); // tMRD | |
2546 | ||
2547 | ||
2548 | // Step: 9 | |
2549 | `ifdef AXIS_FBDIMM_HW | |
2550 | `else | |
2551 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init : St9: Precharge\n"); | |
2552 | `endif | |
2553 | precharge(1,0); | |
2554 | delays(1); // tRP | |
2555 | nop(0); | |
2556 | delays(3); | |
2557 | ||
2558 | // step: 10 | |
2559 | refresh(0); | |
2560 | delays(1); | |
2561 | nop(0); | |
2562 | delays(31); // tRFC | |
2563 | refresh(0); | |
2564 | delays(1); | |
2565 | nop(0); | |
2566 | delays(31); // tRFC | |
2567 | refresh(0); | |
2568 | delays(1); | |
2569 | nop(0); | |
2570 | delays(31); // tRFC | |
2571 | ||
2572 | // step: 11 | |
2573 | ||
2574 | if ( sng_channel ) | |
2575 | mrs_command(3'b000, {3'b001,1'b0,1'b0,drc[2:0],1'b0,3'b011}); // BL = 8 | |
2576 | else | |
2577 | mrs_command(3'b000, {3'b001,1'b0,1'b0,3'b011,1'b0,2'b01,drc[8]}); | |
2578 | delays(1); // tMRD | |
2579 | nop(0); | |
2580 | ||
2581 | delays(200); // make sure 200 cycles are consumed | |
2582 | ||
2583 | ||
2584 | // Step:12 | |
2585 | mrs_command(3'b001, {3'b111,7'b11000}); | |
2586 | delays(1); | |
2587 | nop(0); | |
2588 | delays(2); | |
2589 | mrs_command(3'b001, {3'b000,7'b11000}); // OCD exit | |
2590 | delays(1); | |
2591 | nop(0); | |
2592 | `ifdef AXIS_FBDIMM_HW | |
2593 | `else | |
2594 | `PR_ALWAYS ("dram_init",`DBG_4,"FBDIMM: DRAM Init ended\n"); | |
2595 | `endif | |
2596 | end | |
2597 | ||
2598 | endtask | |
2599 | `endif // AXIS_DDR2_MODEL | |
2600 | ||
2601 | `endif // STINGRAY | |
2602 | ||
2603 | reg start_init_dram; | |
2604 | ||
2605 | // Initialization | |
2606 | initial begin | |
2607 | ||
2608 | `ifdef AXIS_FBDIMM_HW | |
2609 | `else | |
2610 | if ( $test$plusargs("fbdimm_dbg_4")) | |
2611 | $ch_dispmon("dram_init",`DBG_4,1); | |
2612 | ||
2613 | if ( $test$plusargs("fbdimm_dbg")) | |
2614 | $ch_dispmon("dram",`DBG_0,1); | |
2615 | `endif // AXIS_FBDIMM_HW | |
2616 | ||
2617 | bcs_reg[18:0] = 19'h0; | |
2618 | bcas_reg[18:0] = 19'h7ffff; | |
2619 | bwe_reg[18:0] = 19'h7ffff; | |
2620 | bras_reg[18:0] = 19'h7ffff; | |
2621 | ||
2622 | start_init_dram=0; | |
2623 | drams_on=0; | |
2624 | write_command=0; | |
2625 | cke_rank0_reg=0; | |
2626 | cke_rank1_reg=0; | |
2627 | odt_reg = 0; | |
2628 | ||
2629 | RS=0; | |
2630 | `ifdef STINGRAY | |
2631 | @(posedge reset) | |
2632 | stall_pipe=0; | |
2633 | `else | |
2634 | ||
2635 | `ifdef PALLADIUM | |
2636 | `else | |
2637 | #50; | |
2638 | `endif | |
2639 | ||
2640 | cke_rank0_reg=1; | |
2641 | cke_rank1_reg=1; | |
2642 | //@(negedge init); | |
2643 | ||
2644 | ||
2645 | @(posedge frm_boundary); | |
2646 | stall_pipe=0; | |
2647 | ||
2648 | start_init_dram=1; | |
2649 | `endif // STINGRAY | |
2650 | ||
2651 | end | |
2652 | ||
2653 | always@(posedge start_init_dram) | |
2654 | begin | |
2655 | ||
2656 | `ifdef AXIS_FBDIMM_HW | |
2657 | `ifdef AXIS_DDR2_MODEL | |
2658 | `else | |
2659 | init_dram(0); | |
2660 | `endif // AXIS_DDR2_MODEL | |
2661 | drams_on=1; | |
2662 | ||
2663 | `else | |
2664 | if ( !$test$plusargs("AMB_DRAM_INIT")) | |
2665 | begin | |
2666 | RS=0; // initialize rank 0 first | |
2667 | `ifdef AXIS_DDR2_MODEL | |
2668 | `else | |
2669 | init_dram(0); | |
2670 | `endif // ifdef AXIS_DDR2_MODEL | |
2671 | end | |
2672 | drams_on=1; | |
2673 | `endif //AXIS_FBDIMM_HW | |
2674 | ||
2675 | end | |
2676 | ||
2677 | ||
2678 | ||
2679 | endmodule |