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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fbdimm_clk_gen.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifdef STINGRAY | |
36 | `timescale 1ns/1ps | |
37 | `endif | |
38 | ||
39 | module fbdimm_clk_gen(sclk,frm_start,reset_n,dram_clk,dram_2x_clk, link_clk,ref_2x_clk,clk_int,clk_int_2x , frm_boundary_sb); | |
40 | ||
41 | input sclk; | |
42 | input frm_start; | |
43 | input frm_boundary_sb; | |
44 | input reset_n; | |
45 | output dram_clk; | |
46 | output dram_2x_clk; | |
47 | output link_clk; | |
48 | output ref_2x_clk; | |
49 | output clk_int; | |
50 | output clk_int_2x; | |
51 | ||
52 | ||
53 | reg dram_clk_reg,dram_2x_clk_reg, link_clk_reg,ref_2x_clk_reg,ch_mon_clk_reg,clk_int_reg,clk_int_2x_reg; | |
54 | reg dtm_dram_clk_reg,dtm_dram_2x_clk_reg; | |
55 | ||
56 | reg st_dram_clk_reg,st_dram_2x_clk_reg, st_link_clk_reg,st_ref_2x_clk_reg,st_ch_mon_clk_reg,st_clk_int_reg,st_clk_int_2x_reg; | |
57 | reg st_dtm_dram_clk_reg,st_dtm_dram_2x_clk_reg; | |
58 | ||
59 | reg vf_dtm_enabled_reg; | |
60 | ||
61 | `ifdef AXIS //_FBDIMM_HW | |
62 | `else | |
63 | real time1,time2,dram_clk_period; | |
64 | real time1_2x,time2_2x,dram_2x_clk_period; | |
65 | real time1_l,time2_l,link_clk_period; | |
66 | real time1_ch_mon,time2_ch_mon,ch_mon_clk_period; | |
67 | real time1_r,time2_r,ref_2x_clk_period; | |
68 | real time1_i,time2_i,clk_int_period; | |
69 | real time1_i_2x,time2_i_2x,clk_int_2x_period; | |
70 | ||
71 | real st_time1,st_time2,st_dram_clk_period; | |
72 | real st_time1_2x,st_time2_2x,st_dram_2x_clk_period; | |
73 | real st_time1_l,st_time2_l,st_link_clk_period; | |
74 | real st_time1_i,st_time2_i,st_clk_int_period; | |
75 | ||
76 | real my_clk_int_period; | |
77 | real my_clk_int_2x_period; | |
78 | ||
79 | `endif | |
80 | ||
81 | ||
82 | // for stingray, we will create dram clk which is | |
83 | // twice the the freq of the input clk which will be | |
84 | // reference clk | |
85 | ||
86 | //`ifdef STINGRAY | |
87 | // We will use the same clock generator for Stingray from now on. Sept8 | |
88 | //`else | |
89 | ||
90 | // AXIS clocks will be different | |
91 | `ifdef AXIS //_FBDIMM_HW | |
92 | ||
93 | reg [3:0] clk_cnt; | |
94 | reg [3:0] clk_cnt2; | |
95 | reg [3:0] clk_cnt_2; | |
96 | ||
97 | reg clock_en; | |
98 | initial begin | |
99 | clk_cnt=4'h0; | |
100 | clk_cnt2=4'h0; | |
101 | end | |
102 | initial clock_en=1'b0; | |
103 | always @(negedge sclk) begin | |
104 | if (clk_cnt2 < 4'd8 & clock_en) | |
105 | clk_cnt2<=clk_cnt2+4'b1; | |
106 | end | |
107 | always @(negedge sclk) begin | |
108 | if (frm_start) | |
109 | clock_en=1'b1; | |
110 | end | |
111 | ||
112 | `ifdef AXIS_FBDIMM_NO_FSR | |
113 | wire x2sclk; | |
114 | axis_pulse(x2sclk,sclk); | |
115 | always @(posedge x2sclk) begin | |
116 | `else | |
117 | always @(negedge sclk) begin | |
118 | `endif | |
119 | if (clk_cnt < 4'd11 & clk_cnt2 == 4'd8) | |
120 | clk_cnt=clk_cnt+4'b1; | |
121 | else | |
122 | clk_cnt=4'b0; | |
123 | end | |
124 | ||
125 | `ifdef AXIS_FBDIMM_NO_FSR | |
126 | ||
127 | //always@(tb_top.dram_2x_clk) | |
128 | wire x2clk; | |
129 | axis_pulse(x2clk, tb_top.dram_2x_clk); | |
130 | always@(posedge x2clk) | |
131 | begin | |
132 | if (clk_cnt < 4'd11 & clk_cnt2 == 4'd8) | |
133 | clk_cnt_2=clk_cnt_2+4'b1; | |
134 | else | |
135 | clk_cnt_2=4'b0; | |
136 | end | |
137 | ||
138 | assign dram_2x_clk = ~ clk_cnt_2[0]; | |
139 | ||
140 | assign dram_clk = clk_cnt_2[1]; | |
141 | assign ref_2x_clk = ~dram_clk; | |
142 | ||
143 | `else | |
144 | assign dram_2x_clk = (clk_cnt < 4'd3) | ((clk_cnt > 4'd5) & (clk_cnt <4'd9)) ? 1 : 0; | |
145 | assign dram_clk = (clk_cnt < 4'd6) ? 0 : 1; | |
146 | assign ref_2x_clk = (clk_cnt < 4'd6) ? 1 : 0; | |
147 | `endif | |
148 | ||
149 | assign link_clk = sclk; // For AXIS model make sure sclk is not SystemClock but link_clk period | |
150 | ||
151 | `ifdef AXIS_FBDIMM_NO_FSR | |
152 | assign clk_int = sclk; //(clk_cnt < 4'd2 ) | ((clk_cnt > 4'd3) & (clk_cnt < 4'd6)) | ((clk_cnt > 4'd7) & (clk_cnt < 4'd10))? 1 : 0; | |
153 | `else | |
154 | assign clk_int = (clk_cnt < 4'd2 ) | ((clk_cnt > 4'd3) & (clk_cnt < 4'd6)) | ((clk_cnt > 4'd7) & (clk_cnt < 4'd10))? 1 : 0; | |
155 | `endif | |
156 | ||
157 | assign clk_int_2x = 0; | |
158 | ||
159 | ||
160 | ||
161 | ||
162 | ||
163 | `else | |
164 | ||
165 | ||
166 | //`ifdef STINGRAY_RESTART_CLK | |
167 | ||
168 | ||
169 | always@(posedge reset_n ) | |
170 | begin | |
171 | ||
172 | @(negedge sclk); | |
173 | st_time1_i = $realtime; | |
174 | st_time1=$realtime; | |
175 | st_time1_2x=$realtime; | |
176 | st_time1_l=$realtime; | |
177 | @(negedge sclk); | |
178 | st_time2_i = $realtime; | |
179 | st_time2=$realtime; | |
180 | st_time2_2x=$realtime; | |
181 | st_time2_l=$realtime; | |
182 | ||
183 | st_clk_int_reg=1; | |
184 | st_clk_int_period = st_time2_i - st_time1_i; | |
185 | ||
186 | ||
187 | st_link_clk_reg=1; | |
188 | st_link_clk_period=(st_time2_l-st_time1_l); | |
189 | ||
190 | @(negedge frm_start); | |
191 | st_dram_clk_reg=1; | |
192 | st_dram_clk_period = st_time2 - st_time1; | |
193 | ||
194 | st_dram_2x_clk_reg=1; | |
195 | st_dram_2x_clk_period = st_time2_2x - st_time1_2x; | |
196 | end | |
197 | ||
198 | ||
199 | always@(st_clk_int_reg) | |
200 | st_clk_int_reg <= #(st_clk_int_period/12) ~st_clk_int_reg; | |
201 | ||
202 | always@(st_dram_clk_reg) | |
203 | st_dram_clk_reg <= #(st_dram_2x_clk_period/4) ~st_dram_clk_reg; | |
204 | ||
205 | always@(st_dram_2x_clk_reg) | |
206 | st_dram_2x_clk_reg <= #(st_dram_2x_clk_period/8) ~st_dram_2x_clk_reg; | |
207 | ||
208 | always@(st_link_clk_reg) | |
209 | st_link_clk_reg <= #(st_link_clk_period/48) ~st_link_clk_reg; | |
210 | ||
211 | //`else | |
212 | ||
213 | initial begin | |
214 | ||
215 | clk_int_reg=0; | |
216 | ||
217 | #10; | |
218 | @(posedge sclk); | |
219 | time1_i=$realtime; | |
220 | @(posedge sclk); | |
221 | time2_i=$realtime; | |
222 | ||
223 | clk_int_period=(time2_i-time1_i)/6; | |
224 | ||
225 | clk_int_reg=1; | |
226 | ||
227 | ||
228 | if ( ($test$plusargs("DTM_ENABLED")) || ($test$plusargs("VF_DTM_ENABLED")) ) | |
229 | my_clk_int_period = clk_int_period; | |
230 | else my_clk_int_period = clk_int_period/2; | |
231 | ||
232 | forever begin #(my_clk_int_period) clk_int_reg = ~clk_int_reg; end | |
233 | ||
234 | ||
235 | //`ifdef DTM_ENABLED | |
236 | // forever begin #(clk_int_period) clk_int_reg = ~clk_int_reg; end | |
237 | //`else | |
238 | // forever begin #(clk_int_period/2) clk_int_reg = ~clk_int_reg; end | |
239 | //`endif | |
240 | ||
241 | end | |
242 | ||
243 | initial begin | |
244 | vf_dtm_enabled_reg = 1'b0; | |
245 | if ($test$plusargs("VF_DTM_ENABLED")) | |
246 | vf_dtm_enabled_reg = 1'b1; | |
247 | end | |
248 | ||
249 | initial begin | |
250 | ||
251 | clk_int_2x_reg=0; | |
252 | ||
253 | #10; | |
254 | @(posedge sclk); | |
255 | time1_i_2x=$realtime; | |
256 | @(posedge sclk); | |
257 | time2_i_2x=$realtime; | |
258 | ||
259 | clk_int_2x_period=(time2_i_2x-time1_i_2x)/12; | |
260 | ||
261 | clk_int_2x_reg=1; | |
262 | ||
263 | if ( ($test$plusargs("DTM_ENABLED")) || ($test$plusargs("VF_DTM_ENABLED")) ) | |
264 | my_clk_int_2x_period = clk_int_2x_period; | |
265 | else | |
266 | my_clk_int_2x_period = clk_int_2x_period/2; | |
267 | ||
268 | forever begin #(my_clk_int_2x_period) clk_int_2x_reg = ~clk_int_2x_reg; end | |
269 | ||
270 | //`ifdef DTM_ENABLED | |
271 | // forever begin #(clk_int_2x_period) clk_int_2x_reg = ~clk_int_2x_reg; end | |
272 | //`else | |
273 | // forever begin #(clk_int_2x_period/2) clk_int_2x_reg = ~clk_int_2x_reg; end | |
274 | //`endif | |
275 | ||
276 | end | |
277 | ||
278 | initial begin | |
279 | ||
280 | ch_mon_clk_reg=0; | |
281 | ||
282 | @(posedge sclk); | |
283 | time1_ch_mon=$realtime; | |
284 | @(posedge sclk); | |
285 | time2_ch_mon=$realtime; | |
286 | ||
287 | ch_mon_clk_period=(time2_ch_mon-time1_ch_mon)/24; | |
288 | ch_mon_clk_reg=1; | |
289 | forever begin #(ch_mon_clk_period/2) ch_mon_clk_reg = ~ch_mon_clk_reg; end | |
290 | ||
291 | end | |
292 | ||
293 | ||
294 | initial begin | |
295 | ||
296 | ref_2x_clk_reg=0; | |
297 | ||
298 | #10; | |
299 | @(posedge sclk); | |
300 | time1_r=$realtime; | |
301 | @(posedge sclk); | |
302 | time2_r=$realtime; | |
303 | ||
304 | ref_2x_clk_period=(time2_r-time1_r)/2; | |
305 | // Generate 2x dram clock | |
306 | ref_2x_clk_reg=1; | |
307 | forever begin #(ref_2x_clk_period/2) ref_2x_clk_reg = ~ref_2x_clk_reg; end | |
308 | ||
309 | end | |
310 | ||
311 | reg [3:0] clk_cnt; | |
312 | reg [3:0] clk_cnt2; | |
313 | reg clock_en; | |
314 | initial begin | |
315 | clk_cnt=4'h0; | |
316 | clk_cnt2=4'h0; | |
317 | end | |
318 | initial clock_en=1'b0; | |
319 | ||
320 | always @(negedge link_clk) begin | |
321 | if ( frm_boundary_sb ) | |
322 | clk_cnt=4'b0; | |
323 | else | |
324 | clk_cnt=clk_cnt+4'b1; | |
325 | end | |
326 | wire dtm_dram_clk,dtm_dram_2x_clk; | |
327 | ||
328 | assign dtm_dram_clk = (clk_cnt > 4'd1) & (clk_cnt < 4'd8) ? 1 : 0; | |
329 | assign dtm_dram_2x_clk = ((clk_cnt > 4'd1) & (clk_cnt < 4'd5)) || ((clk_cnt > 4'd7) & (clk_cnt < 4'd11)) ? 1: 0; | |
330 | ||
331 | ||
332 | // Initialization | |
333 | initial begin | |
334 | ||
335 | dram_clk_reg=0; | |
336 | dtm_dram_clk_reg=1; | |
337 | ||
338 | #10; | |
339 | @(posedge sclk); | |
340 | time1=$realtime; | |
341 | @(posedge sclk); | |
342 | time2=$realtime; | |
343 | if ( ($test$plusargs("DTM_ENABLED")) || ($test$plusargs("VF_DTM_ENABLED")) ) | |
344 | dram_clk_period=(time2-time1)/1; | |
345 | else | |
346 | dram_clk_period=(time2-time1)/2; | |
347 | ||
348 | ||
349 | // `ifdef DTM_ENABLED | |
350 | // dram_clk_period=(time2-time1)/1; | |
351 | // `else | |
352 | // dram_clk_period=(time2-time1)/2; | |
353 | // `endif | |
354 | ||
355 | // Generate 1:2 dram clk | |
356 | @(negedge frm_start); | |
357 | dram_clk_reg=1; | |
358 | forever begin #(dram_clk_period/2) dram_clk_reg = ~dram_clk_reg; end | |
359 | ||
360 | end | |
361 | ||
362 | initial begin | |
363 | ||
364 | dram_2x_clk_reg=0; | |
365 | dtm_dram_2x_clk_reg=1; | |
366 | #10; | |
367 | @(posedge sclk); | |
368 | time1_2x=$realtime; | |
369 | @(posedge sclk); | |
370 | time2_2x=$realtime; | |
371 | if ( ($test$plusargs("DTM_ENABLED")) || ($test$plusargs("VF_DTM_ENABLED")) ) | |
372 | dram_2x_clk_period=(time2_2x-time1_2x)/2; | |
373 | else | |
374 | dram_2x_clk_period=(time2_2x-time1_2x)/4; | |
375 | ||
376 | // `ifdef DTM_ENABLED | |
377 | // dram_2x_clk_period=(time2_2x-time1_2x)/2; | |
378 | // `else | |
379 | // dram_2x_clk_period=(time2_2x-time1_2x)/4; | |
380 | // `endif | |
381 | ||
382 | // Generate 2x dram clock | |
383 | @(negedge frm_start); | |
384 | dram_2x_clk_reg=1; | |
385 | forever begin #(dram_2x_clk_period/2) dram_2x_clk_reg = ~dram_2x_clk_reg; end | |
386 | ||
387 | ||
388 | end | |
389 | ||
390 | reg [3:0] clock_counter; | |
391 | ||
392 | always@(negedge link_clk) | |
393 | begin | |
394 | if ( frm_start ) | |
395 | clock_counter=0; | |
396 | else | |
397 | clock_counter=clock_counter+1; | |
398 | end | |
399 | ||
400 | wire dtm_DRAM_CLK = (( clock_counter == 1 ) | ( clock_counter == 2 ) | ( clock_counter == 3 ) | ( clock_counter == 4 ) | ( clock_counter == 5 ) | ( clock_counter == 6 )) ? 1'b1: 1'b0; | |
401 | wire dtm_DRAM_2X_CLK = (( clock_counter == 1 ) | ( clock_counter == 2 ) | ( clock_counter == 3 ) | ( clock_counter == 7 ) | ( clock_counter == 8 ) | ( clock_counter == 9 )) ? 1'b1: 1'b0; | |
402 | ||
403 | initial begin | |
404 | ||
405 | link_clk_reg=0; | |
406 | ||
407 | #10; | |
408 | @(posedge sclk); | |
409 | time1_l=$realtime; | |
410 | @(posedge sclk); | |
411 | time2_l=$realtime; | |
412 | ||
413 | if ( ($test$plusargs("DTM_ENABLED")) || ($test$plusargs("VF_DTM_ENABLED")) ) | |
414 | link_clk_period=(time2_l-time1_l)/12; | |
415 | else | |
416 | link_clk_period=(time2_l-time1_l)/24; | |
417 | ||
418 | // `ifdef DTM_ENABLED | |
419 | // link_clk_period=(time2_l-time1_l)/12; | |
420 | // `else | |
421 | // link_clk_period=(time2_l-time1_l)/24; | |
422 | // `endif | |
423 | ||
424 | // Generate 2x dram clock | |
425 | //@(posedge frm_start); | |
426 | link_clk_reg=1; | |
427 | forever begin #(link_clk_period/2) link_clk_reg = ~link_clk_reg; end | |
428 | ||
429 | end | |
430 | ||
431 | `ifdef DTM_ENABLED | |
432 | assign dram_clk = dtm_dram_clk; //dram_clk_reg; | |
433 | assign dram_2x_clk = dtm_dram_2x_clk; //dram_2x_clk_reg; | |
434 | `else | |
435 | `ifdef STINGRAY_RESTART_CLK | |
436 | assign dram_clk = st_dram_clk_reg; | |
437 | assign dram_2x_clk = st_dram_2x_clk_reg; | |
438 | `else | |
439 | assign dram_clk = vf_dtm_enabled_reg ? dtm_dram_clk : dtm_DRAM_CLK; //dram_clk_reg; | |
440 | assign dram_2x_clk = vf_dtm_enabled_reg ? dtm_dram_2x_clk : dtm_DRAM_2X_CLK; //dram_2x_clk_reg; | |
441 | `endif | |
442 | ||
443 | `endif | |
444 | ||
445 | ||
446 | `ifdef STINGRAY_RESTART_CLK | |
447 | assign clk_int = st_clk_int_reg; | |
448 | assign link_clk = st_link_clk_reg; | |
449 | `else | |
450 | assign clk_int = clk_int_reg; | |
451 | assign link_clk = link_clk_reg; | |
452 | `endif | |
453 | ||
454 | ||
455 | ||
456 | `endif // AXIS_FBDIMM_HW | |
457 | ||
458 | ||
459 | ||
460 | ||
461 | ||
462 | endmodule |