[OpenSPARC-T2-DV] / verif / model / verilog / mem / fbdimm / design / sb_crc_error_injector.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: sb_crc_error_injector.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
module sb_crc_error_injector( ps_in, ps_out, init, is_bar, link_clk);
   parameter	     SB_LINK=10;
   parameter	     DS=0;

   input [SB_LINK-1:0]  ps_in;
   output [SB_LINK-1:0] ps_out;
   input		     init;
   input		     link_clk;
   input 	             is_bar;

   reg [9:0]	     ps0_crc_mask;
   reg [9:0]	     ps1_crc_mask;
   reg [9:0]	     ps2_crc_mask;
   reg [9:0]	     ps3_crc_mask;
   reg [9:0]	     ps4_crc_mask;
   reg [9:0]	     ps5_crc_mask;
   reg [9:0]	     ps6_crc_mask;
   reg [9:0]	     ps7_crc_mask;
   reg [9:0]	     ps8_crc_mask;
   reg [9:0]	     ps9_crc_mask;
   reg [9:0]	     ps10_crc_mask;
   reg [9:0]	     ps11_crc_mask;
   reg [11:0]	     ps_frame_num;
   reg [3:0]	     tr_counter;
   reg [11:0]	     ps_crc_freq;
   reg [11:0]	     ps_crc_period;
   reg		     crc_en;
   reg [15:0]	     frame_counter;
   wire [15:0]	     crc_clock_period = (ps_crc_freq+ps_crc_period)*6;
   reg		     header_detected,enable_fsm;
   reg [3:0]	     fsr_counter,lock_counter,prev_counter;
   reg [3:0]	     fsr_counter2,lock_counter2;
   
reg [6:0] nop_cnt;
reg dummy;
wire frm_begin,frm_boundary;
wire tr_complete;
reg bypass_init;

reg [3:0] UI_counter;
reg start_UI_counter;

assign ps_out =  ( UI_counter  == 4'h1 ) & crc_en ? ( ps_in ^ ps0_crc_mask ) :
                 ( UI_counter  == 4'h2 ) & crc_en ? ( ps_in ^ ps1_crc_mask ) :
                 ( UI_counter  == 4'h3 ) & crc_en ? ( ps_in ^ ps2_crc_mask ) :
                 ( UI_counter  == 4'h4 ) & crc_en ? ( ps_in ^ ps3_crc_mask ) :
                 ( UI_counter  == 4'h5 ) & crc_en ? ( ps_in ^ ps4_crc_mask ) :
                 ( UI_counter  == 4'h6 ) & crc_en ? ( ps_in ^ ps5_crc_mask ) :
                 ( UI_counter  == 4'h7 ) & crc_en ? ( ps_in ^ ps6_crc_mask ) :
                 ( UI_counter  == 4'h8 ) & crc_en ? ( ps_in ^ ps7_crc_mask ) :
                 ( UI_counter  == 4'h9 ) & crc_en ? ( ps_in ^ ps8_crc_mask ) :
                 ( UI_counter  == 4'ha ) & crc_en ? ( ps_in ^ ps9_crc_mask ) :
                 ( UI_counter  == 4'hb ) & crc_en ? ( ps_in ^ ps10_crc_mask ) :
                 ( UI_counter  == 4'hc ) & crc_en ? ( ps_in ^ ps11_crc_mask ) : ps_in;


always@(negedge link_clk)
 if ( header_detected )
   start_UI_counter <= 1;

always@(posedge link_clk) if ( start_UI_counter )
begin
  if ( UI_counter == 4'hc )
    UI_counter <= 4'h1;
  else
   UI_counter <= UI_counter + 4'h1;

end

initial begin
tr_counter = 1;
start_UI_counter=0;
UI_counter=4'h1;
ps0_crc_mask=0;
ps1_crc_mask=0;
ps2_crc_mask=0;
ps3_crc_mask=0;
ps4_crc_mask=0;
ps5_crc_mask=0;
ps6_crc_mask=0;
ps7_crc_mask=0;
ps8_crc_mask=0;
ps9_crc_mask=0;
ps10_crc_mask=0;
ps11_crc_mask=0;
crc_en= 0;
ps_crc_freq=0;
ps_frame_num=0;
ps_crc_period=0;
frame_counter=0;
 if ( $test$plusargs("bypass_init") ) begin
  lock_counter = 4'hc;
  bypass_init = 1;
 end
 else 
  bypass_init = 0;

lock_counter2=4'h1;

`ifdef AXIS_FBDIMM_HW
`else
dummy=$value$plusargs("ps0_crc_mask=%h",ps0_crc_mask);
dummy=$value$plusargs("ps1_crc_mask=%h",ps1_crc_mask);
dummy=$value$plusargs("ps2_crc_mask=%h",ps2_crc_mask);
dummy=$value$plusargs("ps3_crc_mask=%h",ps3_crc_mask);
dummy=$value$plusargs("ps4_crc_mask=%h",ps4_crc_mask);
dummy=$value$plusargs("ps5_crc_mask=%h",ps5_crc_mask);
dummy=$value$plusargs("ps6_crc_mask=%h",ps6_crc_mask);
dummy=$value$plusargs("ps7_crc_mask=%h",ps7_crc_mask);
dummy=$value$plusargs("ps8_crc_mask=%h",ps8_crc_mask);
dummy=$value$plusargs("ps9_crc_mask=%h",ps9_crc_mask);
dummy=$value$plusargs("ps10_crc_mask=%h",ps10_crc_mask);
dummy=$value$plusargs("ps11_crc_mask=%h",ps11_crc_mask);
dummy=$value$plusargs("ps_frame_num=%h",ps_frame_num);
dummy=$value$plusargs("ps_crc_freq=%h",ps_crc_freq);
dummy=$value$plusargs("ps_crc_period=%h",ps_crc_period);
`endif

end

reg [47:0] initialization_register_link0;

initial fsr_counter=4'h7;
initial fsr_counter2=4'hd;

always@(posedge link_clk)
begin
  if ( fsr_counter == 4'h1 )
   fsr_counter = 4'h6;
  else
   fsr_counter = fsr_counter - 1;

  if ( fsr_counter2 == 4'h1 )
   fsr_counter2 = 4'hc;
  else
   fsr_counter2 = fsr_counter2 - 1;

end

assign frm_begin = ( fsr_counter2 == lock_counter2 );
assign frm_boundary = (fsr_counter2 == lock_counter);
   
always@(negedge link_clk) if ( ~bypass_init )
begin

  if (header_detected )
     lock_counter <= prev_counter;
  else
   prev_counter <= fsr_counter2;

end  


reg [9:0] ps0_reg,ps1_reg,ps2_reg,ps3_reg,ps4_reg,ps5_reg,ps6_reg,ps7_reg,ps8_reg,ps9_reg,ps10_reg,ps11_reg;

always@(negedge link_clk)
begin
 ps0_reg <= ps1_reg;
 ps1_reg <= ps2_reg;
 ps2_reg <= ps3_reg;
 ps3_reg <= ps4_reg;
 ps4_reg <= ps5_reg;
 ps5_reg <= ps6_reg;
 ps6_reg <= ps7_reg;
 ps7_reg <= ps8_reg;
 ps8_reg <= ps9_reg;
 ps9_reg <= ps10_reg;
 ps10_reg <= ps11_reg;
 ps11_reg <= ps_in  ;

end


always@(posedge link_clk) if ( ~bypass_init )
begin
  if( is_bar == 1'b0)
  begin
  if ( (ps0_reg == 10'h3ff ) &&
       (ps1_reg == 10'h0 ) &&
       (ps2_reg == 10'h3ff ) &&
       (ps3_reg == 10'h3ff ) &&
       (ps4_reg == 10'h3ff ) &&
       (ps5_reg == 10'h3ff ) &&
       (ps6_reg == 10'h3ff ) &&
       (ps7_reg == 10'h3ff ) &&
       (ps8_reg == 10'h3ff ) &&
       (ps9_reg == 10'h3ff ) &&
       (ps10_reg == 10'h3ff ) &&
       (ps11_reg == 10'h0 ) )
   begin
     lock_counter2 <= fsr_counter2;
   end
   end
   else if(is_bar == 1'b1)
   begin
   if( (ps0_reg == 10'h0 ) &&
	(ps1_reg == 10'h3ff) &&
       ( ps2_reg == 10'h0) &&
       ( ps3_reg == 10'h0) &&
       ( ps4_reg == 10'h0) &&
       ( ps5_reg == 10'h0) &&
       ( ps6_reg == 10'h0) &&
       ( ps7_reg == 10'h0) &&
       ( ps8_reg == 10'h0) &&
       ( ps9_reg == 10'h0) &&
       ( ps10_reg == 10'h0) &&
       ( ps11_reg == 10'h3ff) )
    begin
      lock_counter2 <= fsr_counter2;
    end
    end

end  
   
always@(posedge link_clk) if ( ~bypass_init )
begin
 if(is_bar == 1'b0) // Not the sb_bar_crc_error_injector
  begin
   if ( initialization_register_link0[47:36] == 12'hbfe )
     header_detected<=1;
   else
     header_detected<=0;
  end
 else if(is_bar == 1'b1)
  begin
   if( initialization_register_link0[47:36] == 12'h401 )
     header_detected <= 1;
   else
     header_detected <= 0;
  end
end

always@(negedge link_clk)
begin
   initialization_register_link0[47:0] <= { ps_in[0],  initialization_register_link0[47:1]};  
end


always@(posedge link_clk) if ( ~init && (( ps_frame_num !== 0 ) && (crc_clock_period !== 0 )) )
begin


 if ( frame_counter !== crc_clock_period )
 begin

  if ( frame_counter < (ps_crc_freq*12) )
    crc_en <= 1;
  else
    crc_en <= 0;     

  frame_counter=frame_counter+1;

 end if ( frame_counter == crc_clock_period )
   frame_counter = 0;

 
  if ( tr_counter == 4'hc ) begin
    tr_counter=1;

    // If ps_frame_num is FFF, then all frames will have the same crc
    if ( ps_frame_num == 12'hfff ) begin
      crc_en <= 1;
    end
    // If ps_frame_num is non-zero, N number of frames will have crc errors
    // then crc will be turned off
    else if ( ps_frame_num !== 0 ) begin
     crc_en <= 1;
     ps_frame_num = ps_frame_num - 1;
    end
    else
      crc_en <= 0;

  end
   else
    tr_counter=tr_counter+1;

end
else
    crc_en <= 0;

endmodule
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: sb_crc_error_injector.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module sb_crc_error_injector( ps_in, ps_out, init, is_bar, link_clk);
	36	parameter SB_LINK=10;
	37	parameter DS=0;
	38
	39	input [SB_LINK-1:0] ps_in;
	40	output [SB_LINK-1:0] ps_out;
	41	input init;
	42	input link_clk;
	43	input is_bar;
	44
	45	reg [9:0] ps0_crc_mask;
	46	reg [9:0] ps1_crc_mask;
	47	reg [9:0] ps2_crc_mask;
	48	reg [9:0] ps3_crc_mask;
	49	reg [9:0] ps4_crc_mask;
	50	reg [9:0] ps5_crc_mask;
	51	reg [9:0] ps6_crc_mask;
	52	reg [9:0] ps7_crc_mask;
	53	reg [9:0] ps8_crc_mask;
	54	reg [9:0] ps9_crc_mask;
	55	reg [9:0] ps10_crc_mask;
	56	reg [9:0] ps11_crc_mask;
	57	reg [11:0] ps_frame_num;
	58	reg [3:0] tr_counter;
	59	reg [11:0] ps_crc_freq;
	60	reg [11:0] ps_crc_period;
	61	reg crc_en;
	62	reg [15:0] frame_counter;
	63	wire [15:0] crc_clock_period = (ps_crc_freq+ps_crc_period)*6;
	64	reg header_detected,enable_fsm;
65	reg [3:0] fsr_counter,lock_counter,prev_counter;
66	reg [3:0] fsr_counter2,lock_counter2;
67
68	reg [6:0] nop_cnt;
69	reg dummy;
70	wire frm_begin,frm_boundary;
71	wire tr_complete;
72	reg bypass_init;
73
74	reg [3:0] UI_counter;
75	reg start_UI_counter;
76
77	assign ps_out = ( UI_counter == 4'h1 ) & crc_en ? ( ps_in ^ ps0_crc_mask ) :
78	( UI_counter == 4'h2 ) & crc_en ? ( ps_in ^ ps1_crc_mask ) :
79	( UI_counter == 4'h3 ) & crc_en ? ( ps_in ^ ps2_crc_mask ) :
80	( UI_counter == 4'h4 ) & crc_en ? ( ps_in ^ ps3_crc_mask ) :
81	( UI_counter == 4'h5 ) & crc_en ? ( ps_in ^ ps4_crc_mask ) :
82	( UI_counter == 4'h6 ) & crc_en ? ( ps_in ^ ps5_crc_mask ) :
83	( UI_counter == 4'h7 ) & crc_en ? ( ps_in ^ ps6_crc_mask ) :
84	( UI_counter == 4'h8 ) & crc_en ? ( ps_in ^ ps7_crc_mask ) :
85	( UI_counter == 4'h9 ) & crc_en ? ( ps_in ^ ps8_crc_mask ) :
86	( UI_counter == 4'ha ) & crc_en ? ( ps_in ^ ps9_crc_mask ) :
87	( UI_counter == 4'hb ) & crc_en ? ( ps_in ^ ps10_crc_mask ) :
88	( UI_counter == 4'hc ) & crc_en ? ( ps_in ^ ps11_crc_mask ) : ps_in;
89
90
91	always@(negedge link_clk)
92	if ( header_detected )
93	start_UI_counter <= 1;
94
95	always@(posedge link_clk) if ( start_UI_counter )
96	begin
97	if ( UI_counter == 4'hc )
98	UI_counter <= 4'h1;
99	else
100	UI_counter <= UI_counter + 4'h1;
101
102	end
103
104	initial begin
105	tr_counter = 1;
106	start_UI_counter=0;
107	UI_counter=4'h1;
108	ps0_crc_mask=0;
109	ps1_crc_mask=0;
110	ps2_crc_mask=0;
111	ps3_crc_mask=0;
112	ps4_crc_mask=0;
113	ps5_crc_mask=0;
114	ps6_crc_mask=0;
115	ps7_crc_mask=0;
116	ps8_crc_mask=0;
117	ps9_crc_mask=0;
118	ps10_crc_mask=0;
119	ps11_crc_mask=0;
120	crc_en= 0;
121	ps_crc_freq=0;
122	ps_frame_num=0;
123	ps_crc_period=0;
124	frame_counter=0;
125	if ( $test$plusargs("bypass_init") ) begin
126	lock_counter = 4'hc;
127	bypass_init = 1;
128	end
129	else
130	bypass_init = 0;
131
132	lock_counter2=4'h1;
133
134	`ifdef AXIS_FBDIMM_HW
135	`else
136	dummy=$value$plusargs("ps0_crc_mask=%h",ps0_crc_mask);
137	dummy=$value$plusargs("ps1_crc_mask=%h",ps1_crc_mask);
138	dummy=$value$plusargs("ps2_crc_mask=%h",ps2_crc_mask);
139	dummy=$value$plusargs("ps3_crc_mask=%h",ps3_crc_mask);
140	dummy=$value$plusargs("ps4_crc_mask=%h",ps4_crc_mask);
141	dummy=$value$plusargs("ps5_crc_mask=%h",ps5_crc_mask);
142	dummy=$value$plusargs("ps6_crc_mask=%h",ps6_crc_mask);
143	dummy=$value$plusargs("ps7_crc_mask=%h",ps7_crc_mask);
144	dummy=$value$plusargs("ps8_crc_mask=%h",ps8_crc_mask);
145	dummy=$value$plusargs("ps9_crc_mask=%h",ps9_crc_mask);
146	dummy=$value$plusargs("ps10_crc_mask=%h",ps10_crc_mask);
147	dummy=$value$plusargs("ps11_crc_mask=%h",ps11_crc_mask);
148	dummy=$value$plusargs("ps_frame_num=%h",ps_frame_num);
149	dummy=$value$plusargs("ps_crc_freq=%h",ps_crc_freq);
150	dummy=$value$plusargs("ps_crc_period=%h",ps_crc_period);
151	`endif
152
153	end
154
155	reg [47:0] initialization_register_link0;
156
157	initial fsr_counter=4'h7;
158	initial fsr_counter2=4'hd;
159
160	always@(posedge link_clk)
161	begin
162	if ( fsr_counter == 4'h1 )
163	fsr_counter = 4'h6;
164	else
165	fsr_counter = fsr_counter - 1;
166
167	if ( fsr_counter2 == 4'h1 )
168	fsr_counter2 = 4'hc;
169	else
170	fsr_counter2 = fsr_counter2 - 1;
171
172	end
173
174	assign frm_begin = ( fsr_counter2 == lock_counter2 );
175	assign frm_boundary = (fsr_counter2 == lock_counter);
176
177	always@(negedge link_clk) if ( ~bypass_init )
178	begin
179
180	if (header_detected )
181	lock_counter <= prev_counter;
182	else
183	prev_counter <= fsr_counter2;
184
185	end
186
187
188
189	reg [9:0] ps0_reg,ps1_reg,ps2_reg,ps3_reg,ps4_reg,ps5_reg,ps6_reg,ps7_reg,ps8_reg,ps9_reg,ps10_reg,ps11_reg;
190
191	always@(negedge link_clk)
192	begin
193	ps0_reg <= ps1_reg;
194	ps1_reg <= ps2_reg;
195	ps2_reg <= ps3_reg;
196	ps3_reg <= ps4_reg;
197	ps4_reg <= ps5_reg;
198	ps5_reg <= ps6_reg;
199	ps6_reg <= ps7_reg;
200	ps7_reg <= ps8_reg;
201	ps8_reg <= ps9_reg;
202	ps9_reg <= ps10_reg;
203	ps10_reg <= ps11_reg;
204	ps11_reg <= ps_in ;
205
206	end
207
208
209	always@(posedge link_clk) if ( ~bypass_init )
210	begin
211	if( is_bar == 1'b0)
212	begin
213	if ( (ps0_reg == 10'h3ff ) &&
214	(ps1_reg == 10'h0 ) &&
215	(ps2_reg == 10'h3ff ) &&
216	(ps3_reg == 10'h3ff ) &&
217	(ps4_reg == 10'h3ff ) &&
218	(ps5_reg == 10'h3ff ) &&
219	(ps6_reg == 10'h3ff ) &&
220	(ps7_reg == 10'h3ff ) &&
221	(ps8_reg == 10'h3ff ) &&
222	(ps9_reg == 10'h3ff ) &&
223	(ps10_reg == 10'h3ff ) &&
224	(ps11_reg == 10'h0 ) )
225	begin
226	lock_counter2 <= fsr_counter2;
227	end
228	end
229	else if(is_bar == 1'b1)
230	begin
231	if( (ps0_reg == 10'h0 ) &&
232	(ps1_reg == 10'h3ff) &&
233	( ps2_reg == 10'h0) &&
234	( ps3_reg == 10'h0) &&
235	( ps4_reg == 10'h0) &&
236	( ps5_reg == 10'h0) &&
237	( ps6_reg == 10'h0) &&
238	( ps7_reg == 10'h0) &&
239	( ps8_reg == 10'h0) &&
240	( ps9_reg == 10'h0) &&
241	( ps10_reg == 10'h0) &&
242	( ps11_reg == 10'h3ff) )
243	begin
244	lock_counter2 <= fsr_counter2;
245	end
246	end
247
248	end
249
250	always@(posedge link_clk) if ( ~bypass_init )
251	begin
252	if(is_bar == 1'b0) // Not the sb_bar_crc_error_injector
253	begin
254	if ( initialization_register_link0[47:36] == 12'hbfe )
255	header_detected<=1;
256	else
257	header_detected<=0;
258	end
259	else if(is_bar == 1'b1)
260	begin
261	if( initialization_register_link0[47:36] == 12'h401 )
262	header_detected <= 1;
263	else
264	header_detected <= 0;
265	end
266	end
267
268	always@(negedge link_clk)
269	begin
270	initialization_register_link0[47:0] <= { ps_in[0], initialization_register_link0[47:1]};
271	end
272
273
274	always@(posedge link_clk) if ( ~init && (( ps_frame_num !== 0 ) && (crc_clock_period !== 0 )) )
275	begin
276
277
278	if ( frame_counter !== crc_clock_period )
279	begin
280
281	if ( frame_counter < (ps_crc_freq*12) )
282	crc_en <= 1;
283	else
284	crc_en <= 0;
285
286	frame_counter=frame_counter+1;
287
288	end if ( frame_counter == crc_clock_period )
289	frame_counter = 0;
290
291
292
293	if ( tr_counter == 4'hc ) begin
294	tr_counter=1;
295
296	// If ps_frame_num is FFF, then all frames will have the same crc
297	if ( ps_frame_num == 12'hfff ) begin
298	crc_en <= 1;
299	end
300	// If ps_frame_num is non-zero, N number of frames will have crc errors
301	// then crc will be turned off
302	else if ( ps_frame_num !== 0 ) begin
303	crc_en <= 1;
304	ps_frame_num = ps_frame_num - 1;
305	end
306	else
307	crc_en <= 0;
308
309	end
310	else
311	tr_counter=tr_counter+1;
312
313	end
314	else
315	crc_en <= 0;
316
317	endmodule