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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: testing_state_fsm.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifdef AXIS_FBDIMM_NO_FSR | |
36 | `else | |
37 | ||
38 | module testing_state_fsm(ps_bit,link_clk,amb_id,testing_state_start,testing_state_end,amb_id_ok,sb2nbmap); | |
39 | ||
40 | parameter DS=0; | |
41 | ||
42 | input ps_bit; | |
43 | input link_clk; | |
44 | output [3:0] amb_id; | |
45 | input testing_state_start; | |
46 | output testing_state_end; | |
47 | output amb_id_ok; | |
48 | output [2:0] sb2nbmap; | |
49 | ||
50 | reg [2:0] SB2NB_Map,SB2NB_Map_tmp; | |
51 | reg first_frame_enddelimeter_ok; | |
52 | reg [11:0] tr_reg; | |
53 | reg [4:0] tr_state; | |
54 | reg [4:0] tr_count; | |
55 | reg [11:0] clk_trn_ptrn; | |
56 | reg [3:0] clk_grp; | |
57 | reg ts1_ready_reg; | |
58 | reg [3:0] amb_id_reg; | |
59 | reg [23:0] test_param_reg; | |
60 | reg [7:8] test_param_count; | |
61 | reg [47:0] end_del_reg; | |
62 | reg [2:0] sb2nbmap_reg; | |
63 | reg testing_state_start_reg,testing_state_end_reg; | |
64 | assign amb_id=amb_id_reg; | |
65 | assign amb_id_ok = ( amb_id_reg == DS) ? 1'b1: 1'b0; | |
66 | assign sb2nbmap = SB2NB_Map ; | |
67 | ||
68 | `define BEFORE_IDLE 9 | |
69 | ||
70 | initial begin | |
71 | tr_state=`BEFORE_IDLE; | |
72 | tr_count=5'h0; | |
73 | test_param_count=0; | |
74 | amb_id_reg=0; | |
75 | SB2NB_Map=0; | |
76 | SB2NB_Map_tmp=0; | |
77 | end | |
78 | ||
79 | //assign testing_state_start=testing_state_start_reg; | |
80 | assign testing_state_end=testing_state_end_reg; | |
81 | ||
82 | ||
83 | always@(negedge link_clk) if ( testing_state_start ) | |
84 | begin | |
85 | case(tr_state) | |
86 | `BEFORE_IDLE: begin | |
87 | SB2NB_Map <= 0; | |
88 | tr_state<=`IDLE; | |
89 | first_frame_enddelimeter_ok <= 1'b0; | |
90 | end | |
91 | `IDLE: begin | |
92 | tr_reg[11:0] <= {ps_bit, tr_reg[11:1] }; | |
93 | ||
94 | // polling state detected | |
95 | if ( ({ps_bit, tr_reg[11:1] } == 12'b011111111110 ) & | |
96 | first_frame_enddelimeter_ok ) | |
97 | testing_state_end_reg <=1; | |
98 | else | |
99 | testing_state_end_reg <=0; | |
100 | ||
101 | if ( {ps_bit, tr_reg[11:1] } == 12'b111111111110 ) begin | |
102 | tr_state<=`TS_TEST_1; | |
103 | `ifdef FBD_DBG | |
104 | `PR_ALWAYS ("amb_init",`DBG_0,"AMB Detected TESTING"); | |
105 | `endif | |
106 | end | |
107 | ||
108 | end | |
109 | `TS_TEST_1: begin | |
110 | case(tr_count) | |
111 | 4'b0000: begin tr_reg[0] <= ps_bit; tr_count<=tr_count+5'h1; end | |
112 | 4'b0001: begin tr_reg[1] <= ps_bit; tr_count<=tr_count+5'h1; end | |
113 | 4'b0010: begin tr_reg[2] <= ps_bit; tr_count<=tr_count+5'h1;end | |
114 | 4'b0011: begin tr_reg[3] <= ps_bit; tr_count<=tr_count+5'h1; end | |
115 | 4'b0100: begin tr_reg[4] <= ps_bit; tr_count<=tr_count+5'h1; end | |
116 | 4'b0101: begin tr_reg[5] <= ps_bit; tr_count<=tr_count+5'h1; end | |
117 | 4'b0110: begin tr_reg[6] <= ps_bit; tr_count<=tr_count+5'h1; end | |
118 | 4'b0111: begin tr_reg[7] <= ps_bit; tr_count<=tr_count+5'h1; end | |
119 | 4'b1000: begin tr_reg[8] <= ps_bit; tr_count<=tr_count+5'h1; end | |
120 | 4'b1001: begin tr_reg[9] <= ps_bit; tr_count<=tr_count+5'h1; end | |
121 | 4'b1010: begin tr_reg[10] <= ps_bit; tr_count<=tr_count+5'h1; end | |
122 | 4'b1011: begin tr_reg[11] <= ps_bit; tr_state<=`TS_TEST_2; | |
123 | tr_count<=5'h1;clk_grp<=0; amb_id_reg[3:0]<=tr_reg[3:0];SB2NB_Map<=tr_reg[6:4]; | |
124 | ||
125 | `ifdef FBD_DBG | |
126 | `PR_ALWAYS ("amb_init",`DBG_0,"TS_TEST Control values: ambid=%h sb2nbmap %h",tr_reg[3:0],tr_reg[6:4]); | |
127 | `endif | |
128 | end | |
129 | endcase | |
130 | end | |
131 | ||
132 | `TS_TEST_2: begin | |
133 | end_del_reg[47:0] <= { ps_bit,end_del_reg[47:1]}; | |
134 | ||
135 | // if the last 4 groups have; | |
136 | // n-3 => first del, first grp | |
137 | // n-2 => first del, last grp | |
138 | // n-1 => last del, first grp | |
139 | // n => last del, last grp | |
140 | ||
141 | if ( { ps_bit,end_del_reg[47:1]} == {12'b001101000101,12'b011001111000,12'b001101000101,12'b011001111000} ) | |
142 | begin | |
143 | `ifdef FBD_DBG | |
144 | `PR_ALWAYS ("amb_init",`DBG_0,"AMB_INIT testing end sequence detected"); | |
145 | `endif | |
146 | first_frame_enddelimeter_ok <= 1'b1; | |
147 | tr_state<=`IDLE; | |
148 | end | |
149 | ||
150 | end | |
151 | ||
152 | endcase | |
153 | ||
154 | ||
155 | end | |
156 | else begin | |
157 | tr_state<=`BEFORE_IDLE; | |
158 | testing_state_end_reg <= 0; | |
159 | end | |
160 | ||
161 | endmodule | |
162 | ||
163 | ||
164 | ||
165 | module testing_state_fsm_chk(ps_bit,link_clk,testing_state_start); | |
166 | ||
167 | parameter DS=0; | |
168 | ||
169 | input ps_bit; | |
170 | input link_clk; | |
171 | input testing_state_start; | |
172 | ||
173 | reg [2:0] SB2NB_Map; | |
174 | reg [143:0] tr_reg; | |
175 | reg [4:0] tr_state; | |
176 | reg [9:0] tr_count; | |
177 | reg [11:0] clk_trn_ptrn; | |
178 | reg [3:0] clk_grp; | |
179 | reg ts1_ready_reg; | |
180 | reg [3:0] amb_id_reg; | |
181 | reg [23:0] test_param_reg; | |
182 | reg [7:8] test_param_count; | |
183 | reg [47:0] end_del_reg; | |
184 | reg testing_state_start_reg,testing_state_end_reg; | |
185 | ||
186 | initial begin | |
187 | tr_state=0; | |
188 | tr_count=10'h0; | |
189 | test_param_count=0; | |
190 | amb_id_reg=0; | |
191 | SB2NB_Map=0; | |
192 | end | |
193 | ||
194 | ||
195 | always@(posedge link_clk) if ( testing_state_start ) | |
196 | begin | |
197 | case(tr_state) | |
198 | `IDLE: begin | |
199 | // ts1_ready_reg=0; | |
200 | tr_reg[143:0] <= {ps_bit,tr_reg[143:1]}; | |
201 | ||
202 | if (tr_reg[143:132] == 12'b111111111110 ) begin | |
203 | tr_state<=`TS_TEST_1; | |
204 | end | |
205 | ||
206 | end | |
207 | `TS_TEST_1: begin | |
208 | tr_reg[143:0] = {ps_bit,tr_reg[143:1]}; | |
209 | tr_count<=tr_count+10'h1; | |
210 | if ( (tr_count == 10'h83) && (tr_reg[143:0] != 0 ) ) begin | |
211 | `ifdef AXIS_FBDIMM_HW | |
212 | `else | |
213 | `PR_ALWAYS ("ch_mon",`DBG_0,"ts_reg: %h ",tr_reg); | |
214 | ||
215 | /* This is already checked indirectly | |
216 | if ( tr_reg[11:0] != 12'hffe ) | |
217 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: ffe pattern not found for testing state "); | |
218 | ||
219 | */ | |
220 | if ( {tr_reg[23:19]} != {5'b00000} ) | |
221 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: grp1 pattern in testing is wrong! "); | |
222 | ||
223 | if ( (tr_reg[18:16] != 3'b000 ) && (tr_reg[18:16] != 3'b001)) | |
224 | `PR_ALWAYS ("ch_mon",`DBG_0,"ERROR: SBtoNB mapping value(%b) in testing is reserved! ",tr_reg[18:16]); | |
225 | `endif | |
226 | tr_count<=10'h0; | |
227 | tr_state<=`IDLE; | |
228 | end | |
229 | end | |
230 | ||
231 | endcase | |
232 | ||
233 | ||
234 | end | |
235 | ||
236 | ||
237 | endmodule | |
238 | ||
239 | `endif //AXIS_FBDIMM_HW |