Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / model / verilog / niu / niu_enet_models / rgmii_mux.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: rgmii_mux.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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module rgmii_mux(txclk, 
                tx_config, 
                txd0_d4, 
                txd1_d5, 
                txd2_d6, 
                txd3_d7, 
                txen_er,
		rxclk, 
                rx_config, 
                rxd0_d4, 
                rxd1_d5, 
                rxd2_d6, 
                rxd3_d7, 
                rxer_dv,
		txd, 
                txen, 
                txer, 
                rxd, 
                rxdv, 
                rxer);

input		txclk;
input [3:0]	tx_config;
input   	txd0_d4, txd1_d5, txd2_d6, txd3_d7;
input   	txen_er;
output	[7:0]	txd;
output		txen, txer;

input		rxclk;
input [3:0]	rx_config;
output          rxd0_d4, rxd1_d5, rxd2_d6,rxd3_d7;
output          rxer_dv;
input	[7:0]	rxd;
input		rxdv, rxer;


reg	[3:0]	txd_r;
reg	[3:0]	txd_f;
reg		txen_r;
reg		txen, txer;


reg  	        rxd0_d4, rxd1_d5, rxd2_d6,rxd3_d7;
reg    	        rxer_dv;

//wire		rxer_dv;


// ----- TX negedge register -----


   always @(negedge txclk)
     begin
      //if (tx_config[3:0] == 4'b0011) 
       // begin
	txd_f[3] <= #0.5 txd3_d7;
	txd_f[2] <= #0.5 txd2_d6;
	txd_f[1] <= #0.5 txd1_d5;
	txd_f[0] <= #0.5 txd0_d4;
	txen_r   <= #0.5 txen_er;
        //end
     end

always @(posedge txclk)
   begin
	txd_r[3:0]   <= #0.5 {txd3_d7, txd2_d6, txd1_d5,txd0_d4};
	txen  <= #0.5 txen_er;
	txer  <= #0.5 txen_r;
   end

  assign txd[7:0] = {txd_f[3:0],txd_r[3:0]};


always @(negedge rxclk)
//always @(posedge rxclk)
  begin
       rxd0_d4 <= #0.5 rxd[0];
       rxd1_d5 <= #0.5 rxd[1];
       rxd2_d6 <= #0.5 rxd[2];
       rxd3_d7 <= #0.5 rxd[3];
       rxer_dv <= #0.5 rxdv;

  end

//always @(negedge rxclk)
always @(posedge rxclk)
  begin
       rxd0_d4 <= #0.5 rxd[4];
       rxd1_d5 <= #0.5 rxd[5];
       rxd2_d6 <= #0.5 rxd[6];
       rxd3_d7 <= #0.5 rxd[7];
       rxer_dv <= #0.5 rxer;

  end

// ----- RX Mux ----- 
/**
assign #0.5 {rxd0_d4, rxd1_d5, rxd2_d6, rxd3_d7, rxer_dv} = (rxclk==1)		?
					{rxd[4],rxd[5], rxd[6],rxd[7], rxer}  :
					{rxd[0], rxd[1],rxd[2],rxd[3], rxdv};  	

assign #0.0 {rxd0_d4, rxd1_d5, rxd2_d6, rxd3_d7, rxer_dv} = (rxclk==1)		?
					{rxd[4],rxd[5], rxd[6],rxd[7], rxer}  :
					{rxd[0], rxd[1],rxd[2],rxd[3], rxdv};  	

***************************/
endmodule