// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: db0_red_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
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// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
wire [11:0] dmu_ncu_data_fnl;
wire ff_dmu_ncu_data_scanin;
wire ff_dmu_ncu_data_scanout;
wire [31:0] dmu_ncu_data_r;
wire ff_dmu_ncu_data_r0_scanin;
wire ff_dmu_ncu_data_r0_scanout;
wire ff_dmu_ncu_data_r1_scanin;
wire ff_dmu_ncu_data_r1_scanout;
wire ff_dmu_ncu_data_r2_scanin;
wire ff_dmu_ncu_data_r2_scanout;
wire ff_dmu_ncu_data_r3_scanin;
wire ff_dmu_ncu_data_r3_scanout;
wire ff_rep_bus_slice0_scanin;
wire ff_rep_bus_slice0_scanout;
wire ff_rep_bus_slice1_scanin;
wire ff_rep_bus_slice1_scanout;
wire ff_rep_bus_slice2_scanin;
wire ff_rep_bus_slice2_scanout;
wire ff_rep_bus_slice3_scanin;
wire ff_rep_bus_slice3_scanout;
wire ff_rep_bus_slice4_scanin;
wire ff_rep_bus_slice4_scanout;
wire ff_rep_bus_slice5_scanin;
wire ff_rep_bus_slice5_scanout;
wire ff_rep_bus_slice6_scanin;
wire ff_rep_bus_slice6_scanout;
wire ff_rep_bus_slice7_scanin;
wire ff_rep_bus_slice7_scanout;
wire ff_rep_bus_slice8_scanin;
wire ff_rep_bus_slice8_scanout;
wire ff_rep_bus_slice9_scanin;
wire ff_rep_bus_slice9_scanout;
input iol2clk; // Internal IO clock from CCU
output [331:0] red_rtc_rep_bus; // repeatability bus
input dmu_ncu_wrack_vld; //CSR Wr Ack from DMU to NCU
input [3:0] dmu_ncu_wrack_tag; //CSR Wr Tag [3:0] from DMU to NCU
input [31:0] dmu_ncu_data; //CSR read data from DMU to NCU
input dmu_ncu_vld; //CSR Data return valid from DMU to NCU
input dmu_ncu_stall; //Stall asserted by DMU to NCU
input dmu_sii_hdr_vld; //DMU requesting to send DMA/Pio Read return/Interrupt packet to SII
input dmu_sii_reqbypass; //DMU requesting to send packet to bypass queue of SII
input dmu_sii_datareq; //DMU requesting to send packet w/data to SII
input dmu_sii_datareq16; //DMU requesting to send packet w/16B only
input [127:0] dmu_sii_data; //Packet from DMU to SII
input [15:0] dmu_sii_be; //Packet byte enables from DMU to SII
input [7:0] dmu_dbg0_debug_bus_a; //Debug Bus A from DMU
input [7:0] dmu_dbg0_debug_bus_b; //Debug Bus B from DMU
input niu_ncu_vld; //CSR Data return/Interrupt valid from NIU to NCU
input [31:0] niu_ncu_data; //CSR data/ Interrupt packet from NIU to NCU
input niu_ncu_stall; //Stall asserted by NIU to NCU
input niu_sii_hdr_vld; //NIU requesting to send packet to SII
input niu_sii_reqbypass; //NIU requesting to send packet to bypass queue of SII
input niu_sii_datareq; //NIU requesting to send packet w/data to SII
input [127:0] niu_sii_data; //Packet from NIU to SII
input niu_sio_dq; //flow control or credit return signal from NIU to SIO
output [7:0] dbg0_mio_debug_bus_a; //Flopped version of Debug Bus A from DMU
output [7:0] dbg0_mio_debug_bus_b; //Flopped version of Debug Bus B from DMU
assign pce_ov = tcu_pce_ov;
assign stop = tcu_clk_stop;
wire [11:0] dmu_ncu_data_reg0,dmu_ncu_data_reg1,dmu_ncu_data_reg2,dmu_ncu_data_reg3;
wire [35:0] dmu_ncu_data_0,dmu_ncu_data_1,dmu_ncu_data_2,dmu_ncu_data_3;
wire [165:0] dmu_data, niu_data;
// flop dmu_ncu_data[31:0] and dmu_ncu_vld
assign niu_data = {niu_ncu_vld,niu_ncu_data[31:0],niu_ncu_stall,niu_sii_hdr_vld,
niu_sii_reqbypass,niu_sii_datareq,niu_sio_dq,niu_sii_data[127:0]};
assign dmu_data = {dmu_ncu_data_fnl[11:0],dmu_ncu_wrack_vld,dmu_ncu_wrack_tag[3:0],
dmu_ncu_stall,dmu_sii_hdr_vld,dmu_sii_reqbypass,dmu_sii_datareq,
dmu_sii_datareq16,dmu_sii_be[15:0],dmu_sii_data[127:0]
db0_red_dp_msff_macro__stack_34r__width_33 ff_dmu_ncu_data (
.scan_in(ff_dmu_ncu_data_scanin),
.scan_out(ff_dmu_ncu_data_scanout),
.din ({dmu_ncu_vld,dmu_ncu_data[31:0]}),
.dout ({dmu_ncu_vld_r,dmu_ncu_data_r[31:0]}),
// flop dmu_ncu_vld_r,dmu_ncu_data_r[31:0] into 4 separate flops
// based on write enables coming from dbg0_red_ctl.sv
// these are the 4 data beats from dmu to ncu for csr
db0_red_dp_msff_macro__stack_36r__width_36 ff_dmu_ncu_data_r0 (
.scan_in(ff_dmu_ncu_data_r0_scanin),
.scan_out(ff_dmu_ncu_data_r0_scanout),
.din ({dmu_ncu_vld_r,1'b0,dmu_ncu_data_r[31:22],
dmu_ncu_vld_r,dmu_ncu_data_r[21:11],
dmu_ncu_vld_r,dmu_ncu_data_r[10:0]}
.dout (dmu_ncu_data_0[35:0]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_dmu_ncu_data_r1 (
.scan_in(ff_dmu_ncu_data_r1_scanin),
.scan_out(ff_dmu_ncu_data_r1_scanout),
.din ({dmu_ncu_vld_r,1'b0,dmu_ncu_data_r[31:22],
dmu_ncu_vld_r,dmu_ncu_data_r[21:11],
dmu_ncu_vld_r,dmu_ncu_data_r[10:0]}
.dout (dmu_ncu_data_1[35:0]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_dmu_ncu_data_r2 (
.scan_in(ff_dmu_ncu_data_r2_scanin),
.scan_out(ff_dmu_ncu_data_r2_scanout),
.din ({dmu_ncu_vld_r,1'b0,dmu_ncu_data_r[31:22],
dmu_ncu_vld_r,dmu_ncu_data_r[21:11],
dmu_ncu_vld_r,dmu_ncu_data_r[10:0]}
.dout (dmu_ncu_data_2[35:0]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_dmu_ncu_data_r3 (
.scan_in(ff_dmu_ncu_data_r3_scanin),
.scan_out(ff_dmu_ncu_data_r3_scanout),
.din ({dmu_ncu_vld_r,1'b0,dmu_ncu_data_r[31:22],
dmu_ncu_vld_r,dmu_ncu_data_r[21:11],
dmu_ncu_vld_r,dmu_ncu_data_r[10:0]}
.dout (dmu_ncu_data_3[35:0]),
// Mux out the outputs of these 4 flop macros based on
// control signals from dbg0_red_ctl
db0_red_dp_mux_macro__mux_aonpe__ports_3__stack_12r__width_12 mux_1
.dout (dmu_ncu_data_reg0[11:0]),
.din0 (dmu_ncu_data_0[11:0]),
.din1 (dmu_ncu_data_0[23:12]),
.din2 (dmu_ncu_data_0[35:24]),
db0_red_dp_mux_macro__mux_aonpe__ports_3__stack_12r__width_12 mux_2
.dout (dmu_ncu_data_reg1[11:0]),
.din0 (dmu_ncu_data_1[11:0]),
.din1 (dmu_ncu_data_1[23:12]),
.din2 (dmu_ncu_data_1[35:24]),
db0_red_dp_mux_macro__mux_aonpe__ports_3__stack_12r__width_12 mux_3
.dout (dmu_ncu_data_reg2[11:0]),
.din0 (dmu_ncu_data_2[11:0]),
.din1 (dmu_ncu_data_2[23:12]),
.din2 (dmu_ncu_data_2[35:24]),
db0_red_dp_mux_macro__mux_aonpe__ports_3__stack_12r__width_12 mux_4
.dout (dmu_ncu_data_reg3[11:0]),
.din0 (dmu_ncu_data_3[11:0]),
.din1 (dmu_ncu_data_3[23:12]),
.din2 (dmu_ncu_data_3[35:24]),
db0_red_dp_mux_macro__mux_aonpe__ports_4__stack_12r__width_12 mux_5
.dout (dmu_ncu_data_fnl[11:0]),
.din0 (dmu_ncu_data_reg0[11:0]),
.din1 (dmu_ncu_data_reg1[11:0]),
.din2 (dmu_ncu_data_reg2[11:0]),
.din3 (dmu_ncu_data_reg3[11:0]),
// Output flops for rep_bus[331:0] , DMU data on 165:0,NIU on 331:166
db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice0 (
.scan_in(ff_rep_bus_slice0_scanin),
.scan_out(ff_rep_bus_slice0_scanout),
.dout (red_rtc_rep_bus[35:0]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice1 (
.scan_in(ff_rep_bus_slice1_scanin),
.scan_out(ff_rep_bus_slice1_scanout),
.dout (red_rtc_rep_bus[71:36]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice2 (
.scan_in(ff_rep_bus_slice2_scanin),
.scan_out(ff_rep_bus_slice2_scanout),
.dout (red_rtc_rep_bus[107:72]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice3 (
.scan_in(ff_rep_bus_slice3_scanin),
.scan_out(ff_rep_bus_slice3_scanout),
.dout (red_rtc_rep_bus[143:108]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice4 (
.scan_in(ff_rep_bus_slice4_scanin),
.scan_out(ff_rep_bus_slice4_scanout),
.din ({niu_data[13:0],dmu_data[165:144]}
.dout (red_rtc_rep_bus[179:144]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice5 (
.scan_in(ff_rep_bus_slice5_scanin),
.scan_out(ff_rep_bus_slice5_scanout),
.dout (red_rtc_rep_bus[215:180]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice6 (
.scan_in(ff_rep_bus_slice6_scanin),
.scan_out(ff_rep_bus_slice6_scanout),
.dout (red_rtc_rep_bus[251:216]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice7 (
.scan_in(ff_rep_bus_slice7_scanin),
.scan_out(ff_rep_bus_slice7_scanout),
.dout (red_rtc_rep_bus[287:252]),
db0_red_dp_msff_macro__stack_36r__width_36 ff_rep_bus_slice8 (
.scan_in(ff_rep_bus_slice8_scanin),
.scan_out(ff_rep_bus_slice8_scanout),
.dout (red_rtc_rep_bus[323:288]),
db0_red_dp_msff_macro__stack_24r__width_24 ff_rep_bus_slice9 (
.scan_in(ff_rep_bus_slice9_scanin),
.scan_out(ff_rep_bus_slice9_scanout),
.din ({dmu_dbg0_debug_bus_b[7:0],
dmu_dbg0_debug_bus_a[7:0],
.dout ({dbg0_mio_debug_bus_b[7:0],
dbg0_mio_debug_bus_a[7:0],
red_rtc_rep_bus[331:324]}),
assign ff_dmu_ncu_data_scanin = scan_in ;
assign ff_dmu_ncu_data_r0_scanin = ff_dmu_ncu_data_scanout ;
assign ff_dmu_ncu_data_r1_scanin = ff_dmu_ncu_data_r0_scanout;
assign ff_dmu_ncu_data_r2_scanin = ff_dmu_ncu_data_r1_scanout;
assign ff_dmu_ncu_data_r3_scanin = ff_dmu_ncu_data_r2_scanout;
assign ff_rep_bus_slice0_scanin = ff_dmu_ncu_data_r3_scanout;
assign ff_rep_bus_slice1_scanin = ff_rep_bus_slice0_scanout;
assign ff_rep_bus_slice2_scanin = ff_rep_bus_slice1_scanout;
assign ff_rep_bus_slice3_scanin = ff_rep_bus_slice2_scanout;
assign ff_rep_bus_slice4_scanin = ff_rep_bus_slice3_scanout;
assign ff_rep_bus_slice5_scanin = ff_rep_bus_slice4_scanout;
assign ff_rep_bus_slice6_scanin = ff_rep_bus_slice5_scanout;
assign ff_rep_bus_slice7_scanin = ff_rep_bus_slice6_scanout;
assign ff_rep_bus_slice8_scanin = ff_rep_bus_slice7_scanout;
assign ff_rep_bus_slice9_scanin = ff_rep_bus_slice8_scanout;
assign scan_out = ff_rep_bus_slice9_scanout;
// any PARAMS parms go into naming of macro
module db0_red_dp_msff_macro__stack_34r__width_33 (
.so({so[31:0],scan_out}),
// any PARAMS parms go into naming of macro
module db0_red_dp_msff_macro__stack_36r__width_36 (
.so({so[34:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module db0_red_dp_mux_macro__mux_aonpe__ports_3__stack_12r__width_12 (
cl_dp1_muxbuff3_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module db0_red_dp_mux_macro__mux_aonpe__ports_4__stack_12r__width_12 (
cl_dp1_muxbuff4_8x c0_0 (
// any PARAMS parms go into naming of macro
module db0_red_dp_msff_macro__stack_24r__width_24 (
.so({so[22:0],scan_out}),