// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_imu_dms.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
//############################################################################
//############################################################################
//------------------------------------------------------------------------
// Clock and Reset Signals
//------------------------------------------------------------------------
//------------------------------------------------------------------------
// Inputs from RDS Sub-block Signals
//------------------------------------------------------------------------
input [127:0] rds2dms_data;
input [3:0] rds2dms_d_ptr;
//------------------------------------------------------------------------
// Outputs to DIU Block Signals
//------------------------------------------------------------------------
output [`FIRE_DLC_IRD_ADDR_WDTH-1:0] im2di_addr;
output [`FIRE_DLC_IRD_DATA_WDTH-1:0] im2di_data;
output [`FIRE_DLC_IRD_DPAR_WDTH-1:0] im2di_dpar;
output [`FIRE_DLC_IRD_BMASK_WDTH-1:0] im2di_bmask;
//############################################################################
//############################################################################
//############################################################################
//############################################################################
//**************************************************
//**************************************************
wire [`FIRE_DLC_IRD_DPAR_WDTH-1:0] rds2dms_dpar_del;
//**************************************************
// Registers that Are Not Flops
//**************************************************
wire [`FIRE_DLC_IRD_BMASK_WDTH-1:0] im2di_bmask;
//**************************************************
// Registers that Are Flops
//**************************************************
reg rds2dms_data_sel_del;
reg [127:0] rds2dms_data_del;
reg [3:0] rds2dms_d_ptr_del;
reg [`FIRE_DLC_IRD_ADDR_WDTH-1:0] im2di_addr;
reg [`FIRE_DLC_IRD_DATA_WDTH-1:0] im2di_data;
reg [`FIRE_DLC_IRD_DPAR_WDTH-1:0] im2di_dpar;
//############################################################################
//############################################################################
//############################################################################
//############################################################################
//----------------------------------------------
// - Since the 16 bytes of data is always
// valid can just hard wire to 1
// - Also the 1 parity bit can also be
// hard wireed to 1 for odd parity
//----------------------------------------------
assign im2di_bmask = 16'hffff;
assign bmask_dpar = 1'b1;
//----------------------------------------------
// - calculate 1 bit of parity for every 32
// - Do this off of the delayed data
// - Assign output next value
//----------------------------------------------
assign quad_3_dpar = !(^rds2dms_data_del[127:96]);
assign quad_2_dpar = !(^rds2dms_data_del[95:64]);
assign quad_1_dpar = !(^rds2dms_data_del[63:32]);
assign quad_0_dpar = !(^rds2dms_data_del[31:0]);
assign rds2dms_dpar_del = {quad_3_dpar, quad_2_dpar, quad_1_dpar, quad_0_dpar, bmask_dpar};
//############################################################################
//############################################################################
//-----------------------------------------------------------------------------
// Delay the Data Record from the RDS to match pipe delay
//-----------------------------------------------------------------------------
begin // At reset reset all of them to zero.
rds2dms_data_del <= 128'h0;
rds2dms_data_sel_del <= 1'h0;
rds2dms_d_ptr_del <= 4'h0;
rds2dms_data_del <= rds2dms_data;
rds2dms_data_sel_del <= rds2dms_data_sel;
rds2dms_d_ptr_del <= rds2dms_d_ptr;
//-----------------------------------------------------------------------------
// Flop the Outputs to the DIU Block
//-----------------------------------------------------------------------------
begin // At reset reset all of them to zero.
im2di_addr <= {`FIRE_DLC_IRD_ADDR_WDTH{1'h0}};
im2di_data <= {`FIRE_DLC_IRD_DATA_WDTH{1'h0}};
im2di_dpar <= {`FIRE_DLC_IRD_DPAR_WDTH{1'h0}};
im2di_wr <= rds2dms_data_sel_del;
im2di_addr <= rds2dms_d_ptr_del;
im2di_data <= rds2dms_data_del;
im2di_dpar <= rds2dms_dpar_del;