// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_error_log_en_reg.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// GNU General Public License for more details.
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// ========== Copyright Header End ============================================
module dmu_imu_ics_csr_imu_error_log_en_reg
imu_error_log_en_reg_w_ld,
imu_error_log_en_reg_csrbus_read_data,
imu_error_log_en_reg_spare_log_en_hw_read,
imu_error_log_en_reg_eq_over_log_en_hw_read,
imu_error_log_en_reg_eq_not_en_log_en_hw_read,
imu_error_log_en_reg_msi_mal_err_log_en_hw_read,
imu_error_log_en_reg_msi_par_err_log_en_hw_read,
imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read,
imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read,
imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read,
imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read,
imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read,
imu_error_log_en_reg_msi_not_en_log_en_hw_read
//====================================================================
//====================================================================
input por_l; // Reset signal
input imu_error_log_en_reg_w_ld; // SW load bus
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
output [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH-1:0] imu_error_log_en_reg_csrbus_read_data;
output [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_INT_SLC] imu_error_log_en_reg_spare_log_en_hw_read;
// This signal provides the current value of
// imu_error_log_en_reg_spare_log_en.
output imu_error_log_en_reg_eq_over_log_en_hw_read; // This signal provides the
// imu_error_log_en_reg_eq_over_log_en.
output imu_error_log_en_reg_eq_not_en_log_en_hw_read; // This signal provides
// imu_error_log_en_reg_eq_not_en_log_en.
output imu_error_log_en_reg_msi_mal_err_log_en_hw_read; // This signal provides
// imu_error_log_en_reg_msi_mal_err_log_en.
output imu_error_log_en_reg_msi_par_err_log_en_hw_read; // This signal provides
// imu_error_log_en_reg_msi_par_err_log_en.
output imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read; // This signal
// imu_error_log_en_reg_pmeack_mes_not_en_log_en.
output imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read; // This signal
// imu_error_log_en_reg_pmpme_mes_not_en_log_en.
output imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read; // This signal
// imu_error_log_en_reg_fatal_mes_not_en_log_en.
output imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read; // This signal
// imu_error_log_en_reg_nonfatal_mes_not_en_log_en.
output imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read; // This signal
// imu_error_log_en_reg_cor_mes_not_en_log_en.
output imu_error_log_en_reg_msi_not_en_log_en_hw_read; // This signal provides
// imu_error_log_en_reg_msi_not_en_log_en.
//====================================================================
//====================================================================
wire por_l; // Reset signal
wire imu_error_log_en_reg_w_ld; // SW load bus
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
wire [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH-1:0] imu_error_log_en_reg_csrbus_read_data;
wire [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_INT_SLC] imu_error_log_en_reg_spare_log_en_hw_read;
// This signal provides the current value of
// imu_error_log_en_reg_spare_log_en.
wire imu_error_log_en_reg_eq_over_log_en_hw_read; // This signal provides the
// imu_error_log_en_reg_eq_over_log_en.
wire imu_error_log_en_reg_eq_not_en_log_en_hw_read; // This signal provides the
// imu_error_log_en_reg_eq_not_en_log_en.
wire imu_error_log_en_reg_msi_mal_err_log_en_hw_read; // This signal provides
// imu_error_log_en_reg_msi_mal_err_log_en.
wire imu_error_log_en_reg_msi_par_err_log_en_hw_read; // This signal provides
// imu_error_log_en_reg_msi_par_err_log_en.
wire imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read; // This signal
// imu_error_log_en_reg_pmeack_mes_not_en_log_en.
wire imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read; // This signal
// imu_error_log_en_reg_pmpme_mes_not_en_log_en.
wire imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read; // This signal
// imu_error_log_en_reg_fatal_mes_not_en_log_en.
wire imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read; // This signal
// imu_error_log_en_reg_nonfatal_mes_not_en_log_en.
wire imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read; // This signal
// imu_error_log_en_reg_cor_mes_not_en_log_en.
wire imu_error_log_en_reg_msi_not_en_log_en_hw_read; // This signal provides
// imu_error_log_en_reg_msi_not_en_log_en.
//====================================================================
//====================================================================
// synopsys translate_off
reg [`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH-1:0] omni_data;
// vlint flag_unsynthesizable_initial off
omni_data = `FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_WIDTH'b0;
end// vlint flag_unsynthesizable_initial on
//----- Hardware Data Out Mux Assignments
assign imu_error_log_en_reg_spare_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data
[`FIRE_DLC_IMU_ICS_CSR_IMU_ERROR_LOG_EN_REG_SPARE_LOG_EN_SLC];
assign imu_error_log_en_reg_eq_over_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data [9];
assign imu_error_log_en_reg_eq_not_en_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data [8];
assign imu_error_log_en_reg_msi_mal_err_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data [7];
assign imu_error_log_en_reg_msi_par_err_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data [6];
assign imu_error_log_en_reg_pmeack_mes_not_en_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data [5];
assign imu_error_log_en_reg_pmpme_mes_not_en_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data [4];
assign imu_error_log_en_reg_fatal_mes_not_en_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data [3];
assign imu_error_log_en_reg_nonfatal_mes_not_en_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data [2];
assign imu_error_log_en_reg_cor_mes_not_en_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data [1];
assign imu_error_log_en_reg_msi_not_en_log_en_hw_read=
imu_error_log_en_reg_csrbus_read_data [0];
//====================================================================
// Instantiation of entries
//====================================================================
dmu_imu_ics_csr_imu_error_log_en_reg_entry imu_error_log_en_reg_0
// synopsys translate_off
.w_ld (imu_error_log_en_reg_w_ld),
.csrbus_wr_data (csrbus_wr_data),
.imu_error_log_en_reg_csrbus_read_data (imu_error_log_en_reg_csrbus_read_data)
endmodule // dmu_imu_ics_csr_imu_error_log_en_reg