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// OpenSPARC T2 Processor File: dmu_imu_iss_csr_interrupt_mapping_42.v
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module dmu_imu_iss_csr_interrupt_mapping_42
interrupt_mapping_42_w_ld,
interrupt_mapping_42_csrbus_read_data,
interrupt_mapping_42_mdo_mode_hw_read,
interrupt_mapping_42_v_hw_read,
interrupt_mapping_42_t_id_hw_read,
interrupt_mapping_42_int_cntrl_num_hw_read
//====================================================================
//====================================================================
input rst_l; // Reset signal
input interrupt_mapping_42_w_ld; // SW load bus
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_WIDTH-1:0] interrupt_mapping_42_csrbus_read_data;
output interrupt_mapping_42_mdo_mode_hw_read; // This signal provides the
// interrupt_mapping_42_mdo_mode.
output interrupt_mapping_42_v_hw_read; // This signal provides the current
// value of interrupt_mapping_42_v.
output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_INT_SLC] interrupt_mapping_42_t_id_hw_read;
// This signal provides the current value of interrupt_mapping_42_t_id.
output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_42_int_cntrl_num_hw_read;
// This signal provides the current value of
// interrupt_mapping_42_int_cntrl_num.
//====================================================================
//====================================================================
wire rst_l; // Reset signal
wire interrupt_mapping_42_w_ld; // SW load bus
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_WIDTH-1:0] interrupt_mapping_42_csrbus_read_data;
wire interrupt_mapping_42_mdo_mode_hw_read; // This signal provides the current
// interrupt_mapping_42_mdo_mode.
wire interrupt_mapping_42_v_hw_read; // This signal provides the current value
// of interrupt_mapping_42_v.
wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_INT_SLC] interrupt_mapping_42_t_id_hw_read;
// This signal provides the current value of interrupt_mapping_42_t_id.
wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_42_int_cntrl_num_hw_read;
// This signal provides the current value of
// interrupt_mapping_42_int_cntrl_num.
//====================================================================
//====================================================================
// synopsys translate_off
reg [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_WIDTH-1:0] omni_data;
// vlint flag_unsynthesizable_initial off
omni_data = `FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_WIDTH'b0;
end// vlint flag_unsynthesizable_initial on
//----- Hardware Data Out Mux Assignments
assign interrupt_mapping_42_mdo_mode_hw_read=
interrupt_mapping_42_csrbus_read_data [63];
assign interrupt_mapping_42_v_hw_read=
interrupt_mapping_42_csrbus_read_data [31];
assign interrupt_mapping_42_t_id_hw_read=
interrupt_mapping_42_csrbus_read_data
[`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_SLC];
assign interrupt_mapping_42_int_cntrl_num_hw_read=
interrupt_mapping_42_csrbus_read_data
[`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_SLC];
//====================================================================
// Instantiation of entries
//====================================================================
dmu_imu_iss_csr_interrupt_mapping_42_entry interrupt_mapping_42_0
// synopsys translate_off
.w_ld (interrupt_mapping_42_w_ld),
.csrbus_wr_data (csrbus_wr_data),
.interrupt_mapping_42_csrbus_read_data (interrupt_mapping_42_csrbus_read_data)
endmodule // dmu_imu_iss_csr_interrupt_mapping_42