// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_imu_rds_intx_csr_int_c_int_clr_reg.v
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module dmu_imu_rds_intx_csr_int_c_int_clr_reg
int_c_int_clr_reg_csrbus_read_data,
int_c_int_clr_reg_clr_hw_ld,
int_c_int_clr_reg_clr_hw_write,
int_c_int_clr_reg_clr_hw_read
//====================================================================
//====================================================================
input rst_l; // Reset signal
input int_c_int_clr_reg_w_ld; // SW load bus
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
output [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH-1:0] int_c_int_clr_reg_csrbus_read_data;
input int_c_int_clr_reg_clr_hw_ld; // Hardware load enable for
// int_c_int_clr_reg_clr. When set, <hw
// write signal> will be loaded into
input int_c_int_clr_reg_clr_hw_write; // data bus for hw loading of
// int_c_int_clr_reg_clr.
output int_c_int_clr_reg_clr_hw_read; // This signal provides the current value
// of int_c_int_clr_reg_clr.
//====================================================================
//====================================================================
wire rst_l; // Reset signal
wire int_c_int_clr_reg_w_ld; // SW load bus
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
wire [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH-1:0] int_c_int_clr_reg_csrbus_read_data;
wire int_c_int_clr_reg_clr_hw_ld; // Hardware load enable for
// int_c_int_clr_reg_clr. When set, <hw write
// signal> will be loaded into
wire int_c_int_clr_reg_clr_hw_write; // data bus for hw loading of
// int_c_int_clr_reg_clr.
wire int_c_int_clr_reg_clr_hw_read; // This signal provides the current value
// of int_c_int_clr_reg_clr.
//====================================================================
//====================================================================
// synopsys translate_off
reg [`FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH-1:0] omni_data;
// vlint flag_unsynthesizable_initial off
omni_data = `FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH'b0;
end// vlint flag_unsynthesizable_initial on
//----- Hardware Data Out Mux Assignments
assign int_c_int_clr_reg_clr_hw_read=
int_c_int_clr_reg_csrbus_read_data [0];
//====================================================================
// Instantiation of entries
//====================================================================
dmu_imu_rds_intx_csr_int_c_int_clr_reg_entry int_c_int_clr_reg_0
// synopsys translate_off
.w_ld (int_c_int_clr_reg_w_ld),
.csrbus_wr_data (csrbus_wr_data),
.int_c_int_clr_reg_csrbus_read_data (int_c_int_clr_reg_csrbus_read_data),
.int_c_int_clr_reg_clr_hw_ld (int_c_int_clr_reg_clr_hw_ld),
.int_c_int_clr_reg_clr_hw_write (int_c_int_clr_reg_clr_hw_write)
endmodule // dmu_imu_rds_intx_csr_int_c_int_clr_reg