// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_imu_rds_mess_csr_pm_pme_mapping_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// choice is available it will apply instead, Sun elects to use only
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// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
module dmu_imu_rds_mess_csr_pm_pme_mapping_entry
// synopsys translate_off
pm_pme_mapping_csrbus_read_data
//====================================================================
//====================================================================
// synopsys translate_off
input omni_ld; // Omni load
// vlint flag_input_port_not_connected off
input [`FIRE_DLC_IMU_RDS_MESS_CSR_PM_PME_MAPPING_WIDTH - 1:0] omni_data;
// vlint flag_input_port_not_connected on
input clk; // Clock signal
input rst_l; // Reset signal
// vlint flag_input_port_not_connected off
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_IMU_RDS_MESS_CSR_PM_PME_MAPPING_WIDTH-1:0] pm_pme_mapping_csrbus_read_data;
//====================================================================
//====================================================================
// synopsys translate_off
wire omni_ld; // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_DLC_IMU_RDS_MESS_CSR_PM_PME_MAPPING_WIDTH - 1:0] omni_data;
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk; // Clock signal
wire rst_l; // Reset signal
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_IMU_RDS_MESS_CSR_PM_PME_MAPPING_WIDTH-1:0] pm_pme_mapping_csrbus_read_data;
//====================================================================
//====================================================================
wire [0:0] reset_v = 1'h0;
wire [5:0] reset_eqnum = 6'h0;
//----- Active high reset wires
wire rst_l_active_high = ~rst_l;
//====================================================
// Instantiation of flops
//====================================================
// synopsys translate_off
.omni_data (omni_data[0]),
.rst (rst_l_active_high),
.rst_val (reset_eqnum[0]),
.csr_data (csrbus_wr_data[0]),
.q (pm_pme_mapping_csrbus_read_data[0])
// synopsys translate_off
.omni_data (omni_data[1]),
.rst (rst_l_active_high),
.rst_val (reset_eqnum[1]),
.csr_data (csrbus_wr_data[1]),
.q (pm_pme_mapping_csrbus_read_data[1])
// synopsys translate_off
.omni_data (omni_data[2]),
.rst (rst_l_active_high),
.rst_val (reset_eqnum[2]),
.csr_data (csrbus_wr_data[2]),
.q (pm_pme_mapping_csrbus_read_data[2])
// synopsys translate_off
.omni_data (omni_data[3]),
.rst (rst_l_active_high),
.rst_val (reset_eqnum[3]),
.csr_data (csrbus_wr_data[3]),
.q (pm_pme_mapping_csrbus_read_data[3])
// synopsys translate_off
.omni_data (omni_data[4]),
.rst (rst_l_active_high),
.rst_val (reset_eqnum[4]),
.csr_data (csrbus_wr_data[4]),
.q (pm_pme_mapping_csrbus_read_data[4])
// synopsys translate_off
.omni_data (omni_data[5]),
.rst (rst_l_active_high),
.rst_val (reset_eqnum[5]),
.csr_data (csrbus_wr_data[5]),
.q (pm_pme_mapping_csrbus_read_data[5])
assign pm_pme_mapping_csrbus_read_data[6] = 1'b0; // bit 6
assign pm_pme_mapping_csrbus_read_data[7] = 1'b0; // bit 7
assign pm_pme_mapping_csrbus_read_data[8] = 1'b0; // bit 8
assign pm_pme_mapping_csrbus_read_data[9] = 1'b0; // bit 9
assign pm_pme_mapping_csrbus_read_data[10] = 1'b0; // bit 10
assign pm_pme_mapping_csrbus_read_data[11] = 1'b0; // bit 11
assign pm_pme_mapping_csrbus_read_data[12] = 1'b0; // bit 12
assign pm_pme_mapping_csrbus_read_data[13] = 1'b0; // bit 13
assign pm_pme_mapping_csrbus_read_data[14] = 1'b0; // bit 14
assign pm_pme_mapping_csrbus_read_data[15] = 1'b0; // bit 15
assign pm_pme_mapping_csrbus_read_data[16] = 1'b0; // bit 16
assign pm_pme_mapping_csrbus_read_data[17] = 1'b0; // bit 17
assign pm_pme_mapping_csrbus_read_data[18] = 1'b0; // bit 18
assign pm_pme_mapping_csrbus_read_data[19] = 1'b0; // bit 19
assign pm_pme_mapping_csrbus_read_data[20] = 1'b0; // bit 20
assign pm_pme_mapping_csrbus_read_data[21] = 1'b0; // bit 21
assign pm_pme_mapping_csrbus_read_data[22] = 1'b0; // bit 22
assign pm_pme_mapping_csrbus_read_data[23] = 1'b0; // bit 23
assign pm_pme_mapping_csrbus_read_data[24] = 1'b0; // bit 24
assign pm_pme_mapping_csrbus_read_data[25] = 1'b0; // bit 25
assign pm_pme_mapping_csrbus_read_data[26] = 1'b0; // bit 26
assign pm_pme_mapping_csrbus_read_data[27] = 1'b0; // bit 27
assign pm_pme_mapping_csrbus_read_data[28] = 1'b0; // bit 28
assign pm_pme_mapping_csrbus_read_data[29] = 1'b0; // bit 29
assign pm_pme_mapping_csrbus_read_data[30] = 1'b0; // bit 30
assign pm_pme_mapping_csrbus_read_data[31] = 1'b0; // bit 31
assign pm_pme_mapping_csrbus_read_data[32] = 1'b0; // bit 32
assign pm_pme_mapping_csrbus_read_data[33] = 1'b0; // bit 33
assign pm_pme_mapping_csrbus_read_data[34] = 1'b0; // bit 34
assign pm_pme_mapping_csrbus_read_data[35] = 1'b0; // bit 35
assign pm_pme_mapping_csrbus_read_data[36] = 1'b0; // bit 36
assign pm_pme_mapping_csrbus_read_data[37] = 1'b0; // bit 37
assign pm_pme_mapping_csrbus_read_data[38] = 1'b0; // bit 38
assign pm_pme_mapping_csrbus_read_data[39] = 1'b0; // bit 39
assign pm_pme_mapping_csrbus_read_data[40] = 1'b0; // bit 40
assign pm_pme_mapping_csrbus_read_data[41] = 1'b0; // bit 41
assign pm_pme_mapping_csrbus_read_data[42] = 1'b0; // bit 42
assign pm_pme_mapping_csrbus_read_data[43] = 1'b0; // bit 43
assign pm_pme_mapping_csrbus_read_data[44] = 1'b0; // bit 44
assign pm_pme_mapping_csrbus_read_data[45] = 1'b0; // bit 45
assign pm_pme_mapping_csrbus_read_data[46] = 1'b0; // bit 46
assign pm_pme_mapping_csrbus_read_data[47] = 1'b0; // bit 47
assign pm_pme_mapping_csrbus_read_data[48] = 1'b0; // bit 48
assign pm_pme_mapping_csrbus_read_data[49] = 1'b0; // bit 49
assign pm_pme_mapping_csrbus_read_data[50] = 1'b0; // bit 50
assign pm_pme_mapping_csrbus_read_data[51] = 1'b0; // bit 51
assign pm_pme_mapping_csrbus_read_data[52] = 1'b0; // bit 52
assign pm_pme_mapping_csrbus_read_data[53] = 1'b0; // bit 53
assign pm_pme_mapping_csrbus_read_data[54] = 1'b0; // bit 54
assign pm_pme_mapping_csrbus_read_data[55] = 1'b0; // bit 55
assign pm_pme_mapping_csrbus_read_data[56] = 1'b0; // bit 56
assign pm_pme_mapping_csrbus_read_data[57] = 1'b0; // bit 57
assign pm_pme_mapping_csrbus_read_data[58] = 1'b0; // bit 58
assign pm_pme_mapping_csrbus_read_data[59] = 1'b0; // bit 59
assign pm_pme_mapping_csrbus_read_data[60] = 1'b0; // bit 60
assign pm_pme_mapping_csrbus_read_data[61] = 1'b0; // bit 61
assign pm_pme_mapping_csrbus_read_data[62] = 1'b0; // bit 62
// synopsys translate_off
.omni_data (omni_data[63]),
.rst (rst_l_active_high),
.csr_data (csrbus_wr_data[63]),
.q (pm_pme_mapping_csrbus_read_data[63])
endmodule // dmu_imu_rds_mess_csr_pm_pme_mapping_entry