// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_imu_scs.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
// Inputs from RDS sub-block
// Inputs from the EQS sub-block
// Outputs to ORS state Sub-block
//############################################################################
//############################################################################
//------------------------------------------------------------------------
// Clock and Reset Signals
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//------------------------------------------------------------------------
input [`FIRE_DLC_IIN_REC_WDTH-1:0] rds2scs_rcd;
//------------------------------------------------------------------------
// Input from Decoder sub-block
//------------------------------------------------------------------------
//------------------------------------------------------------------------
// Output to Out Record Sub-block
//------------------------------------------------------------------------
output [`FIRE_DLC_IIN_REC_WDTH-1:0] scs2ors_rcd;
output scs2ics_eq_not_en_error;
output [63:0] scs2ics_error_data;
//------------------------------------------------------------------------
//------------------------------------------------------------------------
input [2:0] dbg2scs_dbg_sel_a;
input [2:0] dbg2scs_dbg_sel_b;
output [`FIRE_DEBUG_WDTH-1:0] scs2dbg_dbg_a;
output [`FIRE_DEBUG_WDTH-1:0] scs2dbg_dbg_b;
//############################################################################
//############################################################################
//############################################################################
//############################################################################
//**************************************************
//**************************************************
//-------------------------------------
//-------------------------------------
wire [`FIRE_DLC_IIN_TYPE_WDTH -1:0] in_type;
//-------------------------------------
// Packet Type Decode Wires
//-------------------------------------
//-------------------------------------
// Signal to look at EQ lookup results
//-------------------------------------
//-------------------------------------
// Signal for out record type
//-------------------------------------
wire [`FIRE_DLC_IIN_TYPE_WDTH -1:0] out_type;
//**************************************************
// Registers that Are Not Flops
//**************************************************
reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_a;
reg [`FIRE_DEBUG_WDTH-1:0] n_dbg_b;
//**************************************************
// Registers that Are Flops
//**************************************************
//-------------------------------------
//-------------------------------------
reg [`FIRE_DLC_IIN_REC_WDTH-1:0] scs2ors_rcd;
reg [`FIRE_DEBUG_WDTH-1:0] dbg_a;
reg [`FIRE_DEBUG_WDTH-1:0] dbg_b;
//############################################################################
//############################################################################
//############################################################################
//############################################################################
//--------------------------------
// Grab the Incomming Packet Type
//--------------------------------
assign in_type = rds2scs_rcd[`FIRE_DLC_IIN_TYPE_MSB:`FIRE_DLC_IIN_TYPE_LSB];
//--------------------------------
// Decode Incomming Packet Type
// See if the packet is either
//--------------------------------
assign pkt_is_msi = in_type[`FIRE_DLC_IMU_OTYPE_DECODE_2] &
!in_type[`FIRE_DLC_IMU_OTYPE_DECODE_1] &
!in_type[`FIRE_DLC_IMU_OTYPE_DECODE_0];
assign pkt_is_mes = !in_type[`FIRE_DLC_IMU_OTYPE_DECODE_2];
//--------------------------------
// Form check results Signal
//--------------------------------
assign check_results = pkt_is_msi | pkt_is_mes;
//--------------------------------------
// Calculate Proper Output Type
// If need to check results
// -Check to see if results are good
// If dont need to check results
//--------------------------------------
assign out_type = check_results ? ( eqs2scs_eq_ok ? in_type : `FIRE_DLC_IMU_TYPE_NULL) : in_type;
//--------------------------------
// Error Checking for Interrupt
// - get an EQ wite (mess or msi)
//--------------------------------
assign scs2ics_eq_not_en_error = rds2scs_rcd_sel & check_results & eqs2scs_eq_not_en;
assign scs2ics_error_data = { rds2scs_rcd[`FIRE_DLC_IIN_TYPE_MSB-1 : `FIRE_DLC_IIN_TYPE_LSB],
rds2scs_rcd[`FIRE_DLC_IIN_LEN_MSB : `FIRE_DLC_IIN_LEN_LSB],
rds2scs_rcd[`FIRE_DLC_IIN_REQID_MSB : `FIRE_DLC_IIN_REQID_LSB],
rds2scs_rcd[`FIRE_DLC_IIN_TLPTAG_MSB : `FIRE_DLC_IIN_TLPTAG_LSB],
rds2scs_rcd[`FIRE_DLC_IIN_DATA_MSB : `FIRE_DLC_IIN_DATA_LSB],
//-----------------------------------------------------
//-----------------------------------------------------
always @ (dbg2scs_dbg_sel_a or rds2scs_rcd_sel or in_type or pkt_is_msi or pkt_is_mes or
check_results or eqs2scs_eq_ok or eqs2scs_eq_not_en or scs2ics_eq_not_en_error)
case (dbg2scs_dbg_sel_a) // synopsys infer_mux
3'b000: n_dbg_a = {rds2scs_rcd_sel, in_type[6:0]};
3'b001: n_dbg_a = {3'h0, pkt_is_msi, pkt_is_mes, check_results, eqs2scs_eq_ok, eqs2scs_eq_not_en};
3'b010: n_dbg_a = {7'h0, scs2ics_eq_not_en_error};
always @ (dbg2scs_dbg_sel_b or rds2scs_rcd_sel or in_type or pkt_is_msi or pkt_is_mes or
check_results or eqs2scs_eq_ok or eqs2scs_eq_not_en or scs2ics_eq_not_en_error)
case (dbg2scs_dbg_sel_b) // synopsys infer_mux
3'b000: n_dbg_b = {rds2scs_rcd_sel, in_type[6:0]};
3'b001: n_dbg_b = {3'h0, pkt_is_msi, pkt_is_mes, check_results, eqs2scs_eq_ok, eqs2scs_eq_not_en};
3'b010: n_dbg_b = {7'h0, scs2ics_eq_not_en_error};
assign scs2dbg_dbg_a = dbg_a;
assign scs2dbg_dbg_b = dbg_b;
//############################################################################
//############################################################################
//-----------------------------------------------------------------------------
// Delay all of the In Record information to keep in step with the pipeline.
//-----------------------------------------------------------------------------
scs2ors_rcd <= {`FIRE_DLC_IIN_REC_WDTH{1'h0}};
scs2ors_rcd <= {out_type,rds2scs_rcd[`FIRE_DLC_IIN_TC_MSB:0]};
scs2ors_rcd_sel <= rds2scs_rcd_sel;