// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_mmu_csr_flts_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
module dmu_mmu_csr_flts_entry
// synopsys translate_off
//====================================================================
//====================================================================
// synopsys translate_off
input omni_ld; // Omni load
// vlint flag_input_port_not_connected off
input [`FIRE_DLC_MMU_CSR_FLTS_WIDTH - 1:0] omni_data; // Omni write data
// vlint flag_input_port_not_connected on
input clk; // Clock signal
input por_l; // Reset signal
// vlint flag_input_port_not_connected off
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] flts_csrbus_read_data; // SW read
input flts_entry_hw_ld; // Hardware load enable for flts_entry. When set, <hw
// write signal> will be loaded into flts.
input [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write;
// data bus for hw loading of flts_entry.
input flts_type_hw_ld; // Hardware load enable for flts_type. When set, <hw
// write signal> will be loaded into flts.
input [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write; // data bus
input flts_id_hw_ld; // Hardware load enable for flts_id. When set, <hw write
// signal> will be loaded into flts.
input [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write; // data bus for hw
//====================================================================
//====================================================================
// synopsys translate_off
wire omni_ld; // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_DLC_MMU_CSR_FLTS_WIDTH - 1:0] omni_data; // Omni write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk; // Clock signal
wire por_l; // Reset signal
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] flts_csrbus_read_data; // SW read data
wire flts_entry_hw_ld; // Hardware load enable for flts_entry. When set, <hw
// write signal> will be loaded into flts.
wire [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write; // data bus
wire flts_type_hw_ld; // Hardware load enable for flts_type. When set, <hw
// write signal> will be loaded into flts.
wire [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write; // data bus for
wire flts_id_hw_ld; // Hardware load enable for flts_id. When set, <hw write
// signal> will be loaded into flts.
wire [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write; // data bus for hw
//====================================================================
//====================================================================
wire [8:0] reset_entry = 9'b0;
wire [6:0] reset_type = 7'b0;
wire [15:0] reset_id = 16'b0;
//----- Active high reset wires
wire por_l_active_high = ~por_l;
//====================================================
// Instantiation of flops
//====================================================
// synopsys translate_off
.omni_data (omni_data[0]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[0]),
.hw_data (flts_id_hw_write[0]),
.q (flts_csrbus_read_data[0])
// synopsys translate_off
.omni_data (omni_data[1]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[1]),
.hw_data (flts_id_hw_write[1]),
.q (flts_csrbus_read_data[1])
// synopsys translate_off
.omni_data (omni_data[2]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[2]),
.hw_data (flts_id_hw_write[2]),
.q (flts_csrbus_read_data[2])
// synopsys translate_off
.omni_data (omni_data[3]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[3]),
.hw_data (flts_id_hw_write[3]),
.q (flts_csrbus_read_data[3])
// synopsys translate_off
.omni_data (omni_data[4]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[4]),
.hw_data (flts_id_hw_write[4]),
.q (flts_csrbus_read_data[4])
// synopsys translate_off
.omni_data (omni_data[5]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[5]),
.hw_data (flts_id_hw_write[5]),
.q (flts_csrbus_read_data[5])
// synopsys translate_off
.omni_data (omni_data[6]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[6]),
.hw_data (flts_id_hw_write[6]),
.q (flts_csrbus_read_data[6])
// synopsys translate_off
.omni_data (omni_data[7]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[7]),
.hw_data (flts_id_hw_write[7]),
.q (flts_csrbus_read_data[7])
// synopsys translate_off
.omni_data (omni_data[8]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[8]),
.hw_data (flts_id_hw_write[8]),
.q (flts_csrbus_read_data[8])
// synopsys translate_off
.omni_data (omni_data[9]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[9]),
.hw_data (flts_id_hw_write[9]),
.q (flts_csrbus_read_data[9])
// synopsys translate_off
.omni_data (omni_data[10]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[10]),
.hw_data (flts_id_hw_write[10]),
.q (flts_csrbus_read_data[10])
// synopsys translate_off
.omni_data (omni_data[11]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[11]),
.hw_data (flts_id_hw_write[11]),
.q (flts_csrbus_read_data[11])
// synopsys translate_off
.omni_data (omni_data[12]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[12]),
.hw_data (flts_id_hw_write[12]),
.q (flts_csrbus_read_data[12])
// synopsys translate_off
.omni_data (omni_data[13]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[13]),
.hw_data (flts_id_hw_write[13]),
.q (flts_csrbus_read_data[13])
// synopsys translate_off
.omni_data (omni_data[14]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[14]),
.hw_data (flts_id_hw_write[14]),
.q (flts_csrbus_read_data[14])
// synopsys translate_off
.omni_data (omni_data[15]),
.rst (por_l_active_high),
.csr_data (csrbus_wr_data[15]),
.hw_data (flts_id_hw_write[15]),
.q (flts_csrbus_read_data[15])
// synopsys translate_off
.omni_data (omni_data[16]),
.rst (por_l_active_high),
.rst_val (reset_type[0]),
.csr_data (csrbus_wr_data[16]),
.hw_ld (flts_type_hw_ld),
.hw_data (flts_type_hw_write[0]),
.q (flts_csrbus_read_data[16])
// synopsys translate_off
.omni_data (omni_data[17]),
.rst (por_l_active_high),
.rst_val (reset_type[1]),
.csr_data (csrbus_wr_data[17]),
.hw_ld (flts_type_hw_ld),
.hw_data (flts_type_hw_write[1]),
.q (flts_csrbus_read_data[17])
// synopsys translate_off
.omni_data (omni_data[18]),
.rst (por_l_active_high),
.rst_val (reset_type[2]),
.csr_data (csrbus_wr_data[18]),
.hw_ld (flts_type_hw_ld),
.hw_data (flts_type_hw_write[2]),
.q (flts_csrbus_read_data[18])
// synopsys translate_off
.omni_data (omni_data[19]),
.rst (por_l_active_high),
.rst_val (reset_type[3]),
.csr_data (csrbus_wr_data[19]),
.hw_ld (flts_type_hw_ld),
.hw_data (flts_type_hw_write[3]),
.q (flts_csrbus_read_data[19])
// synopsys translate_off
.omni_data (omni_data[20]),
.rst (por_l_active_high),
.rst_val (reset_type[4]),
.csr_data (csrbus_wr_data[20]),
.hw_ld (flts_type_hw_ld),
.hw_data (flts_type_hw_write[4]),
.q (flts_csrbus_read_data[20])
// synopsys translate_off
.omni_data (omni_data[21]),
.rst (por_l_active_high),
.rst_val (reset_type[5]),
.csr_data (csrbus_wr_data[21]),
.hw_ld (flts_type_hw_ld),
.hw_data (flts_type_hw_write[5]),
.q (flts_csrbus_read_data[21])
// synopsys translate_off
.omni_data (omni_data[22]),
.rst (por_l_active_high),
.rst_val (reset_type[6]),
.csr_data (csrbus_wr_data[22]),
.hw_ld (flts_type_hw_ld),
.hw_data (flts_type_hw_write[6]),
.q (flts_csrbus_read_data[22])
assign flts_csrbus_read_data[23] = 1'b0; // bit 23
assign flts_csrbus_read_data[24] = 1'b0; // bit 24
assign flts_csrbus_read_data[25] = 1'b0; // bit 25
assign flts_csrbus_read_data[26] = 1'b0; // bit 26
assign flts_csrbus_read_data[27] = 1'b0; // bit 27
assign flts_csrbus_read_data[28] = 1'b0; // bit 28
assign flts_csrbus_read_data[29] = 1'b0; // bit 29
assign flts_csrbus_read_data[30] = 1'b0; // bit 30
assign flts_csrbus_read_data[31] = 1'b0; // bit 31
// synopsys translate_off
.omni_data (omni_data[32]),
.rst (por_l_active_high),
.rst_val (reset_entry[0]),
.csr_data (csrbus_wr_data[32]),
.hw_ld (flts_entry_hw_ld),
.hw_data (flts_entry_hw_write[0]),
.q (flts_csrbus_read_data[32])
// synopsys translate_off
.omni_data (omni_data[33]),
.rst (por_l_active_high),
.rst_val (reset_entry[1]),
.csr_data (csrbus_wr_data[33]),
.hw_ld (flts_entry_hw_ld),
.hw_data (flts_entry_hw_write[1]),
.q (flts_csrbus_read_data[33])
// synopsys translate_off
.omni_data (omni_data[34]),
.rst (por_l_active_high),
.rst_val (reset_entry[2]),
.csr_data (csrbus_wr_data[34]),
.hw_ld (flts_entry_hw_ld),
.hw_data (flts_entry_hw_write[2]),
.q (flts_csrbus_read_data[34])
// synopsys translate_off
.omni_data (omni_data[35]),
.rst (por_l_active_high),
.rst_val (reset_entry[3]),
.csr_data (csrbus_wr_data[35]),
.hw_ld (flts_entry_hw_ld),
.hw_data (flts_entry_hw_write[3]),
.q (flts_csrbus_read_data[35])
// synopsys translate_off
.omni_data (omni_data[36]),
.rst (por_l_active_high),
.rst_val (reset_entry[4]),
.csr_data (csrbus_wr_data[36]),
.hw_ld (flts_entry_hw_ld),
.hw_data (flts_entry_hw_write[4]),
.q (flts_csrbus_read_data[36])
// synopsys translate_off
.omni_data (omni_data[37]),
.rst (por_l_active_high),
.rst_val (reset_entry[5]),
.csr_data (csrbus_wr_data[37]),
.hw_ld (flts_entry_hw_ld),
.hw_data (flts_entry_hw_write[5]),
.q (flts_csrbus_read_data[37])
// synopsys translate_off
.omni_data (omni_data[38]),
.rst (por_l_active_high),
.rst_val (reset_entry[6]),
.csr_data (csrbus_wr_data[38]),
.hw_ld (flts_entry_hw_ld),
.hw_data (flts_entry_hw_write[6]),
.q (flts_csrbus_read_data[38])
// synopsys translate_off
.omni_data (omni_data[39]),
.rst (por_l_active_high),
.rst_val (reset_entry[7]),
.csr_data (csrbus_wr_data[39]),
.hw_ld (flts_entry_hw_ld),
.hw_data (flts_entry_hw_write[7]),
.q (flts_csrbus_read_data[39])
// synopsys translate_off
.omni_data (omni_data[40]),
.rst (por_l_active_high),
.rst_val (reset_entry[8]),
.csr_data (csrbus_wr_data[40]),
.hw_ld (flts_entry_hw_ld),
.hw_data (flts_entry_hw_write[8]),
.q (flts_csrbus_read_data[40])
assign flts_csrbus_read_data[41] = 1'b0; // bit 41
assign flts_csrbus_read_data[42] = 1'b0; // bit 42
assign flts_csrbus_read_data[43] = 1'b0; // bit 43
assign flts_csrbus_read_data[44] = 1'b0; // bit 44
assign flts_csrbus_read_data[45] = 1'b0; // bit 45
assign flts_csrbus_read_data[46] = 1'b0; // bit 46
assign flts_csrbus_read_data[47] = 1'b0; // bit 47
assign flts_csrbus_read_data[48] = 1'b0; // bit 48
assign flts_csrbus_read_data[49] = 1'b0; // bit 49
assign flts_csrbus_read_data[50] = 1'b0; // bit 50
assign flts_csrbus_read_data[51] = 1'b0; // bit 51
assign flts_csrbus_read_data[52] = 1'b0; // bit 52
assign flts_csrbus_read_data[53] = 1'b0; // bit 53
assign flts_csrbus_read_data[54] = 1'b0; // bit 54
assign flts_csrbus_read_data[55] = 1'b0; // bit 55
assign flts_csrbus_read_data[56] = 1'b0; // bit 56
assign flts_csrbus_read_data[57] = 1'b0; // bit 57
assign flts_csrbus_read_data[58] = 1'b0; // bit 58
assign flts_csrbus_read_data[59] = 1'b0; // bit 59
assign flts_csrbus_read_data[60] = 1'b0; // bit 60
assign flts_csrbus_read_data[61] = 1'b0; // bit 61
assign flts_csrbus_read_data[62] = 1'b0; // bit 62
assign flts_csrbus_read_data[63] = 1'b0; // bit 63
endmodule // dmu_mmu_csr_flts_entry