// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_mmu_csr_fsh_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
module dmu_mmu_csr_fsh_entry
// synopsys translate_off
//====================================================================
//====================================================================
// synopsys translate_off
input omni_ld; // Omni load
// vlint flag_input_port_not_connected off
input [`FIRE_DLC_MMU_CSR_FSH_WIDTH - 1:0] omni_data; // Omni write data
// vlint flag_input_port_not_connected on
input clk; // Clock signal
input rst_l; // Reset signal
// vlint flag_input_port_not_connected off
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_MMU_CSR_FSH_WIDTH-1:0] fsh_csrbus_read_data; // SW read data
//====================================================================
//====================================================================
// synopsys translate_off
wire omni_ld; // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_DLC_MMU_CSR_FSH_WIDTH - 1:0] omni_data; // Omni write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk; // Clock signal
wire rst_l; // Reset signal
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_MMU_CSR_FSH_WIDTH-1:0] fsh_csrbus_read_data; // SW read data
//====================================================================
//====================================================================
wire [32:0] reset_flsh_addr = 33'h0;
//----- Active high reset wires
wire rst_l_active_high = ~rst_l;
//====================================================
// Instantiation of flops
//====================================================
assign fsh_csrbus_read_data[0] = 1'b0; // bit 0
assign fsh_csrbus_read_data[1] = 1'b0; // bit 1
assign fsh_csrbus_read_data[2] = 1'b0; // bit 2
assign fsh_csrbus_read_data[3] = 1'b0; // bit 3
assign fsh_csrbus_read_data[4] = 1'b0; // bit 4
assign fsh_csrbus_read_data[5] = 1'b0; // bit 5
// synopsys translate_off
.omni_data (omni_data[6]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[0]),
.csr_data (csrbus_wr_data[6]),
.q (fsh_csrbus_read_data[6])
// synopsys translate_off
.omni_data (omni_data[7]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[1]),
.csr_data (csrbus_wr_data[7]),
.q (fsh_csrbus_read_data[7])
// synopsys translate_off
.omni_data (omni_data[8]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[2]),
.csr_data (csrbus_wr_data[8]),
.q (fsh_csrbus_read_data[8])
// synopsys translate_off
.omni_data (omni_data[9]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[3]),
.csr_data (csrbus_wr_data[9]),
.q (fsh_csrbus_read_data[9])
// synopsys translate_off
.omni_data (omni_data[10]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[4]),
.csr_data (csrbus_wr_data[10]),
.q (fsh_csrbus_read_data[10])
// synopsys translate_off
.omni_data (omni_data[11]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[5]),
.csr_data (csrbus_wr_data[11]),
.q (fsh_csrbus_read_data[11])
// synopsys translate_off
.omni_data (omni_data[12]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[6]),
.csr_data (csrbus_wr_data[12]),
.q (fsh_csrbus_read_data[12])
// synopsys translate_off
.omni_data (omni_data[13]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[7]),
.csr_data (csrbus_wr_data[13]),
.q (fsh_csrbus_read_data[13])
// synopsys translate_off
.omni_data (omni_data[14]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[8]),
.csr_data (csrbus_wr_data[14]),
.q (fsh_csrbus_read_data[14])
// synopsys translate_off
.omni_data (omni_data[15]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[9]),
.csr_data (csrbus_wr_data[15]),
.q (fsh_csrbus_read_data[15])
// synopsys translate_off
.omni_data (omni_data[16]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[10]),
.csr_data (csrbus_wr_data[16]),
.q (fsh_csrbus_read_data[16])
// synopsys translate_off
.omni_data (omni_data[17]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[11]),
.csr_data (csrbus_wr_data[17]),
.q (fsh_csrbus_read_data[17])
// synopsys translate_off
.omni_data (omni_data[18]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[12]),
.csr_data (csrbus_wr_data[18]),
.q (fsh_csrbus_read_data[18])
// synopsys translate_off
.omni_data (omni_data[19]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[13]),
.csr_data (csrbus_wr_data[19]),
.q (fsh_csrbus_read_data[19])
// synopsys translate_off
.omni_data (omni_data[20]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[14]),
.csr_data (csrbus_wr_data[20]),
.q (fsh_csrbus_read_data[20])
// synopsys translate_off
.omni_data (omni_data[21]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[15]),
.csr_data (csrbus_wr_data[21]),
.q (fsh_csrbus_read_data[21])
// synopsys translate_off
.omni_data (omni_data[22]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[16]),
.csr_data (csrbus_wr_data[22]),
.q (fsh_csrbus_read_data[22])
// synopsys translate_off
.omni_data (omni_data[23]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[17]),
.csr_data (csrbus_wr_data[23]),
.q (fsh_csrbus_read_data[23])
// synopsys translate_off
.omni_data (omni_data[24]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[18]),
.csr_data (csrbus_wr_data[24]),
.q (fsh_csrbus_read_data[24])
// synopsys translate_off
.omni_data (omni_data[25]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[19]),
.csr_data (csrbus_wr_data[25]),
.q (fsh_csrbus_read_data[25])
// synopsys translate_off
.omni_data (omni_data[26]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[20]),
.csr_data (csrbus_wr_data[26]),
.q (fsh_csrbus_read_data[26])
// synopsys translate_off
.omni_data (omni_data[27]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[21]),
.csr_data (csrbus_wr_data[27]),
.q (fsh_csrbus_read_data[27])
// synopsys translate_off
.omni_data (omni_data[28]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[22]),
.csr_data (csrbus_wr_data[28]),
.q (fsh_csrbus_read_data[28])
// synopsys translate_off
.omni_data (omni_data[29]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[23]),
.csr_data (csrbus_wr_data[29]),
.q (fsh_csrbus_read_data[29])
// synopsys translate_off
.omni_data (omni_data[30]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[24]),
.csr_data (csrbus_wr_data[30]),
.q (fsh_csrbus_read_data[30])
// synopsys translate_off
.omni_data (omni_data[31]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[25]),
.csr_data (csrbus_wr_data[31]),
.q (fsh_csrbus_read_data[31])
// synopsys translate_off
.omni_data (omni_data[32]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[26]),
.csr_data (csrbus_wr_data[32]),
.q (fsh_csrbus_read_data[32])
// synopsys translate_off
.omni_data (omni_data[33]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[27]),
.csr_data (csrbus_wr_data[33]),
.q (fsh_csrbus_read_data[33])
// synopsys translate_off
.omni_data (omni_data[34]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[28]),
.csr_data (csrbus_wr_data[34]),
.q (fsh_csrbus_read_data[34])
// synopsys translate_off
.omni_data (omni_data[35]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[29]),
.csr_data (csrbus_wr_data[35]),
.q (fsh_csrbus_read_data[35])
// synopsys translate_off
.omni_data (omni_data[36]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[30]),
.csr_data (csrbus_wr_data[36]),
.q (fsh_csrbus_read_data[36])
// synopsys translate_off
.omni_data (omni_data[37]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[31]),
.csr_data (csrbus_wr_data[37]),
.q (fsh_csrbus_read_data[37])
// synopsys translate_off
.omni_data (omni_data[38]),
.rst (rst_l_active_high),
.rst_val (reset_flsh_addr[32]),
.csr_data (csrbus_wr_data[38]),
.q (fsh_csrbus_read_data[38])
assign fsh_csrbus_read_data[39] = 1'b0; // bit 39
assign fsh_csrbus_read_data[40] = 1'b0; // bit 40
assign fsh_csrbus_read_data[41] = 1'b0; // bit 41
assign fsh_csrbus_read_data[42] = 1'b0; // bit 42
assign fsh_csrbus_read_data[43] = 1'b0; // bit 43
assign fsh_csrbus_read_data[44] = 1'b0; // bit 44
assign fsh_csrbus_read_data[45] = 1'b0; // bit 45
assign fsh_csrbus_read_data[46] = 1'b0; // bit 46
assign fsh_csrbus_read_data[47] = 1'b0; // bit 47
assign fsh_csrbus_read_data[48] = 1'b0; // bit 48
assign fsh_csrbus_read_data[49] = 1'b0; // bit 49
assign fsh_csrbus_read_data[50] = 1'b0; // bit 50
assign fsh_csrbus_read_data[51] = 1'b0; // bit 51
assign fsh_csrbus_read_data[52] = 1'b0; // bit 52
assign fsh_csrbus_read_data[53] = 1'b0; // bit 53
assign fsh_csrbus_read_data[54] = 1'b0; // bit 54
assign fsh_csrbus_read_data[55] = 1'b0; // bit 55
assign fsh_csrbus_read_data[56] = 1'b0; // bit 56
assign fsh_csrbus_read_data[57] = 1'b0; // bit 57
assign fsh_csrbus_read_data[58] = 1'b0; // bit 58
assign fsh_csrbus_read_data[59] = 1'b0; // bit 59
assign fsh_csrbus_read_data[60] = 1'b0; // bit 60
assign fsh_csrbus_read_data[61] = 1'b0; // bit 61
assign fsh_csrbus_read_data[62] = 1'b0; // bit 62
assign fsh_csrbus_read_data[63] = 1'b0; // bit 63
endmodule // dmu_mmu_csr_fsh_entry