// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: l2t_ecc39a_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
//Output: 32bit corrected data
//refer to the comments in parity_gen_32b.v for the position description
// assign c0= parity[0]^(din[0]^din[1])^(din[3]^din[4])^(din[6]^din[8])
// ^(din[10]^din[11])^(din[13]^din[15])^(din[17]^din[19])
// ^(din[21]^din[23])^(din[25]^din[26])^(din[28]^din[30]);
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_10 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_11 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_12 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_13 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_14 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_15 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_20 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_21 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_22a (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_22b (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c0_slice_22c (
// assign c1= parity[1]^(din[0]^din[2])^(din[3]^din[5])^(din[6]^din[9])
// ^(din[10]^din[12])^(din[13]^din[16])^(din[17]^din[20])
// ^(din[21]^din[24])^(din[25]^din[27])^(din[28]^din[31]);
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_10 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_11 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_12 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_13 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_14 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_15 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_20 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_21 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_22a (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c1_slice_22b (
// assign c2= parity[2]^(din[1]^din[2])^(din[3]^din[7])^(din[8]^din[9])
// ^(din[10]^din[14])^(din[15]^din[16])^(din[17]^din[22])
// ^(din[23]^din[24])^(din[25]^din[29])^(din[30]^din[31]);
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_10 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_11 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_12 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_13 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_14 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_15 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_20 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_21 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_22a (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c2_slice_22b (
// assign c3= parity[3]^(din[4]^din[5])^(din[6]^din[7])^(din[8]^din[9])
// ^(din[10]^din[18])^(din[19]^din[20])^(din[21]^din[22])
// ^(din[23]^din[24])^din[25];
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_10 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_11 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_12 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_13 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_14 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_20 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c3_slice_21 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_2__width_1 c3_slice_22a (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_2__width_1 c3_slice_22b (
// assign c4= parity[4]^(din[11]^din[12])^(din[13]^din[14])^
// (din[15]^din[16])^(din[17]^din[18])^(din[19]^din[20])^
// (din[21]^din[22])^(din[23]^din[24])^din[25];
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_10 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_11 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_12 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_13 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_14 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_20 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c4_slice_21 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_2__width_1 c4_slice_22a (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_2__width_1 c4_slice_22b (
// assign c5= parity[5]^(din[26]^din[27])^(din[28]^din[29])^
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c5_slice_10 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c5_slice_11 (
l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 c5_slice_20 (
// //generate total parity flag
//assign c0_intern= parity[0]^(din[0]^din[1])^(din[3]^din[4])^(din[6]^din[8])
// ^(din[10]^din[11])^(din[13]^din[15])^(din[17]^din[19])
// ^(din[21]^din[23])^(din[25]^din[26])^(din[28]^din[30]);
//assign pflag= c0_intern ^
// (( (((parity[1]^parity[2])^(parity[3]^parity[4])) ^
// ((parity[5]^parity[6])^(din[2]^din[5]))) ^
// (((din[7]^din[9])^(din[12]^din[14])) ^
// ((din[16]^din[18])^(din[20]^din[22]))) ) ^
// ((din[24]^din[27])^(din[29]^din[31])) );
l2t_ecc39a_dp_prty_macro__dprty_8x__width_32 prty1_macro
l2t_ecc39a_dp_prty_macro__dprty_8x__width_8 prty2_macro
.din ({1'b0,parity[6:0]})
l2t_ecc39a_dp_inv_macro__dinv_8x__width_2 inv_int_pflags
.dout ({pflag_1_n,pflag_2_n}),
l2t_ecc39a_dp_nand_macro__dnand_32x__width_3 nand_pflag_n
.dout ({pinvterm1,pinvterm2,pflag_n}),
.din0 ({pflag_1_n,pflag_1,pinvterm1}),
.din1 ({pflag_2_n,pflag_2,pinvterm2})
l2t_ecc39a_dp_nand_macro__dnand_32x__width_3 nand_pflag
.dout ({pterm1,pterm2,pflag}),
.din0 ({pflag_1,pflag_1_n,pterm1}),
.din1 ({pflag_2_n,pflag_2,pterm2})
assign cflag= {c5,c4_1,c3_1,c2_1,c1_1,c0_1};
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c0_inv_slice_1
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c0_inv_slice_2
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c1_inv_slice_1
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c1_inv_slice_2
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c2_inv_slice_1
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c2_inv_slice_2
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c3_inv_slice_1
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c3_inv_slice_2
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c4_inv_slice_1
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c4_inv_slice_2
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c5_inv_slice_1
l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 c5_inv_slice_2
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit0_pos_slice_10a (
.dout (err_bit0_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit0_pos_slice_10b (
.dout (err_bit0_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit0_pos_slice_10c (
.din0 (err_bit0_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit1_pos_slice_10a (
.dout (err_bit1_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit1_pos_slice_10b (
.dout (err_bit1_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit1_pos_slice_10c (
.din0 (err_bit1_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit2_pos_slice_10a (
.dout (err_bit2_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit2_pos_slice_10b (
.dout (err_bit2_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit2_pos_slice_10c (
.din0 (err_bit2_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit3_pos_slice_10a (
.dout (err_bit3_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit3_pos_slice_10b (
.dout (err_bit3_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit3_pos_slice_10c (
.din0 (err_bit3_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit4_pos_slice_10a (
.dout (err_bit4_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit4_pos_slice_10b (
.dout (err_bit4_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit4_pos_slice_10c (
.din0 (err_bit4_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit5_pos_slice_10a (
.dout (err_bit5_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit5_pos_slice_10b (
.dout (err_bit5_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit5_pos_slice_10c (
.din0 (err_bit5_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit6_pos_slice_10a (
.dout (err_bit6_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit6_pos_slice_10b (
.dout (err_bit6_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit6_pos_slice_10c (
.din0 (err_bit6_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit7_pos_slice_10a (
.dout (err_bit7_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit7_pos_slice_10b (
.dout (err_bit7_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit7_pos_slice_10c (
.din0 (err_bit7_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit8_pos_slice_10a (
.dout (err_bit8_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit8_pos_slice_10b (
.dout (err_bit8_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit8_pos_slice_10c (
.din0 (err_bit8_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit9_pos_slice_10a (
.dout (err_bit9_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit9_pos_slice_10b (
.dout (err_bit9_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit9_pos_slice_10c (
.din0 (err_bit9_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit10_pos_slice_10a (
.dout (err_bit10_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit10_pos_slice_10b (
.dout (err_bit10_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit10_pos_slice_10c (
.din0 (err_bit10_pos_10a),
.din1 (err_bit10_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit11_pos_slice_10a (
.dout (err_bit11_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit11_pos_slice_10b (
.dout (err_bit11_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit11_pos_slice_10c (
.din0 (err_bit11_pos_10a),
.din1 (err_bit11_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit12_pos_slice_10a (
.dout (err_bit12_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit12_pos_slice_10b (
.dout (err_bit12_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit12_pos_slice_10c (
.din0 (err_bit12_pos_10a),
.din1 (err_bit12_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit13_pos_slice_10a (
.dout (err_bit13_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit13_pos_slice_10b (
.dout (err_bit13_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit13_pos_slice_10c (
.din0 (err_bit13_pos_10a),
.din1 (err_bit13_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit14_pos_slice_10a (
.dout (err_bit14_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit14_pos_slice_10b (
.dout (err_bit14_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit14_pos_slice_10c (
.din0 (err_bit14_pos_10a),
.din1 (err_bit14_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit15_pos_slice_10a (
.dout (err_bit15_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit15_pos_slice_10b (
.dout (err_bit15_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit15_pos_slice_10c (
.din0 (err_bit15_pos_10a),
.din1 (err_bit15_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit16_pos_slice_10a (
.dout (err_bit16_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit16_pos_slice_10b (
.dout (err_bit16_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit16_pos_slice_10c (
.din0 (err_bit16_pos_10a),
.din1 (err_bit16_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit17_pos_slice_10a (
.dout (err_bit17_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit17_pos_slice_10b (
.dout (err_bit17_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit17_pos_slice_10c (
.din0 (err_bit17_pos_10a),
.din1 (err_bit17_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit18_pos_slice_10a (
.dout (err_bit18_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit18_pos_slice_10b (
.dout (err_bit18_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit18_pos_slice_10c (
.din0 (err_bit18_pos_10a),
.din1 (err_bit18_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit19_pos_slice_10a (
.dout (err_bit19_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit19_pos_slice_10b (
.dout (err_bit19_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit19_pos_slice_10c (
.din0 (err_bit19_pos_10a),
.din1 (err_bit19_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit20_pos_slice_10a (
.dout (err_bit20_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit20_pos_slice_10b (
.dout (err_bit20_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit20_pos_slice_10c (
.din0 (err_bit20_pos_10a),
.din1 (err_bit20_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit21_pos_slice_10a (
.dout (err_bit21_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit21_pos_slice_10b (
.dout (err_bit21_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit21_pos_slice_10c (
.din0 (err_bit21_pos_10a),
.din1 (err_bit21_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit22_pos_slice_10a (
.dout (err_bit22_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit22_pos_slice_10b (
.dout (err_bit22_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit22_pos_slice_10c (
.din0 (err_bit22_pos_10a),
.din1 (err_bit22_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit23_pos_slice_10a (
.dout (err_bit23_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit23_pos_slice_10b (
.dout (err_bit23_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit23_pos_slice_10c (
.din0 (err_bit23_pos_10a),
.din1 (err_bit23_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit24_pos_slice_10a (
.dout (err_bit24_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit24_pos_slice_10b (
.dout (err_bit24_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit24_pos_slice_10c (
.din0 (err_bit24_pos_10a),
.din1 (err_bit24_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit25_pos_slice_10a (
.dout (err_bit25_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit25_pos_slice_10b (
.dout (err_bit25_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit25_pos_slice_10c (
.din0 (err_bit25_pos_10a),
.din1 (err_bit25_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit26_pos_slice_10a (
.dout (err_bit26_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit26_pos_slice_10b (
.dout (err_bit26_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit26_pos_slice_10c (
.din0 (err_bit26_pos_10a),
.din1 (err_bit26_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit27_pos_slice_10a (
.dout (err_bit27_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit27_pos_slice_10b (
.dout (err_bit27_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit27_pos_slice_10c (
.din0 (err_bit27_pos_10a),
.din1 (err_bit27_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit28_pos_slice_10a (
.dout (err_bit28_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit28_pos_slice_10b (
.dout (err_bit28_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit28_pos_slice_10c (
.din0 (err_bit28_pos_10a),
.din1 (err_bit28_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit29_pos_slice_10a (
.dout (err_bit29_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit29_pos_slice_10b (
.dout (err_bit29_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit29_pos_slice_10c (
.din0 (err_bit29_pos_10a),
.din1 (err_bit29_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit30_pos_slice_10a (
.dout (err_bit30_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit30_pos_slice_10b (
.dout (err_bit30_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit30_pos_slice_10c (
.din0 (err_bit30_pos_10a),
.din1 (err_bit30_pos_10b)
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit31_pos_slice_10a (
.dout (err_bit31_pos_10a),
l2t_ecc39a_dp_nand_macro__ports_3__width_1 err_bit31_pos_slice_10b (
.dout (err_bit31_pos_10b),
l2t_ecc39a_dp_nor_macro__ports_2__width_1 err_bit31_pos_slice_10c (
.din0 (err_bit31_pos_10a),
.din1 (err_bit31_pos_10b)
// correct the error bit, it can only correct one error bit.
// assign dout = din ^ err_bit_pos;
l2t_ecc39a_dp_xor_macro__dxor_16x__width_32 dout_slice
.din1 (err_bit_pos[31:0])
// xor macro for ports = 2,3
module l2t_ecc39a_dp_xor_macro__dxor_16x__ports_3__width_1 (
// xor macro for ports = 2,3
module l2t_ecc39a_dp_xor_macro__dxor_16x__ports_2__width_1 (
// parity macro (even parity)
module l2t_ecc39a_dp_prty_macro__dprty_8x__width_32 (
// parity macro (even parity)
module l2t_ecc39a_dp_prty_macro__dprty_8x__width_8 (
module l2t_ecc39a_dp_inv_macro__dinv_8x__width_2 (
// nand macro for ports = 2,3,4
module l2t_ecc39a_dp_nand_macro__dnand_32x__width_3 (
module l2t_ecc39a_dp_inv_macro__dinv_32x__width_1 (
// nand macro for ports = 2,3,4
module l2t_ecc39a_dp_nand_macro__ports_3__width_1 (
// nor macro for ports = 2,3
module l2t_ecc39a_dp_nor_macro__ports_2__width_1 (
// xor macro for ports = 2,3
module l2t_ecc39a_dp_xor_macro__dxor_16x__width_32 (