// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: l2t_evctag_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
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// ========== Copyright Header End ============================================
`define TAG_WIDTH_LESS1 27
`define MBD_WIDTH 106 // BS and SR 11/12/03 N2 Xbar Packet format change
// BS and SR 11/12/03 N2 Xbar Packet format change
`define MBD_ECC_HI_PLUS1 106
`define MBD_ECC_HI_PLUS5 110
// BS and SR 11/12/03 N2 Xbar Packet format change
// BS and SR 11/12/03 N2 Xbar Packet format change , maps to bits [128:104] of PCXS packet , ther than RSVD bit
`define ERR_TID_HI 59 // PRM needs to change to reflect this : TID will be bits [59:54] instead of [58:54]
// Phase 2 : SIU Inteface and format change
`define JBI_HDR_SZ 26 // BS and SR 11/12/03 N2 Xbar Packet format change
`define JBI_HDR_SZ_LESS1 25 // BS and SR 11/12/03 N2 Xbar Packet format change
// `define JBI_RSVD 16 NOt used
`define JBI_OPES_LO 27 // 0 = 30, P=29, E=28, S=27
// Phase 2 : SIU Inteface and format change
// BS and SR 11/12/03 N2 Xbar Packet format change :
// `define JBINST_RSVD 8 NOT used
`define JBINST_CTAG_HI 15
`define JBINST_RQ_WR64 18
`define JBINST_OPES_LO 19 // 0 = 22, P=21, E=20, S=19
`define JBINST_OPES_HI 22
`define JBINST_ENTRY_LO 23
`define JBINST_ENTRY_HI 24
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
// Change 4/7/2003: Added a pin, evctag_vuad_idx_c3 to the bottom.
////////////////////////////////////////////////////////////////////////
arbadr_ncu_l2t_pm_n_dist,
arbadr_2bnk_true_enbld_dist,
arbadr_4bnk_true_enbld_dist,
arbadr_mbcam_addr_px2_buff,
arbadr_arbdp_cam_addr_px2,
wbuf_wb_or_rdma_wr_req_en,
wire arbadr_ncu_l2t_pm_n;
wire arbadr_4bnk_true_enbld;
wire arbadr_2bnk_true_enbld;
wire ff_read_mb_tag_reg_scanin;
wire ff_read_mb_tag_reg_scanout;
wire ff_read_fb_tag_reg_scanin;
wire ff_read_fb_tag_reg_scanout;
wire arb_mux1_mbsel_px1_n;
wire [39:0] evctag_addr_px2_unbuff;
wire ff_mcu_read_addr_scanin;
wire ff_mcu_read_addr_scanout;
wire [39:5] mcu_read_addr_n;
wire ff_wb_rdma_write_addr_scanin;
wire ff_wb_rdma_write_addr_scanout;
wire [39:6] mcu_wr_addr_n;
wire [39:0] inst_addr_c1_fnl;
wire [41:9] arbadr_mbcam_addr_px2_reg;
wire ff_arbadr_mbcam_addr_px2_scanin;
wire ff_arbadr_mbcam_addr_px2_scanout;
wire ff_lkup_addr_c1_scanin;
wire ff_lkup_addr_c1_scanout;
wire ff_inst_addr_c2_scanin;
wire ff_inst_addr_c2_scanout;
wire [41:0] evctag_mb_write_addr_unbuff;
wire [7:0] l2t_mb2_wdata_r2;
wire ff_inst_addr_c3_scanin;
wire ff_inst_addr_c3_scanout;
wire misbuf_arb_mcurd_en_n;
wire ff_shifted_index_scanin;
wire ff_shifted_index_scanout;
wire [3:0] mbist_cam_sel_r1;
wire [3:0] mbist_cam_sel_r2;
wire [3:0] mbist_cam_sel_r3;
wire [3:0] mbist_cam_sel_r4;
wire misbuf_buf_rd_en_r1;
wire [3:0] mbist_cam_sel_r5;
wire ff_inst_addr_c4_scanin;
wire ff_inst_addr_c4_scanout;
wire [39:0] evctag_wb_write_addr_fnl;
wire [7:0] l2t_mb2_wdata_r3;
wire [41:0] mbist_cam_read_data;
wire [41:0] mbist_cmp_read_data;
wire cam_mb2_rw_fail_raw;
wire read_enable_piped_1;
wire read_enable_piped_r2_n;
wire read_enable_piped_r2;
wire ff_mbist_read_data_r1_scanin;
wire ff_mbist_read_data_r1_scanout;
wire [41:0] mbist_read_data;
wire [7:0] l2t_mb2_wdata_r5;
wire [41:0] mb_read_data_reg;
wire ff_mb_read_data_scanin;
wire ff_mb_read_data_scanout;
wire ff_l2t_mb2_wdata_scanin;
wire ff_l2t_mb2_wdata_scanout;
wire [7:0] l2t_mb2_wdata_r4;
wire ff_other_cam_match_scanin;
wire ff_other_cam_match_scanout;
wire read_enable_piped_r3_unused;
wire read_enable_piped_r1;
wire [7:0] l2t_mb2_wdata_r1;
output [39:0] evctag_addr_px2;
output [39:0] evctag_mb_read_data;
output [39:6] evctag_evict_addr ; // to the csr block
output [39:7] l2t_mcu_addr;
output [39:7] evctag_lkup_addr_c1; // address to lkup buffer tags.
output [41:0] evctag_mb_write_addr;
output [39:0] evctag_wb_write_addr;
output [8:0] evctag_vuad_idx_c3; // Bottom.
input arbadr_ncu_l2t_pm_n_dist; // BS 03/25/04 for partial bank/core modes support
input arbadr_2bnk_true_enbld_dist;// BS 03/25/04 for partial bank/core modes support
input arbadr_4bnk_true_enbld_dist; // BS 03/25/04 for partial bank/core modes support
input [39:0] wb_read_data ; // wr address from wb
input [39:0] rdma_read_data; // wr address from rdmawb
input [41:0] mb_read_data;
input [39:0] fb_read_data;
input [41:7] arbadr_mbcam_addr_px2;
output [41:7] arbadr_mbcam_addr_px2_buff;
//input [31:0] mb_cam_match;
//input [7:0] wb_cam_match_c2;
//input [7:0] fb_cam_match;
//input [7:0] rdmat_cam_match_c2;
input [39:0] arbadr_arbdp_cam_addr_px2;
input [`TAG_WIDTH-1:6] tagd_evict_tag_c4;
input wbuf_wr_addr_sel ; // sel wb_read_data
input wbuf_wb_or_rdma_wr_req_en ; // enable wr addr flop.
input misbuf_arb_l2rd_en;
input misbuf_arb_mcurd_en;
input filbuf_arb_l2rd_en;
input arb_mux1_mbsel_px1; // from arb
input arb_evict_c4;// from arb.
input [127:64] mbdata_din_unbuf;
output [127:64] mbdata_din;
input [39:0] fbtag_din_unbuff;
//input [39:6] rdmatag_wr_addr_s2;
//input [127:0] mb_data_read_data;
//output [41:0] mbist_cam_read_data;
input [3:0] mbist_cam_sel;
//input [1:0] mbdata_cmp_sel;
input [7:0] l2t_mb2_wdata;
//output cam_mb2_cam_fail;
assign stop = tcu_clk_stop;
assign pce_ov = tcu_pce_ov;
//assign scan_out = 1'b0;
wire [39:7] l2t_mcu_addr_muxout;
wire l2t_mcu_addr_5_muxout;
wire [23:0] evct_addr_39_16;
wire [39:0] mbf_addr_px2, fbf_addr_px2;
wire [39:6] evict_rd_data;
wire [39:5] mcu_read_addr;
wire [39:0] inst_addr_c1;
wire [39:0] inst_addr_c2, inst_addr_c3;
wire [39:0] inst_addr_c4;
wire [39:0] evict_addr_c4;
//////////////////////////////
// Arb mux between MB and FB
//////////////////////////////
//mux_macro mux_mbrd_mbwr_idx_c2 (width=16,ports=3,mux=aonpe,stack=16r,dmux=8x)
// .dout ({mbwr_idx_c2[17:9],mbrd_idx_c2[15:9]}),
// .din0({inst_addr_c2[17:9],mb_read_data[15:9]}), // original idx , all banks enabled
// .din1({inst_addr_c2[16:8],mb_read_data[16:10]}), // 1 bit shifted idx for 4 banks enabled
// .din2({inst_addr_c2[15:7],mb_read_data[17:11]}), //2 bit shifted idx for 2 banks enabled
// .sel0(arbadr_ncu_l2t_pm_n),
// .sel1(arbadr_4bnk_true_enbld),
// .sel2(arbadr_2bnk_true_enbld)
l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_42r__width_40 mux_mbrdwridx_evict_addr_c4
.dout ({mbwr_idx_c2[17:9],mbrd_idx_c2[15:9],evct_addr_39_16[23:0]}),
.din0 ({inst_addr_c2[17:9],mb_read_data[15:9],tagd_evict_tag_c4[`TAG_WIDTH-1:6],inst_addr_c4[17:16]}),
.din1 ({inst_addr_c2[16:8],mb_read_data[16:10],1'b0,tagd_evict_tag_c4[`TAG_WIDTH-1:6],inst_addr_c4[16]}),
.din2 ({inst_addr_c2[15:7],mb_read_data[17:11],2'b0,tagd_evict_tag_c4[`TAG_WIDTH-1:6]}),
.sel0(arbadr_ncu_l2t_pm_n),
.sel1(arbadr_4bnk_true_enbld),
.sel2(arbadr_2bnk_true_enbld)
//assign evctag_mb_read_data = {mb_read_data[41:18],mbrd_idx_c2[15:9],mb_read_data[8:0]};
l2t_evctag_dp_buff_macro__dbuff_16x__stack_42r__width_40 buff_evctag_mb_read_data
.dout (evctag_mb_read_data[39:0]),
.din ({mb_read_data[41:18],mbrd_idx_c2[15:9],mb_read_data[8:0]})
l2t_evctag_dp_msff_macro__stack_42r__width_40 ff_read_mb_tag_reg
.scan_in(ff_read_mb_tag_reg_scanin),
.scan_out(ff_read_mb_tag_reg_scanout),
.din (evctag_mb_read_data[39:0]),
.dout (mbf_addr_px2[39:0]),
.en (misbuf_arb_l2rd_en),
l2t_evctag_dp_msff_macro__stack_42r__width_40 ff_read_fb_tag_reg
.scan_in(ff_read_fb_tag_reg_scanin),
.scan_out(ff_read_fb_tag_reg_scanout),
.din (fb_read_data[39:0]),
.dout (fbf_addr_px2[39:0]),
.en (filbuf_arb_l2rd_en),
// -created 4 sets fo selects for the evctag_addr_px2 mux.
// -in the implementation, invert the data before muxing,
// use a 2x or 4x mux and drive the output of the mux
l2t_evctag_dp_inv_macro__width_1 inv_mux1_mbsel_px2_1 (
.dout (arb_mux1_mbsel_px1_n),
.din (arb_mux1_mbsel_px1 )
l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_42r__width_40 mux_mux1_addr_px2
.dout (evctag_addr_px2_unbuff[39:0]) ,
.din0 (mbf_addr_px2[39:0]),
.din1 (fbf_addr_px2[39:0] ),
.sel0 (mux1_mbsel_px2_1),
.sel1 (mux1_mbsel_px2_1_n)
l2t_evctag_dp_buff_macro__dbuff_16x__stack_42r__width_40 buff_evctag_addr_px2
.dout (evctag_addr_px2[39:0]) ,
.din (evctag_addr_px2_unbuff[39:0])
//////////////////////////////
//////////////////////////////
l2t_evctag_dp_msffi_macro__dmsffi_32x__stack_42r__width_35 ff_mcu_read_addr
.din(evctag_mb_read_data[39:5]),
.scan_in(ff_mcu_read_addr_scanin),
.scan_out(ff_mcu_read_addr_scanout),
.dout_l(mcu_read_addr_n[39:5]),
.en(misbuf_arb_mcurd_en),
//////////////////////////////
// MUX Between RDMA and WB addresses.
//////////////////////////////
l2t_evctag_dp_inv_macro__width_1 wbuf_wr_addr_sel_inv_slice
.dout (wbuf_wr_addr_sel_n),
l2t_evctag_dp_mux_macro__mux_aonpe__ports_2__stack_42r__width_34 rdmawb_addr_mux
.dout (evict_rd_data[39:6]),
.din0 (rdma_read_data[39:6]), // rdma evict addr
.din1 (wb_read_data[39:6]), // wb evict addr
.sel0 (wbuf_wr_addr_sel_n), // sel rdma evict addr
.sel1 (wbuf_wr_addr_sel) // sel wb evict addr.
l2t_evctag_dp_msffi_macro__dmsffi_32x__stack_42r__width_34 ff_wb_rdma_write_addr
.din (evict_rd_data[39:6]),
.scan_in(ff_wb_rdma_write_addr_scanin),
.scan_out(ff_wb_rdma_write_addr_scanout),
.dout_l (mcu_wr_addr_n[39:6]),
.en (wbuf_wb_or_rdma_wr_req_en),
// assign evctag_evict_addr = mcu_wr_addr[39:6] ;
//buff_macro buff_evctag_evict_addr (width=34,dbuff=32x,stack=42r)
l2t_evctag_dp_inv_macro__dinv_32x__stack_42r__width_34 buff_evctag_evict_addr
.dout (evctag_evict_addr[39:6]),
.din (mcu_wr_addr_n[39:6])
//// ctl flop. This flop is here for timing reasons.
//msff_macro ff_mcu_pick_d2 (width=1,stack=1r)
// .scan_in(ff_mcu_pick_d2_scanin),
// .scan_out(ff_mcu_pick_d2_scanout),
// .din (misbuf_arb_mcurd_en),
//////////////////////////////
//////////////////////////////
//inv_macro mcu_pick_d2_inv_slice (width=1)
// .dout (mcu_pick_d2_n),
l2t_evctag_dp_buff_macro__dbuff_32x__stack_42r__width_35 buff_arbadr_mbcam_addr_px2
.dout (arbadr_mbcam_addr_px2_buff[41:7]),
.din (arbadr_mbcam_addr_px2[41:7])
l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_42r__width_34 mcu_addr_mux
.dout ({l2t_mcu_addr_muxout[39:7],l2t_mcu_addr_5_muxout}),
.din0 ({mcu_read_addr_n[39:7],mcu_read_addr_n[5]}),
.din1 ({mcu_wr_addr_n[39:7],1'b1}),
l2t_evctag_dp_inv_macro__dinv_32x__stack_34r__width_34 inv1_l2t_mcu_addr
.dout ({l2t_mcu_addr[39:7],l2t_mcu_addr_5}),
.din ({l2t_mcu_addr_muxout[39:7],l2t_mcu_addr_5_muxout})
//////////////////////////////
//////////////////////////////
l2t_evctag_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_42r__width_40 mux_mbist_lookup_c1
.dout (inst_addr_c1[39:0]),
.din0 (inst_addr_c1_fnl[39:0]),
// .din1 ({arbadr_mbcam_addr_px2[41:9],7'b0}),
.din1 ({arbadr_mbcam_addr_px2_reg[41:9],7'b0}),
.sel0 (l2t_mb2_run_r1_n_1)
l2t_evctag_dp_msff_macro__stack_42r__width_33 ff_arbadr_mbcam_addr_px2
.scan_in(ff_arbadr_mbcam_addr_px2_scanin),
.scan_out(ff_arbadr_mbcam_addr_px2_scanout),
.din (arbadr_mbcam_addr_px2[41:9]),
.dout (arbadr_mbcam_addr_px2_reg[41:9]),
l2t_evctag_dp_msff_macro__stack_42r__width_40 ff_lkup_addr_c1
.scan_in(ff_lkup_addr_c1_scanin),
.scan_out(ff_lkup_addr_c1_scanout),
.din (arbadr_arbdp_cam_addr_px2[39:0]),
.dout (inst_addr_c1_fnl[39:0]),
assign evctag_lkup_addr_c1[39:7] = inst_addr_c1[39:7] ;
//buff_macro buff_evctag_lkup_addr_c1 (width=33,dbuff=32x,stack=42r)
// .dout (evctag_lkup_addr_c1[39:7]),
// .din (inst_addr_c1[39:7])
l2t_evctag_dp_msff_macro__dmsff_32x__stack_42r__width_40 ff_inst_addr_c2
.scan_in(ff_inst_addr_c2_scanin),
.scan_out(ff_inst_addr_c2_scanout),
.din (inst_addr_c1[39:0]),
.dout (inst_addr_c2[39:0]),
// assign evctag_mb_write_addr = {inst_addr_c2[39:16],mbwr_idx_c2[17:9],inst_addr_c2[8:0]};
l2t_evctag_dp_buff_macro__dbuff_16x__stack_42r__width_42 buff_evctag_mb_write_addr
.dout (evctag_mb_write_addr[41:0]),
// .din ({inst_addr_c2[39:16],mbwr_idx_c2[17:9],inst_addr_c2[8:0]})
.din (evctag_mb_write_addr_unbuff[41:0])
l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_42r__width_42 mux_mb_write_addr
.dout (evctag_mb_write_addr_unbuff[41:0]),
.din0 ({inst_addr_c2[39:16],mbwr_idx_c2[17:9],inst_addr_c2[8:0]}),
.din1 ({l2t_mb2_wdata_r2[1:0],{5{l2t_mb2_wdata_r2[7:0]}}}),
.sel0 (l2t_mb2_run_r1_n),
l2t_evctag_dp_msff_macro__stack_42r__width_40 ff_inst_addr_c3
.scan_in(ff_inst_addr_c3_scanin),
.scan_out(ff_inst_addr_c3_scanout),
.din (inst_addr_c2[39:0]),
.dout (inst_addr_c3[39:0]),
l2t_evctag_dp_inv_macro__width_1 inv_misbuf_arb_mcurd_en
.dout (misbuf_arb_mcurd_en_n),
.din (misbuf_arb_mcurd_en)
l2t_evctag_dp_msff_macro__dmsff_32x__stack_42r__width_40 ff_shifted_index
.scan_in(ff_shifted_index_scanin),
.scan_out(ff_shifted_index_scanout),
.din ({misbuf_buf_rd_en,mbist_cam_sel[3:0],mbist_cam_sel_r1[3:0],mbist_cam_sel_r2[3:0],mbist_cam_sel_r3[3:0],
mbist_cam_sel_r4[3:0],l2t_mb2_run,l2t_mb2_run_n, l2t_mb2_run_n,
misbuf_arb_mcurd_en_n,misbuf_arb_mcurd_en,arb_mux1_mbsel_px1,arb_mux1_mbsel_px1_n,
arbadr_ncu_l2t_pm_n_dist,arbadr_4bnk_true_enbld_dist,arbadr_2bnk_true_enbld_dist,mbwr_idx_c2[17:9]}),
.dout ({misbuf_buf_rd_en_r1,mbist_cam_sel_r1[3:0],mbist_cam_sel_r2[3:0],mbist_cam_sel_r3[3:0],mbist_cam_sel_r4[3:0],
mbist_cam_sel_r5[3:0],l2t_mb2_run_r1,l2t_mb2_run_r1_n,l2t_mb2_run_r1_n_1,
mcu_pick_d2_n,mcu_pick_d2,mux1_mbsel_px2_1,mux1_mbsel_px2_1_n,
arbadr_ncu_l2t_pm_n,arbadr_4bnk_true_enbld,arbadr_2bnk_true_enbld,evctag_vuad_idx_c3[8:0]}),
l2t_evctag_dp_msff_macro__stack_42r__width_40 ff_inst_addr_c4
.scan_in(ff_inst_addr_c4_scanin),
.scan_out(ff_inst_addr_c4_scanout),
.din (inst_addr_c3[39:0]),
.dout (inst_addr_c4[39:0]),
//assign evict_addr_c4[39:18] = tagd_evict_tag_c4[`TAG_WIDTH-1:6] ;
//assign evict_addr_c4[17:6] = inst_addr_c4[17:6] ;
//assign evict_addr_c4[5:0] = 6'b0 ;
// fix for bug 93448 : tag read from tag array on evict needs to be shifted around to
// original address before being sent to MCU
//mux_macro mux_evict_addr_c4 (width=24,ports=3,mux=aonpe,stack=24r,dmux=8x)
// .dout (evct_addr_39_16[23:0]),
// .din0({tagd_evict_tag_c4[`TAG_WIDTH-1:6],inst_addr_c4[17:16]}), // original idx , all banks enabled
// .din1({1'b0,tagd_evict_tag_c4[`TAG_WIDTH-1:6],inst_addr_c4[16]}), // 1 bit shifted idx for 4 banks enabled
// .din2({2'b0,tagd_evict_tag_c4[`TAG_WIDTH-1:6]}), //2 bit shifted idx for 2 banks enabled
// .sel0(arbadr_ncu_l2t_pm_n),
// .sel1(arbadr_4bnk_true_enbld),
// .sel2(arbadr_2bnk_true_enbld)
l2t_evctag_dp_buff_macro__dbuff_16x__stack_42r__width_40 buff_evict_addr_c4
.dout (evict_addr_c4[39:0]),
.din ({evct_addr_39_16[23:0],inst_addr_c4[15:6],6'b0})
l2t_evctag_dp_inv_macro__width_1 arb_evict_c4invert_slice
l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_42r__width_40 mux_wbtag
.dout (evctag_wb_write_addr[39:0]),
.din0 (evctag_wb_write_addr_fnl[39:0]),
.din1 ({5{l2t_mb2_wdata_r3[7:0]}}),
.sel0 (l2t_mb2_run_r1_n),
l2t_evctag_dp_mux_macro__mux_aonpe__ports_2__stack_42r__width_40 mux_wbb_wraddr_c3
.dout (evctag_wb_write_addr_fnl[39:0]),
.din0 (inst_addr_c4[39:0]),
.din1 (evict_addr_c4[39:0]),
////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////
l2t_evctag_dp_cmp_macro__dcmp_8x__width_32 cmp_cam_data_compare
.din0 (mbist_cam_read_data[31:0]),
.din1 (mbist_cmp_read_data[31:0])
l2t_evctag_dp_cmp_macro__dcmp_8x__width_16 cmp_cam_data_compare1
.din0 ({6'b0,mbist_cam_read_data[41:32]}),
.din1 ({6'b0,mbist_cmp_read_data[41:32]})
l2t_evctag_dp_and_macro__ports_2__width_1 and_cam_fail_out
.dout (cam_mb2_rw_fail_raw),
//msff_macro ff_mbist_cam_sel (width=8)
// .scan_in(ff_mbist_cam_sel_scanin),
// .scan_out(ff_mbist_cam_sel_scanout),
// .dout ({mbist_cam_sel_r1[3:0],mbist_cam_sel_r2[3:0]}),
// .din ({mbist_cam_sel[3:0],mbist_cam_sel_r1[3:0]}),
//assign read_enable_piped = (misbuf_buf_rd_en & mbist_cam_sel[0] ) |
// (filbuf_buf_rd_en & mbist_cam_sel[1] ) |
// (wb_read_en & mbist_cam_sel[2] ) |
// (rdmat_read_en & mbist_cam_sel[3] );
l2t_evctag_dp_and_macro__ports_2__width_4 and_mbreads
.dout ({rdmat_reads,wb_reads,fb_reads,mb_reads}),
.din0 (mbist_cam_sel_r2[3:0]),
.din1 ({rdmat_read_en,wb_read_en,filbuf_buf_rd_en,misbuf_buf_rd_en_r1})
l2t_evctag_dp_or_macro__ports_3__width_1 or_read_enable_piped
.dout (read_enable_piped_1),
l2t_evctag_dp_or_macro__ports_2__width_1 or_read_enable_piped1
.dout (read_enable_piped),
.din0 (read_enable_piped_1),
//assign read_enable_piped_r2_n = ~read_enable_piped_r2;
l2t_evctag_dp_inv_macro__width_1 inv_read_enable_piped_r2
.dout (read_enable_piped_r2_n),
.din (read_enable_piped_r2)
l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_1 mux_rw_failsignal
.din0 (cam_mb2_rw_fail_raw),
.sel0 (read_enable_piped_r2),
.sel1 (read_enable_piped_r2_n)
l2t_evctag_dp_msff_macro__stack_42r__width_42 ff_mbist_read_data_r1
.scan_in(ff_mbist_read_data_r1_scanin),
.scan_out(ff_mbist_read_data_r1_scanout),
.dout (mbist_cam_read_data[41:0]),
.din (mbist_read_data[41:0]),
l2t_evctag_dp_mux_macro__mux_aonpe__ports_4__stack_42r__width_42 mux_read_comp_all_cams
.dout (mbist_cmp_read_data[41:0]),
.din0 ({l2t_mb2_wdata_r5[1:0],{5{l2t_mb2_wdata_r5[7:0]}}}),
.din1 ({2'b0,{5{l2t_mb2_wdata_r5[7:0]}}}),
.din2 ({2'b0,{5{l2t_mb2_wdata_r5[7:0]}}}),
.din3 ({2'b0,{l2t_mb2_wdata_r5[1:0],{4{l2t_mb2_wdata_r5[7:0]}}},6'b0}),
.sel0 (mbist_cam_sel_r5[0]),
.sel1 (mbist_cam_sel_r5[1]),
.sel2 (mbist_cam_sel_r5[2]),
.sel3 (mbist_cam_sel_r5[3])
l2t_evctag_dp_mux_macro__mux_aonpe__ports_4__stack_42r__width_42 mux_read_all_cams
.dout (mbist_read_data[41:0]),
.din0 (mb_read_data_reg[41:0]),
.din1 ({2'b0,fb_read_data[39:0]}),
.din2 ({2'b0,wb_read_data[39:0]}),
.din3 ({2'b0,rdma_read_data[39:0]}),
.sel0 (mbist_cam_sel_r4[0]),
.sel1 (mbist_cam_sel_r4[1]),
.sel2 (mbist_cam_sel_r4[2]),
.sel3 (mbist_cam_sel_r4[3])
l2t_evctag_dp_msff_macro__stack_42r__width_42 ff_mb_read_data
.scan_in(ff_mb_read_data_scanin),
.scan_out(ff_mb_read_data_scanout),
.dout (mb_read_data_reg[41:0]),
.din (mb_read_data[41:0]),
//msff_macro ff_mb_cam_match (width=40,stack=42r)
// .scan_in(ff_mb_cam_match_scanin),
// .scan_out(ff_mb_cam_match_scanout),
// .dout ({mb_cam_match_reg[31:0],
// l2t_mb2_wdata_r3[7:0]}),
// .din ({mb_cam_match[31:0],
// l2t_mb2_wdata_r2[7:0]}),
l2t_evctag_dp_msff_macro__stack_42r__width_24 ff_l2t_mb2_wdata
.scan_in(ff_l2t_mb2_wdata_scanin),
.scan_out(ff_l2t_mb2_wdata_scanout),
.dout ({l2t_mb2_wdata_r3[7:0],l2t_mb2_wdata_r4[7:0],l2t_mb2_wdata_r5[7:0]}),
.din ({l2t_mb2_wdata_r2[7:0],l2t_mb2_wdata_r3[7:0],l2t_mb2_wdata_r4[7:0]}),
//buff_macro other_cam_match_minbuff (width=24,stack=46r,minbuff=1) (
// .din ({rdmat_cam_match_c2[7:0], fb_cam_match[7:0], wb_cam_match_c2[7:0]}),
// .dout({rdmat_cam_match_c2_buf[7:0],fb_cam_match_buf[7:0],wb_cam_match_c2_buf[7:0]}));
l2t_evctag_dp_msff_macro__stack_46r__width_19 ff_other_cam_match
.scan_in(ff_other_cam_match_scanin),
.scan_out(ff_other_cam_match_scanout),
.dout ({read_enable_piped_r3_unused,read_enable_piped_r2,read_enable_piped_r1,
l2t_mb2_wdata_r2[7:0],l2t_mb2_wdata_r1[7:0]}),
.din ({read_enable_piped_r2,read_enable_piped_r1,read_enable_piped,
l2t_mb2_wdata_r1[7:0],l2t_mb2_wdata[7:0]}),
//mux_macro mux_cam_all_cams (width=32,ports=4,mux=aonpe,stack=42r,dmux=8x)
// .dout (mbist_cam_out[31:0]),
// .din0 (mb_cam_match_reg[31:0]),
// .din1 ({24'b0,fb_cam_match_reg[7:0]}),
// .din2 ({24'b0,wb_cam_match_c2_reg[7:0]}),
// .din3 ({24'b0,rdmat_cam_match_c2_reg[7:0]}),
// .sel0 (mbist_cam_sel_r2[0]),
// .sel1 (mbist_cam_sel_r2[1]),
// .sel2 (mbist_cam_sel_r2[2]),
// .sel3 (mbist_cam_sel_r2[3])
//cmp_macro cmp_cam_data (width=32)
// .dout (cam_mb2_cam_fail),
// .din0 (mbist_cam_out[31:0]),
// .din1 ({4{l2t_mb2_wdata[7:0]}})
l2t_evctag_dp_inv_macro__dinv_32x__width_1 inv_l2t_mb2_run_r1 (
//mux_macro mux_mbdata0 (width=32,stack=42r,mux=pgpe,ports=2,dmux=32x)
// .dout (mbdata_din[31:0]),
// .din0 (mbdata_din_unbuf[31:0]),
// .din1 ({4{l2t_mb2_wdata_r2[7:0]}}),
// .sel0 (l2t_mb2_run_r1_n),
//mux_macro mux_mbdata1 (width=32,stack=42r,mux=pgpe,ports=2,dmux=32x)
// .dout (mbdata_din[63:32]),
// .din0 (mbdata_din_unbuf[63:32]),
// .din1 ({4{l2t_mb2_wdata_r2[7:0]}}),
// .sel0 (l2t_mb2_run_r1_n),
l2t_evctag_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_42r__width_32 mux_mbdata2
.dout (mbdata_din[95:64]),
.din0 (mbdata_din_unbuf[95:64]),
.din1 ({4{l2t_mb2_wdata_r2[7:0]}}),
l2t_evctag_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_42r__width_32 mux_mbdata3
.dout (mbdata_din[127:96]),
.din0 (mbdata_din_unbuf[127:96]),
.din1 ({4{l2t_mb2_wdata_r2[7:0]}}),
l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_42r__width_40 mux_fbtag
.din0 (fbtag_din_unbuff[39:0]),
.din1 ({5{l2t_mb2_wdata_r3[7:0]}}),
.sel0 (l2t_mb2_run_r1_n),
assign ff_read_mb_tag_reg_scanin = scan_in ;
assign ff_read_fb_tag_reg_scanin = ff_read_mb_tag_reg_scanout;
assign ff_mcu_read_addr_scanin = ff_read_fb_tag_reg_scanout;
assign ff_wb_rdma_write_addr_scanin = ff_mcu_read_addr_scanout ;
assign ff_arbadr_mbcam_addr_px2_scanin = ff_wb_rdma_write_addr_scanout;
assign ff_lkup_addr_c1_scanin = ff_arbadr_mbcam_addr_px2_scanout;
assign ff_inst_addr_c2_scanin = ff_lkup_addr_c1_scanout ;
assign ff_inst_addr_c3_scanin = ff_inst_addr_c2_scanout ;
assign ff_shifted_index_scanin = ff_inst_addr_c3_scanout ;
assign ff_inst_addr_c4_scanin = ff_shifted_index_scanout ;
assign ff_mbist_read_data_r1_scanin = ff_inst_addr_c4_scanout ;
assign ff_mb_read_data_scanin = ff_mbist_read_data_r1_scanout;
assign ff_l2t_mb2_wdata_scanin = ff_mb_read_data_scanout ;
assign ff_other_cam_match_scanin = ff_l2t_mb2_wdata_scanout ;
assign scan_out = ff_other_cam_match_scanout;
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_3__stack_42r__width_40 (
cl_dp1_muxbuff3_8x c0_0 (
module l2t_evctag_dp_buff_macro__dbuff_16x__stack_42r__width_40 (
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_msff_macro__stack_42r__width_40 (
.so({so[38:0],scan_out}),
module l2t_evctag_dp_inv_macro__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_42r__width_40 (
cl_dp1_muxbuff2_8x c0_0 (
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_msffi_macro__dmsffi_32x__stack_42r__width_35 (
.so({so[33:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_mux_macro__mux_aonpe__ports_2__stack_42r__width_34 (
cl_dp1_muxbuff2_8x c0_0 (
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_msffi_macro__dmsffi_32x__stack_42r__width_34 (
.so({so[32:0],scan_out}),
module l2t_evctag_dp_inv_macro__dinv_32x__stack_42r__width_34 (
module l2t_evctag_dp_buff_macro__dbuff_32x__stack_42r__width_35 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_42r__width_34 (
cl_dp1_muxbuff2_8x c0_0 (
module l2t_evctag_dp_inv_macro__dinv_32x__stack_34r__width_34 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_42r__width_40 (
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_msff_macro__stack_42r__width_33 (
.so({so[31:0],scan_out}),
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_msff_macro__dmsff_32x__stack_42r__width_40 (
.so({so[38:0],scan_out}),
module l2t_evctag_dp_buff_macro__dbuff_16x__stack_42r__width_42 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__stack_42r__width_42 (
cl_dp1_muxbuff2_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_mux_macro__mux_aonpe__ports_2__stack_42r__width_40 (
cl_dp1_muxbuff2_8x c0_0 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module l2t_evctag_dp_cmp_macro__dcmp_8x__width_32 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module l2t_evctag_dp_cmp_macro__dcmp_8x__width_16 (
// and macro for ports = 2,3,4
module l2t_evctag_dp_and_macro__ports_2__width_1 (
// and macro for ports = 2,3,4
module l2t_evctag_dp_and_macro__ports_2__width_4 (
// or macro for ports = 2,3
module l2t_evctag_dp_or_macro__ports_3__width_1 (
// or macro for ports = 2,3
module l2t_evctag_dp_or_macro__ports_2__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_mux_macro__dmux_8x__mux_aonpe__ports_2__width_1 (
cl_dp1_muxbuff2_8x c0_0 (
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_msff_macro__stack_42r__width_42 (
.so({so[40:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_mux_macro__mux_aonpe__ports_4__stack_42r__width_42 (
cl_dp1_muxbuff4_8x c0_0 (
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_msff_macro__stack_42r__width_24 (
.so({so[22:0],scan_out}),
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_msff_macro__stack_46r__width_19 (
.so({so[17:0],scan_out}),
module l2t_evctag_dp_inv_macro__dinv_32x__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_evctag_dp_mux_macro__dmux_32x__mux_pgpe__ports_2__stack_42r__width_32 (