// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: mcu_addrdp_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
drif_single_channel_mode,
wire l2b0_adr_queue_scanin;
wire l2b0_adr_queue_scanout;
wire [14:0] l2b0_ras_adr_queue;
wire [10:0] l2b0_cas_adr_queue;
wire [2:0] l2b0_rd_req_id_queue;
wire [14:0] l2b0_ras_wr1_adr_queue;
wire [10:0] l2b0_cas_wr1_adr_queue;
wire [14:0] l2b0_ras_wr2_adr_queue;
wire [10:0] l2b0_cas_wr2_adr_queue;
wire l2b1_adr_queue_scanin;
wire l2b1_adr_queue_scanout;
wire [14:0] l2b1_ras_adr_queue;
wire [10:0] l2b1_cas_adr_queue;
wire [2:0] l2b1_rd_req_id_queue;
wire [14:0] l2b1_ras_wr1_adr_queue;
wire [10:0] l2b1_cas_wr1_adr_queue;
wire [14:0] l2b1_ras_wr2_adr_queue;
wire [10:0] l2b1_cas_wr2_adr_queue;
input drif_single_channel_mode;
// Outputs in module: mcu_adrgen_dp
input [14:0] l2b0_rd_ras_adr;
input [10:0] l2b0_rd_cas_adr;
input l2b0_rd_rank_adr; // rank address
input [2:0] l2b0_rd_dimm_adr; // rank address
input [2:0] l2b0_rd_bank_adr; // bank address
input [2:0] l2b0_l2rd_req_id; // request id
input [14:0] l2b0_wr_ras_adr;
input [10:0] l2b0_wr_cas_adr;
input l2b0_wr_rank_adr; // rank address
input [2:0] l2b0_wr_dimm_adr; // rank address
input [2:0] l2b0_wr_bank_adr; // bank address
// Outputs in module: mcu_adrgen_dp
input [14:0] l2b1_rd_ras_adr;
input [10:0] l2b1_rd_cas_adr;
input l2b1_rd_rank_adr; // rank address
input [2:0] l2b1_rd_dimm_adr; // rank address
input [2:0] l2b1_rd_bank_adr; // bank address
input [2:0] l2b1_l2rd_req_id; // request id
input [14:0] l2b1_wr_ras_adr;
input [10:0] l2b1_wr_cas_adr;
input l2b1_wr_rank_adr; // rank address
input [2:0] l2b1_wr_dimm_adr; // rank address
input [2:0] l2b1_wr_bank_adr; // bank address
// Inputs in module: mcu_adrq_dp
input l2b0_rd_adr_queue7_en; // read address queue entry7 enable
input l2b0_rd_adr_queue6_en; // read address queue entry6 enable
input l2b0_rd_adr_queue5_en; // read address queue entry5 enable
input l2b0_rd_adr_queue4_en; // read address queue entry4 enable
input l2b0_rd_adr_queue3_en; // read address queue entry3 enable
input l2b0_rd_adr_queue2_en; // read address queue entry2 enable
input l2b0_rd_adr_queue1_en; // read address queue entry1 enable
input l2b0_rd_adr_queue0_en; // read address queue entry0 enable
input [7:0] l2b0_rd_adr_queue_sel; // read address queue select
input l2b0_wr_adr_queue7_en; // write address queue entry7 enable
input l2b0_wr_adr_queue6_en; // write address queue entry6 enable
input l2b0_wr_adr_queue5_en; // write address queue entry5 enable
input l2b0_wr_adr_queue4_en; // write address queue entry4 enable
input l2b0_wr_adr_queue3_en; // write address queue entry3 enable
input l2b0_wr_adr_queue2_en; // write address queue entry2 enable
input l2b0_wr_adr_queue1_en; // write address queue entry1 enable
input l2b0_wr_adr_queue0_en; // write address queue entry0 enable
input [1:0] l2b0_req_rdwr_addr_sel; // read or write address queue select
// Outputs in module: mcu_adrq_dp
output l2b0_rd_wr_adr7_eq;
output l2b0_rd_wr_adr6_eq;
output l2b0_rd_wr_adr5_eq;
output l2b0_rd_wr_adr4_eq;
output l2b0_rd_wr_adr3_eq;
output l2b0_rd_wr_adr2_eq;
output l2b0_rd_wr_adr1_eq;
output l2b0_rd_wr_adr0_eq;
// Inputs in module: mcu_adrq_dp
input l2b1_rd_adr_queue7_en; // read address queue entry7 enable
input l2b1_rd_adr_queue6_en; // read address queue entry6 enable
input l2b1_rd_adr_queue5_en; // read address queue entry5 enable
input l2b1_rd_adr_queue4_en; // read address queue entry4 enable
input l2b1_rd_adr_queue3_en; // read address queue entry3 enable
input l2b1_rd_adr_queue2_en; // read address queue entry2 enable
input l2b1_rd_adr_queue1_en; // read address queue entry1 enable
input l2b1_rd_adr_queue0_en; // read address queue entry0 enable
input [7:0] l2b1_rd_adr_queue_sel; // read address queue select
input l2b1_wr_adr_queue7_en; // write address queue entry7 enable
input l2b1_wr_adr_queue6_en; // write address queue entry6 enable
input l2b1_wr_adr_queue5_en; // write address queue entry5 enable
input l2b1_wr_adr_queue4_en; // write address queue entry4 enable
input l2b1_wr_adr_queue3_en; // write address queue entry3 enable
input l2b1_wr_adr_queue2_en; // write address queue entry2 enable
input l2b1_wr_adr_queue1_en; // write address queue entry1 enable
input l2b1_wr_adr_queue0_en; // write address queue entry0 enable
input [1:0] l2b1_req_rdwr_addr_sel; // read or write address queue select
// Outputs in module: mcu_adrq_dp
output l2b1_rd_wr_adr7_eq;
output l2b1_rd_wr_adr6_eq;
output l2b1_rd_wr_adr5_eq;
output l2b1_rd_wr_adr4_eq;
output l2b1_rd_wr_adr3_eq;
output l2b1_rd_wr_adr2_eq;
output l2b1_rd_wr_adr1_eq;
output l2b1_rd_wr_adr0_eq;
input [1:0] rascas_adr_sel; // [0]: L2b0 address queue sel, [1]: L2b1 address queue sel, [2]: scrub address select
input [1:0] rascas_wr1_adr_sel;
input [1:0] rascas_wr2_adr_sel;
input [7:0] wr_adr_queue_sel; // write address queue select
input [7:0] wr1_adr_queue_sel; // write address queue select
input [7:0] wr2_adr_queue_sel; // write address queue select
output [14:0] ras_adr_queue; // RAS address
output [10:0] cas_adr_queue; // CAS address
output [2:0] rd_req_id_queue; // read request ID
output [14:0] ras_wr1_adr_queue; // RAS address
output [10:0] cas_wr1_adr_queue; // CAS address
output [14:0] ras_wr2_adr_queue; // RAS address
output [10:0] cas_wr2_adr_queue; // CAS address
assign pce_ov = tcu_pce_ov;
assign drif_scm = drif_single_channel_mode;
// L2Bank0: mcu_adr_queue
mcu_adrq_dp l2b0_adr_queue (
.scan_in(l2b0_adr_queue_scanin),
.scan_out(l2b0_adr_queue_scanout),
.rd_rank_adr ( {l2b0_rd_rank_adr, l2b0_rd_dimm_adr[2:0]} ),
.rd_bank_adr ( l2b0_rd_bank_adr[2:0] ),
.rd_ras_adr ( l2b0_rd_ras_adr[14:0] ),
.rd_cas_adr ( l2b0_rd_cas_adr[10:0] ),
.l2rd_req_id ( l2b0_l2rd_req_id[2:0] ),
.wr_rank_adr ( {l2b0_wr_rank_adr, l2b0_wr_dimm_adr[2:0]} ),
.wr_bank_adr ( l2b0_wr_bank_adr[2:0] ),
.wr_ras_adr ( l2b0_wr_ras_adr[14:0] ),
.wr_cas_adr ( l2b0_wr_cas_adr[10:0] ),
.rd_adr_queue7_en ( l2b0_rd_adr_queue7_en ),
.rd_adr_queue6_en ( l2b0_rd_adr_queue6_en ),
.rd_adr_queue5_en ( l2b0_rd_adr_queue5_en ),
.rd_adr_queue4_en ( l2b0_rd_adr_queue4_en ),
.rd_adr_queue3_en ( l2b0_rd_adr_queue3_en ),
.rd_adr_queue2_en ( l2b0_rd_adr_queue2_en ),
.rd_adr_queue1_en ( l2b0_rd_adr_queue1_en ),
.rd_adr_queue0_en ( l2b0_rd_adr_queue0_en ),
.rd_adr_queue_sel ( l2b0_rd_adr_queue_sel[7:0] ),
.wr_adr_queue7_en ( l2b0_wr_adr_queue7_en ),
.wr_adr_queue6_en ( l2b0_wr_adr_queue6_en ),
.wr_adr_queue5_en ( l2b0_wr_adr_queue5_en ),
.wr_adr_queue4_en ( l2b0_wr_adr_queue4_en ),
.wr_adr_queue3_en ( l2b0_wr_adr_queue3_en ),
.wr_adr_queue2_en ( l2b0_wr_adr_queue2_en ),
.wr_adr_queue1_en ( l2b0_wr_adr_queue1_en ),
.wr_adr_queue0_en ( l2b0_wr_adr_queue0_en ),
.req_rdwr_addr_sel ( l2b0_req_rdwr_addr_sel[1:0] ),
.ras_adr_queue ( l2b0_ras_adr_queue[14:0] ),
.cas_adr_queue ( l2b0_cas_adr_queue[10:0] ),
.rd_req_id_queue ( l2b0_rd_req_id_queue[2:0] ),
.ras_wr1_adr_queue ( l2b0_ras_wr1_adr_queue[14:0] ),
.cas_wr1_adr_queue ( l2b0_cas_wr1_adr_queue[10:0] ),
.ras_wr2_adr_queue ( l2b0_ras_wr2_adr_queue[14:0] ),
.cas_wr2_adr_queue ( l2b0_cas_wr2_adr_queue[10:0] ),
.rd_wr_adr7_eq ( l2b0_rd_wr_adr7_eq ),
.rd_wr_adr6_eq ( l2b0_rd_wr_adr6_eq ),
.rd_wr_adr5_eq ( l2b0_rd_wr_adr5_eq ),
.rd_wr_adr4_eq ( l2b0_rd_wr_adr4_eq ),
.rd_wr_adr3_eq ( l2b0_rd_wr_adr3_eq ),
.rd_wr_adr2_eq ( l2b0_rd_wr_adr2_eq ),
.rd_wr_adr1_eq ( l2b0_rd_wr_adr1_eq ),
.rd_wr_adr0_eq ( l2b0_rd_wr_adr0_eq ),
.tcu_scan_en(tcu_scan_en),
.wr_adr_queue_sel(wr_adr_queue_sel[7:0]),
.wr1_adr_queue_sel(wr1_adr_queue_sel[7:0]),
.wr2_adr_queue_sel(wr2_adr_queue_sel[7:0])
// L2bank1: mcu_adr_queue
mcu_adrq_dp l2b1_adr_queue (
.scan_in(l2b1_adr_queue_scanin),
.scan_out(l2b1_adr_queue_scanout),
.rd_rank_adr ( {l2b1_rd_rank_adr, l2b1_rd_dimm_adr[2:0]} ),
.rd_bank_adr ( l2b1_rd_bank_adr[2:0] ),
.rd_ras_adr ( l2b1_rd_ras_adr[14:0] ),
.rd_cas_adr ( l2b1_rd_cas_adr[10:0] ),
.l2rd_req_id ( l2b1_l2rd_req_id[2:0] ),
.wr_rank_adr ( {l2b1_wr_rank_adr, l2b1_wr_dimm_adr[2:0]} ),
.wr_bank_adr ( l2b1_wr_bank_adr[2:0] ),
.wr_ras_adr ( l2b1_wr_ras_adr[14:0] ),
.wr_cas_adr ( l2b1_wr_cas_adr[10:0] ),
.rd_adr_queue7_en ( l2b1_rd_adr_queue7_en ),
.rd_adr_queue6_en ( l2b1_rd_adr_queue6_en ),
.rd_adr_queue5_en ( l2b1_rd_adr_queue5_en ),
.rd_adr_queue4_en ( l2b1_rd_adr_queue4_en ),
.rd_adr_queue3_en ( l2b1_rd_adr_queue3_en ),
.rd_adr_queue2_en ( l2b1_rd_adr_queue2_en ),
.rd_adr_queue1_en ( l2b1_rd_adr_queue1_en ),
.rd_adr_queue0_en ( l2b1_rd_adr_queue0_en ),
.rd_adr_queue_sel ( l2b1_rd_adr_queue_sel[7:0] ),
.wr_adr_queue7_en ( l2b1_wr_adr_queue7_en ),
.wr_adr_queue6_en ( l2b1_wr_adr_queue6_en ),
.wr_adr_queue5_en ( l2b1_wr_adr_queue5_en ),
.wr_adr_queue4_en ( l2b1_wr_adr_queue4_en ),
.wr_adr_queue3_en ( l2b1_wr_adr_queue3_en ),
.wr_adr_queue2_en ( l2b1_wr_adr_queue2_en ),
.wr_adr_queue1_en ( l2b1_wr_adr_queue1_en ),
.wr_adr_queue0_en ( l2b1_wr_adr_queue0_en ),
.req_rdwr_addr_sel ( l2b1_req_rdwr_addr_sel[1:0] ),
.ras_adr_queue ( l2b1_ras_adr_queue[14:0] ),
.cas_adr_queue ( l2b1_cas_adr_queue[10:0] ),
.rd_req_id_queue ( l2b1_rd_req_id_queue[2:0] ),
.ras_wr1_adr_queue ( l2b1_ras_wr1_adr_queue[14:0] ),
.cas_wr1_adr_queue ( l2b1_cas_wr1_adr_queue[10:0] ),
.ras_wr2_adr_queue ( l2b1_ras_wr2_adr_queue[14:0] ),
.cas_wr2_adr_queue ( l2b1_cas_wr2_adr_queue[10:0] ),
.rd_wr_adr7_eq ( l2b1_rd_wr_adr7_eq ),
.rd_wr_adr6_eq ( l2b1_rd_wr_adr6_eq ),
.rd_wr_adr5_eq ( l2b1_rd_wr_adr5_eq ),
.rd_wr_adr4_eq ( l2b1_rd_wr_adr4_eq ),
.rd_wr_adr3_eq ( l2b1_rd_wr_adr3_eq ),
.rd_wr_adr2_eq ( l2b1_rd_wr_adr2_eq ),
.rd_wr_adr1_eq ( l2b1_rd_wr_adr1_eq ),
.rd_wr_adr0_eq ( l2b1_rd_wr_adr0_eq ),
.tcu_scan_en(tcu_scan_en),
.wr_adr_queue_sel(wr_adr_queue_sel[7:0]),
.wr1_adr_queue_sel(wr1_adr_queue_sel[7:0]),
.wr2_adr_queue_sel(wr2_adr_queue_sel[7:0])
mcu_addrdp_dp_mux_macro__mux_aonpe__ports_2__stack_38r__width_29 u_l2b0b1_addr_id (
.din0 ( { l2b0_rd_req_id_queue[2:0], l2b0_ras_adr_queue[14:0], l2b0_cas_adr_queue[10:0] } ),
.din1 ( { l2b1_rd_req_id_queue[2:0], l2b1_ras_adr_queue[14:0], l2b1_cas_adr_queue[10:0] } ),
.sel0 ( rascas_adr_sel[0] ),
.sel1 ( rascas_adr_sel[1] ),
.dout ( { rd_req_id_queue[2:0], ras_adr_queue[14:0], cas_adr_queue[10:0] } ));
mcu_addrdp_dp_mux_macro__mux_aonpe__ports_2__stack_38r__width_26 u_l2b0b1_wr1_addr (
.din0 ( { l2b0_ras_wr1_adr_queue[14:0], l2b0_cas_wr1_adr_queue[10:0] } ),
.din1 ( { l2b1_ras_wr1_adr_queue[14:0], l2b1_cas_wr1_adr_queue[10:0] } ),
.sel0 ( rascas_wr1_adr_sel[0] ),
.sel1 ( rascas_wr1_adr_sel[1] ),
.dout ( { ras_wr1_adr_queue[14:0], cas_wr1_adr_queue[10:0] } ));
mcu_addrdp_dp_mux_macro__mux_aonpe__ports_2__stack_38r__width_26 u_l2b0b1_wr2_addr (
.din0 ( { l2b0_ras_wr2_adr_queue[14:0], l2b0_cas_wr2_adr_queue[10:0] } ),
.din1 ( { l2b1_ras_wr2_adr_queue[14:0], l2b1_cas_wr2_adr_queue[10:0] } ),
.sel0 ( rascas_wr2_adr_sel[0] ),
.sel1 ( rascas_wr2_adr_sel[1] ),
.dout ( { ras_wr2_adr_queue[14:0], cas_wr2_adr_queue[10:0] } ));
assign l2b0_adr_queue_scanin = scan_in ;
assign l2b1_adr_queue_scanin = l2b0_adr_queue_scanout ;
assign scan_out = l2b1_adr_queue_scanout ;
// any PARAMS parms go into naming of macro
module mcu_addrdp_dp_msff_macro__stack_38r__width_36 (
.so({so[34:0],scan_out}),
// any PARAMS parms go into naming of macro
module mcu_addrdp_dp_msff_macro__stack_38r__width_34 (
.so({so[32:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mcu_addrdp_dp_mux_macro__mux_aonpe__ports_8__stack_38r__width_36 (
cl_dp1_muxbuff8_8x c0_0 (
module mcu_addrdp_dp_inv_macro (
// and macro for ports = 2,3,4
module mcu_addrdp_dp_and_macro (
// any PARAMS parms go into naming of macro
module mcu_addrdp_dp_msff_macro__stack_38r__width_33 (
.so({so[31:0],scan_out}),
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module mcu_addrdp_dp_cmp_macro__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mcu_addrdp_dp_mux_macro__mux_aonpe__ports_8__stack_38r__width_26 (
cl_dp1_muxbuff8_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mcu_addrdp_dp_mux_macro__mux_aonpe__ports_2__stack_38r__width_26 (
cl_dp1_muxbuff2_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mcu_addrdp_dp_mux_macro__mux_aonpe__ports_2__stack_38r__width_29 (
cl_dp1_muxbuff2_8x c0_0 (