// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: mcu_frdbuf_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// This program is free software; you can redistribute it and/or modify
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// ========== Copyright Header End ============================================
wire ff_clk_stop_sync_scanin;
wire ff_clk_stop_sync_scanout;
wire [3:0] frdbuf_cnt_next;
wire frdbuf_cnt_cout_unused;
wire fsr_stsrx_losdtct_sync_l;
wire frdbuf_enable_sync_count;
wire [3:0] frdbuf_cnt_in;
wire frdbuf_frame_lock_in;
wire [1:0] frdbuf_wptr_in;
wire fsr_stsrx_losdtct_d1;
wire fsr_stsrx_losdtct_sync;
wire frdbuf_enable_sync_count_in;
wire frdbuf_frame_lock_l;
wire [1:0] frdbuf_wptr_l;
wire [11:0] frdbuf_buffer0;
wire [11:0] frdbuf_buffer1;
wire [11:0] frdbuf_buffer2;
wire [11:0] frdbuf_buffer3;
wire frdbuf_elect_idle_d1;
wire ff_data_sync_scanin;
wire ff_data_sync_scanout;
output [11:0] frdbuf_data;
output frdbuf_elect_idle_sync;
output frdbuf_frame_lock;
output frdbuf_testfail_sync;
input fsr_stsrx_testfail;
input fbdic_enable_sync_count;
input tcu_mcu_fbd_clk_stop;
assign pce_ov = tcu_pce_ov;
mcu_frdbuf_dp_and_macro m_fbd_siclk (
mcu_frdbuf_dp_and_macro m_fbd_soclk (
mcu_frdbuf_dp_and_macro m_fbd_se (
assign ff_clk_stop_sync_scanin = 1'b0;
mcu_frdbuf_dp_msff_macro__stack_11r__width_4 ff_clk_stop_sync (
.scan_in(ff_clk_stop_sync_scanin),
.scan_out(ff_clk_stop_sync_scanout),
.din({tcu_mcu_fbd_clk_stop, clk_stop_d1, tcu_pce_ov, tcu_pce_ov_d1}),
.dout({clk_stop_d1, rxbclk_stop, tcu_pce_ov_d1, fbd_pce_ov}),
// want to turn off clk_stop in atpg_mode
mcu_frdbuf_dp_inv_macro m_inv_rxbclk_stop (
mcu_frdbuf_dp_nor_macro m_rxbclk_stop_atpg (
.dout(rxbclk_stop_atpg));
////////////////////////////
////////////////////////////
cl_dp1_l1hdr_8x alat_hdr (
cl_dp1_alatch_4x alat11 (
cl_dp1_alatch_4x alat10 (
mcu_frdbuf_dp_buff_macro__minbuff_1__stack_12r__width_12 m_alat_buf (
.dout(latout_buf[11:0]));
// Count 4 frame sync signals from SERDES before determining frame lock
// Reset on electrical idle
mcu_frdbuf_dp_increment_macro__width_4 m_frdbuf_cnt_inc (
.din ( frdbuf_cnt[3:0] ),
.cin ( fsr_stsrx_sync_lat ),
.dout ( frdbuf_cnt_next[3:0] ),
.cout ( frdbuf_cnt_cout_unused ) );
mcu_frdbuf_dp_and_macro__ports_3__width_4 m_frdbuf_cnt_clr (
.din0(frdbuf_cnt_next[3:0]),
.din1({4{fsr_stsrx_losdtct_sync_l}}),
.din2({4{frdbuf_enable_sync_count}}),
.dout(frdbuf_cnt_in[3:0]));
cl_dp1_l1hdr_8x ff_cnt_hdr (
.siclk_out(fbd_siclk_out),
.soclk_out(fbd_soclk_out),
.stop(rxbclk_stop_atpg));
cl_dp1_alatch_4x ff_cnt_d11 (
cl_dp1_msff_4x ff_cnt_d10 (
.d(frdbuf_frame_lock_in),
cl_dp1_msff_4x ff_cnt_d9 (
cl_dp1_msff_4x ff_cnt_d8 (
cl_dp1_msff_4x ff_cnt_d7 (
cl_dp1_msff_4x ff_cnt_d6 (
cl_dp1_msff_4x ff_cnt_d5 (
cl_dp1_msff_4x ff_cnt_d4 (
cl_dp1_msff_4x ff_cnt_d3 (
.q(fsr_stsrx_losdtct_d1));
cl_dp1_msff_4x ff_cnt_d2 (
.d(fsr_stsrx_losdtct_d1),
.q(fsr_stsrx_losdtct_sync));
cl_dp1_msff_4x ff_cnt_d1 (
.d(fbdic_enable_sync_count),
.q(frdbuf_enable_sync_count_in));
cl_dp1_msff_4x ff_cnt_d0 (
.d(frdbuf_enable_sync_count_in),
.q(frdbuf_enable_sync_count));
//assign frdbuf_frame_lock_in = ~fsr_fbd_elect_idle & (frdbuf_cnt[2] | frdbuf_frame_lock);
mcu_frdbuf_dp_or_macro__ports_2__width_1 m_or_0_0 (
.din1 ( frdbuf_frame_lock ),
mcu_frdbuf_dp_inv_macro__width_1 m_fsr_fbd_elect_idle_not (
.din ( fsr_stsrx_losdtct_sync ),
.dout ( fsr_stsrx_losdtct_sync_l ) );
mcu_frdbuf_dp_and_macro__ports_2__width_1 m_frdbuf_frame_lock_in (
.din0 ( fsr_stsrx_losdtct_sync_l ),
.dout ( frdbuf_frame_lock_in ) );
mcu_frdbuf_dp_inv_macro__width_1 m_frdbuf_frame_lock_inv (
.din ( frdbuf_frame_lock ),
.dout ( frdbuf_frame_lock_l ) );
// write pointer for asynchronous buffer, enabled by frame lock in SERDES clock domain
//assign frdbuf_wptr_in[1:0] = {2{frdbuf_frame_lock}} & {frdbuf_wptr[0],~frdbuf_wptr[1]};
mcu_frdbuf_dp_inv_macro__width_2 m_frdbuf_wptr_inv (
.din ( frdbuf_wptr[1:0] ),
.dout ( frdbuf_wptr_l[1:0] ) );
mcu_frdbuf_dp_and_macro__width_2 m_frdbuf_wptr_in (
.din0({frdbuf_wptr[0],frdbuf_wptr_l[1]}),
.din1({2{frdbuf_frame_lock}}),
.dout(frdbuf_wptr_in[1:0]));
// Four deep buffer for asynchronous clock domain crossing
//assign frdbuf_buffer0_en = frdbuf_frame_lock & ~frdbuf_wptr[1] & ~frdbuf_wptr[0];
mcu_frdbuf_dp_nor_macro__ports_3__width_1 m_frdbuf_buffer0_en (
.din0 ( frdbuf_wptr[0] ),
.din1 ( frdbuf_wptr[1] ),
.din2 ( frdbuf_frame_lock_l ),
.dout ( frdbuf_buffer0_en ) );
mcu_frdbuf_dp_msff_macro__stack_12r__width_12 ff_buffer0 (
.scan_in(ff_buffer0_scanin),
.scan_out(ff_buffer0_scanout),
.dout(frdbuf_buffer0[11:0]),
//assign frdbuf_buffer1_en = frdbuf_frame_lock & ~frdbuf_wptr[1] & frdbuf_wptr[0];
mcu_frdbuf_dp_nor_macro__ports_3__width_1 m_frdbuf_buffer1_en (
.din0 ( frdbuf_wptr[1] ),
.din1 ( frdbuf_wptr_l[0] ),
.din2 ( frdbuf_frame_lock_l ),
.dout ( frdbuf_buffer1_en ) );
mcu_frdbuf_dp_msff_macro__stack_12r__width_12 ff_buffer1 (
.scan_in(ff_buffer1_scanin),
.scan_out(ff_buffer1_scanout),
.dout(frdbuf_buffer1[11:0]),
//assign frdbuf_buffer2_en = frdbuf_frame_lock & frdbuf_wptr[1] & ~frdbuf_wptr[0];
mcu_frdbuf_dp_nor_macro__ports_3__width_1 m_frdbuf_buffer2_en (
.din0 ( frdbuf_wptr[0] ),
.din1 ( frdbuf_wptr_l[1] ),
.din2 ( frdbuf_frame_lock_l ),
.dout ( frdbuf_buffer2_en ) );
mcu_frdbuf_dp_msff_macro__stack_12r__width_12 ff_buffer2 (
.scan_in(ff_buffer2_scanin),
.scan_out(ff_buffer2_scanout),
.dout(frdbuf_buffer2[11:0]),
//assign frdbuf_buffer3_en = frdbuf_frame_lock & frdbuf_wptr[1] & frdbuf_wptr[0];
mcu_frdbuf_dp_nor_macro__ports_3__width_1 m_frdbuf_buffer3_en (
.din0 ( frdbuf_wptr_l[0] ),
.din1 ( frdbuf_wptr_l[1] ),
.din2 ( frdbuf_frame_lock_l ),
.dout ( frdbuf_buffer3_en ) );
mcu_frdbuf_dp_msff_macro__stack_12r__width_12 ff_buffer3 (
.scan_in(ff_buffer3_scanin),
.scan_out(ff_buffer3_scanout),
.dout(frdbuf_buffer3[11:0]),
////////////////////////////
////////////////////////////
// Synchronize electrical idle and frame lock signals for MCU
mcu_frdbuf_dp_msff_macro__stack_12r__width_4 ff_sync (
.scan_in(ff_sync_scanin),
.scan_out(ff_sync_scanout),
.din({fsr_stsrx_testfail,frdbuf_testfail_d1,fsr_stsrx_losdtct,frdbuf_elect_idle_d1}),
.dout({frdbuf_testfail_d1,frdbuf_testfail_sync,frdbuf_elect_idle_d1,frdbuf_elect_idle_sync}),
mcu_frdbuf_dp_inv_macro__width_2 m_frdbuf_rptr_inv (
.din ( fdout_rptr[1:0] ),
.dout ( fdout_rptr_l[1:0] ) );
// Selection of async buffer output
mcu_frdbuf_dp_nor_macro__ports_2__width_1 m_sl0 (
.din1 ( fdout_rptr[1] ) );
mcu_frdbuf_dp_nor_macro__ports_2__width_1 m_sl1 (
.din0 ( fdout_rptr_l[0] ),
.din1 ( fdout_rptr[1] ) );
mcu_frdbuf_dp_nor_macro__ports_2__width_1 m_sl2 (
.din1 ( fdout_rptr_l[1] ) );
mcu_frdbuf_dp_nor_macro__ports_2__width_1 m_sl3 (
.din0 ( fdout_rptr_l[0] ),
.din1 ( fdout_rptr_l[1] ) );
mcu_frdbuf_dp_msff_macro__mux_aonpe__ports_4__stack_12r__width_12 ff_data_sync (
.scan_in(ff_data_sync_scanin),
.scan_out(ff_data_sync_scanout),
.din0 ( frdbuf_buffer0[11:0] ),
.din1 ( frdbuf_buffer1[11:0] ),
.din2 ( frdbuf_buffer2[11:0] ),
.din3 ( frdbuf_buffer3[11:0] ),
.dout ( frdbuf_data[11:0] ),
mcu_frdbuf_dp_inv_macro m_inv_testmode (
.dout(tcu_mcu_testmode_l));
mcu_frdbuf_dp_mux_macro__buffsel_none__mux_aonpe m_scan_mux (
.din0(ff_buffer3_scanout),
.sel1(tcu_mcu_testmode_l),
.dout(m_scan_mux_scanout));
assign alat0_si = scan_in ;
assign ff_cnt_scanin = alat11_so ;
assign ff_buffer0_scanin = ff_cnt_scanout ;
assign ff_buffer1_scanin = ff_buffer0_scanout ;
assign ff_buffer2_scanin = ff_buffer1_scanout ;
assign ff_buffer3_scanin = ff_buffer2_scanout ;
assign ff_sync_scanin = m_scan_mux_scanout ;
assign ff_data_sync_scanin = ff_sync_scanout ;
assign scan_out = ff_data_sync_scanout ;
// and macro for ports = 2,3,4
module mcu_frdbuf_dp_and_macro (
// any PARAMS parms go into naming of macro
module mcu_frdbuf_dp_msff_macro__stack_11r__width_4 (
module mcu_frdbuf_dp_inv_macro (
// nor macro for ports = 2,3
module mcu_frdbuf_dp_nor_macro (
module mcu_frdbuf_dp_buff_macro__minbuff_1__stack_12r__width_12 (
module mcu_frdbuf_dp_increment_macro__width_4 (
// and macro for ports = 2,3,4
module mcu_frdbuf_dp_and_macro__ports_3__width_4 (
// or macro for ports = 2,3
module mcu_frdbuf_dp_or_macro__ports_2__width_1 (
module mcu_frdbuf_dp_inv_macro__width_1 (
// and macro for ports = 2,3,4
module mcu_frdbuf_dp_and_macro__ports_2__width_1 (
module mcu_frdbuf_dp_inv_macro__width_2 (
// and macro for ports = 2,3,4
module mcu_frdbuf_dp_and_macro__width_2 (
// nor macro for ports = 2,3
module mcu_frdbuf_dp_nor_macro__ports_3__width_1 (
// any PARAMS parms go into naming of macro
module mcu_frdbuf_dp_msff_macro__stack_12r__width_12 (
.so({so[10:0],scan_out}),
// any PARAMS parms go into naming of macro
module mcu_frdbuf_dp_msff_macro__stack_12r__width_4 (
// nor macro for ports = 2,3
module mcu_frdbuf_dp_nor_macro__ports_2__width_1 (
// any PARAMS parms go into naming of macro
module mcu_frdbuf_dp_msff_macro__mux_aonpe__ports_4__stack_12r__width_12 (
cl_dp1_muxbuff4_8x c1_0 (
.so({so[10:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module mcu_frdbuf_dp_mux_macro__buffsel_none__mux_aonpe (