// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: ncu_c2ibuf32_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
module ncu_c2ibuf32_ctl (
wire buf1_older_ff_scanin;
wire buf1_older_ff_scanout;
wire buf0_vld_ff_scanout;
wire buf1_vld_ff_scanout;
wire buf0_obj_p_ff_scanin;
wire buf0_obj_p_ff_scanout;
wire buf0_obj_h_ff_scanin;
wire buf0_obj_h_ff_scanout;
wire buf1_obj_p_ff_scanin;
wire buf1_obj_p_ff_scanout;
wire buf1_obj_h_ff_scanin;
wire buf1_obj_h_ff_scanout;
wire [127:0] outdata_buf_in;
wire [127:0] outdata_buf;
wire stall_d1_ff_scanout;
wire [3:0] outdata_vec_next;
wire outdata_vec_ff_scanin;
wire outdata_vec_ff_scanout;
wire [127:0] outdata_buf_next;
wire outdata_buf_ff_scanin;
wire outdata_buf_ff_scanout;
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// slow control interface
// slow datapath interface
input [127:0] c2i_packet;
output [31:0] iob_ucb_data;
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
assign dbl_buf_wr = c2i_packet_vld & ucb_sel & ~dbl_buf_full;
assign ucb_buf_acpt = dbl_buf_wr;
assign dbl_buf_rd = dbl_buf_vld & ~outdata_buf_busy;
assign outdata_buf_wr = dbl_buf_rd;
//assign outdata_vec_in = {128/UCB_BUS_WIDTH{1'b1}};
/******************************************************************
//dbl_buf #(128) dbl_buf (
// .din(c2i_packet[127:0]),
// .dout(outdata_buf_in[127:0]),
******************************************************************/
assign wr_buf0 = dbl_buf_wr & (buf1_vld | (~buf0_vld & ~buf1_older));
assign wr_buf1 = dbl_buf_wr & (buf0_vld | (~buf1_vld & buf1_older));
// read from the older entry
assign rd_buf0 = dbl_buf_rd & ~buf1_older;
assign rd_buf1 = dbl_buf_rd & buf1_older;
// flip older pointer when an entry is read
assign rd_buf = dbl_buf_rd & (buf0_vld | buf1_vld);
assign buf1_older_n = ~buf1_older;
ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_1 buf1_older_ff
.scan_in(buf1_older_ff_scanin),
.scan_out(buf1_older_ff_scanout),
// set valid bit for writes and reset for reads
assign en_vld0 = wr_buf0 | rd_buf0;
assign en_vld1 = wr_buf1 | rd_buf1;
ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_1 buf0_vld_ff
.scan_in(buf0_vld_ff_scanin),
.scan_out(buf0_vld_ff_scanout),
ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_1 buf1_vld_ff
.scan_in(buf1_vld_ff_scanin),
.scan_out(buf1_vld_ff_scanout),
ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_64 buf0_obj_p_ff
.scan_in(buf0_obj_p_ff_scanin),
.scan_out(buf0_obj_p_ff_scanout),
.dout (buf0_obj_p[63:0]),
.din (c2i_packet[127:64]),
ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_55 buf0_obj_h_ff
.scan_in(buf0_obj_h_ff_scanin),
.scan_out(buf0_obj_h_ff_scanout),
.dout (buf0_obj_h[54:0]),
ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_64 buf1_obj_p_ff
.scan_in(buf1_obj_p_ff_scanin),
.scan_out(buf1_obj_p_ff_scanout),
.dout (buf1_obj_p[63:0]),
.din (c2i_packet[127:64]),
ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_55 buf1_obj_h_ff
.scan_in(buf1_obj_h_ff_scanin),
.scan_out(buf1_obj_h_ff_scanout),
.dout (buf1_obj_h[54:0]),
// mux out the older entry
//assign outdata_buf_in[127:0] = (buf1_older) ? buf1_obj[127:0] : buf0_obj[127:0] ;
assign outdata_buf_in[127:0] = (buf1_older) ? {buf1_obj_p[63:0],9'b0,buf1_obj_h[54:0]} :
{buf0_obj_p[63:0],9'b0,buf0_obj_h[54:0]} ;
assign dbl_buf_vld = buf0_vld | buf1_vld;
assign dbl_buf_full = buf0_vld & buf1_vld;
/*******************************************************************
//ucb_bus_out #(UCB_BUS_WIDTH) ucb_bus_out (
// .outdata_buf_wr(outdata_buf_wr),
// .outdata_buf_in(outdata_buf_in[127:0]),
// .outdata_vec_in(outdata_vec_in[128/UCB_BUS_WIDTH-1:0]),
// .outdata_buf_busy(outdata_buf_busy),
// .data(iob_ucb_data[UCB_BUS_WIDTH-1:0]),
// .stall(ucb_iob_stall));
*******************************************************************/
assign iob_ucb_vld = outdata_vec[0] & tcu_dbr_gateoff;
assign iob_ucb_data[31:0] = outdata_buf[31:0];
ncu_c2ibuf32_ctl_msff_ctl_macro__width_1 rdy0_ff
.scan_in(rdy0_ff_scanin),
.scan_out(rdy0_ff_scanout),
ncu_c2ibuf32_ctl_msff_ctl_macro__width_1 rdy1_ff
.scan_in(rdy1_ff_scanin),
.scan_out(rdy1_ff_scanout),
ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_1 stall_d1_ff
.scan_in(stall_d1_ff_scanin),
.scan_out(stall_d1_ff_scanout),
/************************************************************
************************************************************/
// accept new data only if there is none being processed
assign load_outdata = outdata_buf_wr & ~outdata_buf_busy;
assign outdata_buf_busy = outdata_vec[0] | stall_d1;
assign shift_outdata = outdata_vec[0] & ~stall_d1;
assign outdata_vec_next[3:0] =
//load_outdata ? outdata_vec_in[3:0] :
//shift_outdata ? outdata_vec[128/UCB_BUS_WIDTH-1:0] >> 1 :
shift_outdata ? {1'b0,outdata_vec[3:1]} : outdata_vec[3:0] ;
ncu_c2ibuf32_ctl_msff_ctl_macro__width_4 outdata_vec_ff
.scan_in(outdata_vec_ff_scanin),
.scan_out(outdata_vec_ff_scanout),
.dout (outdata_vec[3:0]),
.din (outdata_vec_next[3:0]),
assign outdata_buf_next[127:0] = load_outdata ? outdata_buf_in[127:0] :
shift_outdata ? (outdata_buf[127:0] >> 32) :
ncu_c2ibuf32_ctl_msff_ctl_macro__width_128 outdata_buf_ff
.scan_in(outdata_buf_ff_scanin),
.scan_out(outdata_buf_ff_scanout),
.dout (outdata_buf[127:0]),
.din (outdata_buf_next[127:0]),
/**** adding clock header ****/
ncu_c2ibuf32_ctl_l1clkhdr_ctl_macro clkgen (
/*** building tcu port ***/
assign pce_ov = tcu_pce_ov;
assign stop = tcu_clk_stop;
assign buf1_older_ff_scanin = scan_in ;
assign buf0_vld_ff_scanin = buf1_older_ff_scanout ;
assign buf1_vld_ff_scanin = buf0_vld_ff_scanout ;
assign buf0_obj_p_ff_scanin = buf1_vld_ff_scanout ;
assign buf0_obj_h_ff_scanin = buf0_obj_p_ff_scanout ;
assign buf1_obj_p_ff_scanin = buf0_obj_h_ff_scanout ;
assign buf1_obj_h_ff_scanin = buf1_obj_p_ff_scanout ;
assign rdy0_ff_scanin = buf1_obj_h_ff_scanout ;
assign rdy1_ff_scanin = rdy0_ff_scanout ;
assign stall_d1_ff_scanin = rdy1_ff_scanout ;
assign outdata_vec_ff_scanin = stall_d1_ff_scanout ;
assign outdata_buf_ff_scanin = outdata_vec_ff_scanout ;
assign scan_out = outdata_buf_ff_scanout ;
// any PARAMS parms go into naming of macro
module ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_1 (
assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});
// any PARAMS parms go into naming of macro
module ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_64 (
assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}});
.so({so[62:0],scan_out}),
// any PARAMS parms go into naming of macro
module ncu_c2ibuf32_ctl_msff_ctl_macro__en_1__width_55 (
assign fdin[54:0] = (din[54:0] & {55{en}}) | (dout[54:0] & ~{55{en}});
.so({so[53:0],scan_out}),
// any PARAMS parms go into naming of macro
module ncu_c2ibuf32_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module ncu_c2ibuf32_ctl_msff_ctl_macro__width_4 (
assign fdin[3:0] = din[3:0];
// any PARAMS parms go into naming of macro
module ncu_c2ibuf32_ctl_msff_ctl_macro__width_128 (
assign fdin[127:0] = din[127:0];
.si({scan_in,so[126:0]}),
.so({so[126:0],scan_out}),
// any PARAMS parms go into naming of macro
module ncu_c2ibuf32_ctl_l1clkhdr_ctl_macro (