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// OpenSPARC T2 Processor File: fflp_cam_srch_sm.v
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/**********************************************************************/
/*module name: fflp_cam_srch_sm */
/* Controls CAM accesses for both CPU commands and */
/*parent module in: fflp_cam_srch */
/*child modules in: none */
/*author name: Jeanne Cai */
/*date created: 03-10-04 */
/* Copyright (c) 2004, Sun Microsystems, Inc. */
/* Sun Proprietary and Confidential */
input[3:0] cam_srch_latency;
output[1:0] data_inp_sel;
output kick_off_ram_srch_sm;
reg kick_off_ram_srch_sm;
wire[3:0] srch_wait_cnt_in;
assign srch_wait_done = (srch_wait_cnt == cam_srch_latency);
kick_off_ram_srch_sm = 1'b0;
case (state) //synopsys parallel_case full_case
// 0in < case -full -parallel -message "0in ERROR: case check in fflp_cam_srch_sm:state"
case (cpu_cmd) //synopsys parallel_case full_case
`NOP_CMD1, `NOP_CMD2, `NOP_CMD3:
next_state = CMD_WR_CYC_2;
next_state = CMD_COMP_CYC_2;
kick_off_ram_srch_sm = 1'b1;
kick_off_ram_srch_sm = 1'b0;
next_state = CMD_WR_CYC_3;
next_state = CMD_WR_CYC_4;
next_state = CMD_COMP_CYC_3;
dffr #(3) state_reg (cclk, reset, next_state, state);
dffr #(4) srch_wait_cnt_reg (cclk, reset, srch_wait_cnt_in, srch_wait_cnt);
assign srch_wait_cnt_in = {4{inc_wait_cnt}} & (srch_wait_cnt + 4'd1);