// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: niu.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
tcu_rdp_rdmc_mbist_start,
tcu_rtx_rxc_ipp0_mbist_start,
tcu_rtx_rxc_ipp1_mbist_start,
tcu_rtx_rxc_mb5_mbist_start,
tcu_rtx_rxc_mb6_mbist_start,
tcu_rtx_rxc_zcp0_mbist_start,
tcu_rtx_rxc_zcp1_mbist_start,
tcu_rtx_txc_txe0_mbist_start,
tcu_rtx_txc_txe1_mbist_start,
tcu_tds_tdmc_mbist_start,
rtx_rxc_ipp0_tcu_mbist_done,
rtx_rxc_ipp0_tcu_mbist_fail,
rtx_rxc_ipp1_tcu_mbist_done,
rtx_rxc_ipp1_tcu_mbist_fail,
rtx_rxc_mb5_tcu_mbist_done,
rtx_rxc_mb5_tcu_mbist_fail,
rtx_rxc_mb6_tcu_mbist_done,
rtx_rxc_mb6_tcu_mbist_fail,
rtx_rxc_zcp0_tcu_mbist_done,
rtx_rxc_zcp0_tcu_mbist_fail,
rtx_rxc_zcp1_tcu_mbist_done,
rtx_rxc_zcp1_tcu_mbist_fail,
rtx_txc_txe0_tcu_mbist_done,
rtx_txc_txe0_tcu_mbist_fail,
rtx_txc_txe1_tcu_mbist_done,
rtx_txc_txe1_tcu_mbist_fail,
tcu_asic_se_scancollar_in,
tcu_asic_se_scancollar_out,
tcu_asic_array_wr_inhibit,
input [4:0] dbg1_niu_dbg_sel;
input efu_niu_4k_xfer_en;
input efu_niu_cfifo0_clr;
input efu_niu_cfifo0_xfer_en;
input efu_niu_cfifo1_clr;
input efu_niu_cfifo1_xfer_en;
input efu_niu_cfifo_data;
input efu_niu_ipp0_xfer_en;
input efu_niu_ipp1_xfer_en;
input efu_niu_mac01_sfro_data;
input efu_niu_mac0_ro_clr;
input efu_niu_mac0_ro_xfer_en;
input efu_niu_mac0_sf_clr;
input efu_niu_mac0_sf_xfer_en;
input efu_niu_mac1_ro_clr;
input efu_niu_mac1_ro_xfer_en;
input efu_niu_mac1_sf_clr;
input efu_niu_mac1_sf_xfer_en;
input efu_niu_ram0_xfer_en;
input efu_niu_ram1_xfer_en;
input efu_niu_ram_xfer_en;
input gl_mac_io_clk_stop;
input mac_125rx_test_clk;
input mac_125tx_test_clk;
input mac_156rx_test_clk;
input mac_156tx_test_clk;
input mac_312rx_test_clk;
input mac_312tx_test_clk;
input [31:0] ncu_niu_data;
input rdp_rdmc_mbist_scan_in;
input [127:0] sio_niu_data;
input [7:0] sio_niu_parity;
input tcu_mbist_user_mode;
input tcu_rdp_rdmc_mbist_start;
input [2:0] tcu_rtx_dmo_ctl;
input tcu_rtx_rxc_ipp0_mbist_start;
input tcu_rtx_rxc_ipp1_mbist_start;
input tcu_rtx_rxc_mb5_mbist_start;
input tcu_rtx_rxc_mb6_mbist_start;
input tcu_rtx_rxc_zcp0_mbist_start;
input tcu_rtx_rxc_zcp1_mbist_start;
input tcu_rtx_txc_txe0_mbist_start;
input tcu_rtx_txc_txe1_mbist_start;
input tcu_sbs_actestsignal;
input tcu_tds_smx_mbist_start;
input tcu_tds_tdmc_mbist_start;
output arb0_rcr_data_req;
output arb0_rcr_req_accept;
output arb0_rdc_data_req;
output arb0_rdc_req_accept;
output arb1_rbr_req_accept;
output arb1_rbr_req_errors;
output mac_mcu_3_sbs_output;
output niu_dbg1_stall_ack;
output niu_efu_4k_xfer_en;
output niu_efu_cfifo0_data;
output niu_efu_cfifo0_xfer_en;
output niu_efu_cfifo1_data;
output niu_efu_cfifo1_xfer_en;
output niu_efu_ipp0_data;
output niu_efu_ipp0_xfer_en;
output niu_efu_ipp1_data;
output niu_efu_ipp1_xfer_en;
output niu_efu_mac0_ro_data;
output niu_efu_mac0_ro_xfer_en;
output niu_efu_mac0_sf_data;
output niu_efu_mac0_sf_xfer_en;
output niu_efu_mac1_ro_data;
output niu_efu_mac1_ro_xfer_en;
output niu_efu_mac1_sf_data;
output niu_efu_mac1_sf_xfer_en;
output niu_efu_ram0_data;
output niu_efu_ram0_xfer_en;
output niu_efu_ram1_data;
output niu_efu_ram1_xfer_en;
output niu_efu_ram_xfer_en;
output [1:0] niu_mio_debug_clock;
output [31:0] niu_mio_debug_data;
output [31:0] niu_ncu_data;
output [127:0] niu_sii_data;
output [7:0] niu_sii_parity;
output niu_sii_reqbypass;
output niu_txc_interrupts;
output rdp_rdmc_mbist_scan_out;
output rdp_rdmc_tcu_mbist_done;
output rdp_rdmc_tcu_mbist_fail;
output [39:0] rdp_tcu_dmo_dout;
output rtx_mbist_scan_out;
output rtx_rxc_ipp0_tcu_mbist_done;
output rtx_rxc_ipp0_tcu_mbist_fail;
output rtx_rxc_ipp1_tcu_mbist_done;
output rtx_rxc_ipp1_tcu_mbist_fail;
output rtx_rxc_mb5_tcu_mbist_done;
output rtx_rxc_mb5_tcu_mbist_fail;
output rtx_rxc_mb6_tcu_mbist_done;
output rtx_rxc_mb6_tcu_mbist_fail;
output rtx_rxc_zcp0_tcu_mbist_done;
output rtx_rxc_zcp0_tcu_mbist_fail;
output rtx_rxc_zcp1_tcu_mbist_done;
output rtx_rxc_zcp1_tcu_mbist_fail;
output [39:0] rtx_tcu_dmo_data_out;
output rtx_txc_txe0_tcu_mbist_done;
output rtx_txc_txe0_tcu_mbist_fail;
output rtx_txc_txe1_tcu_mbist_done;
output rtx_txc_txe1_tcu_mbist_fail;
output [63:0] tdmc_pio_intr;
output tds_mbist_scan_out;
output tds_smx_tcu_mbist_done;
output tds_smx_tcu_mbist_fail;
output [39:0] tds_tcu_dmo_dout;
output tds_tdmc_tcu_mbist_done;
output tds_tdmc_tcu_mbist_fail;
input gl_rst_niu_wmr_c1b;
input tcu_asic_se_scancollar_in;
input tcu_asic_se_scancollar_out;
input tcu_asic_array_wr_inhibit;
input gl_rdp_io_clk_stop;
input gl_tds_io_clk_stop;
input gl_rtx_io_clk_stop;
input [2:0] tcu_srd_atpgmode;
wire [9:0] esr_mac_rxd0_0;
wire [9:0] esr_mac_rxd0_1;
wire [9:0] esr_mac_rxd1_0;
wire [9:0] esr_mac_rxd1_1;
wire [9:0] esr_mac_rxd2_0;
wire [9:0] esr_mac_rxd2_1;
wire [9:0] esr_mac_rxd3_0;
wire [9:0] esr_mac_rxd3_1;
wire [9:0] mac_esr_txd0_0;
wire [9:0] mac_esr_txd0_1;
wire [9:0] mac_esr_txd1_0;
wire [9:0] mac_esr_txd1_1;
wire [9:0] mac_esr_txd2_0;
wire [9:0] mac_esr_txd2_1;
wire [9:0] mac_esr_txd3_0;
wire [9:0] mac_esr_txd3_1;
reg rdp_niu_pio_ucb_niu_clk;
reg tds_niu_smx_niu_reset_l;
rdp_niu_pio_ucb_niu_clk = 1'b0;
tds_niu_smx_niu_clk = 1'b0;
tds_niu_smx_niu_reset_l = 1'b0;
always @(posedge cmp_gclk_c0_rdp)
rdp_niu_pio_ucb_niu_clk = #1 gl_io_out_c1b;
always @(posedge cmp_gclk_c0_tds)
tds_niu_smx_niu_clk = #1 gl_io_out_c1b;
always @(posedge cmp_gclk_c0_rtx)
rtx_txc_niu_clk = #1 gl_io_out_c1b;
always @(posedge tds_niu_smx_niu_clk)
tds_niu_smx_niu_reset_l <= cluster_arst_l;
if ($test$plusargs("live_interval="))
status = $value$plusargs("live_interval=%d", live_interval);
$display($time, " SYSTEMC: live");
if ($test$plusargs("dump_niu=")) begin
$fsdbDumpvars(0, tb_top.cpu.niu);
$fsdbDumpvars(0, tb_top.enet_model);
niu_ncu_interface niu_ncu_interface(
.niu_ncu_data (niu_ncu_data),
.niu_ncu_vld (niu_ncu_vld),
.niu_ncu_stall (niu_ncu_stall),
.ncu_niu_data (ncu_niu_data),
.ncu_niu_vld (ncu_niu_vld),
.ncu_niu_stall (ncu_niu_stall),
.clk (rdp_niu_pio_ucb_niu_clk),
.niu_rd_addr (niu_rd_addr),
.niu_rd_data (niu_rd_data));
$display("NIU_READ to sas: %h %h", {8'h81, 5'h0, niu_rd_addr}, niu_rd_data);
if (`PARGS.nas_check_on )
niu_csr = $sim_send(`PLI_CSR_READ, {24'h0, 8'h81, 5'h0, niu_rd_addr}, niu_rd_data, 8'h01);
niu_siu_interface niu_siu_interface(
.clk (rdp_niu_pio_ucb_niu_clk),
.niu_sii_hdr_vld (niu_sii_hdr_vld),
.niu_sii_reqbypass (niu_sii_reqbypass),
.sio_niu_data (sio_niu_data),
.sio_niu_datareq (sio_niu_datareq),
.sio_niu_parity (sio_niu_parity),
.niu_sio_dq (niu_sio_dq),
.niu_sii_data (niu_sii_data),
.niu_sii_parity (niu_sii_parity),
.niu_sii_datareq (niu_sii_datareq),
.sio_niu_hdr_vld (sio_niu_hdr_vld),
.sii_niu_bqdq (sii_niu_bqdq),
.sii_niu_oqdq (sii_niu_oqdq));
.esr_mac_rxd0 (esr_mac_rxd0_0),
.esr_mac_rxd1 (esr_mac_rxd1_0),
.esr_mac_rxd2 (esr_mac_rxd2_0),
.esr_mac_rxd3 (esr_mac_rxd3_0),
.mac_esr_txd0 (mac_esr_txd0_0),
.mac_esr_txd1 (mac_esr_txd1_0),
.mac_esr_txd2 (mac_esr_txd2_0),
.mac_esr_txd3 (mac_esr_txd3_0),
.mac_clk (XAUI0_REFCLK_P),
.reset (~gl_rst_mac_c1b));
.esr_mac_rxd0 (esr_mac_rxd0_1),
.esr_mac_rxd1 (esr_mac_rxd1_1),
.esr_mac_rxd2 (esr_mac_rxd2_1),
.esr_mac_rxd3 (esr_mac_rxd3_1),
.mac_esr_txd0 (mac_esr_txd0_1),
.mac_esr_txd1 (mac_esr_txd1_1),
.mac_esr_txd2 (mac_esr_txd2_1),
.mac_esr_txd3 (mac_esr_txd3_1),
.mac_clk (XAUI0_REFCLK_P),
.reset (~gl_rst_mac_c1b));
niu_mac_interface niu_mac_interface (
.reset (~gl_rst_mac_c1b),
.mac_clk (XAUI0_REFCLK_P),
.esr_mac_rxd0_0 (esr_mac_rxd0_0),
.esr_mac_rxd0_1 (esr_mac_rxd0_1),
.esr_mac_rxd1_0 (esr_mac_rxd1_0),
.esr_mac_rxd1_1 (esr_mac_rxd1_1),
.esr_mac_rxd2_0 (esr_mac_rxd2_0),
.esr_mac_rxd2_1 (esr_mac_rxd2_1),
.esr_mac_rxd3_0 (esr_mac_rxd3_0),
.esr_mac_rxd3_1 (esr_mac_rxd3_1),
.mac_esr_txd0_0 (mac_esr_txd0_0),
.mac_esr_txd0_1 (mac_esr_txd0_1),
.mac_esr_txd1_0 (mac_esr_txd1_0),
.mac_esr_txd1_1 (mac_esr_txd1_1),
.mac_esr_txd2_0 (mac_esr_txd2_0),
.mac_esr_txd2_1 (mac_esr_txd2_1),
.mac_esr_txd3_0 (mac_esr_txd3_0),
.mac_esr_txd3_1 (mac_esr_txd3_1)
clock_multiplier_10x clock_multiplier_10x(XAUI0_REFCLK_P, xaui_clk);
assign arb0_rcr_data_req = 1'b0;
assign arb0_rcr_req_accept = 1'b0;
assign arb0_rdc_data_req = 1'b0;
assign arb0_rdc_req_accept = 1'b0;
assign arb1_rbr_req_accept = 1'b0;
assign arb1_rbr_req_errors = 1'b0;
assign mac_mcu_3_sbs_output = 1'b0;
assign mac_scan_out = 1'b0;
assign niu_efu_4k_data = 1'b0;
assign niu_efu_4k_xfer_en = 1'b0;
assign niu_efu_cfifo0_data = 1'b0;
assign niu_efu_cfifo0_xfer_en = 1'b0;
assign niu_efu_cfifo1_data = 1'b0;
assign niu_efu_cfifo1_xfer_en = 1'b0;
assign niu_efu_fdo = 1'b0;
assign niu_efu_ipp0_data = 1'b0;
assign niu_efu_ipp0_xfer_en = 1'b0;
assign niu_efu_ipp1_data = 1'b0;
assign niu_efu_ipp1_xfer_en = 1'b0;
assign niu_efu_mac0_ro_data = 1'b0;
assign niu_efu_mac0_ro_xfer_en = 1'b0;
assign niu_efu_mac0_sf_data = 1'b0;
assign niu_efu_mac0_sf_xfer_en = 1'b0;
assign niu_efu_mac1_ro_data = 1'b0;
assign niu_efu_mac1_ro_xfer_en = 1'b0;
assign niu_efu_mac1_sf_data = 1'b0;
assign niu_efu_mac1_sf_xfer_en = 1'b0;
assign niu_efu_ram0_data = 1'b0;
assign niu_efu_ram0_xfer_en = 1'b0;
assign niu_efu_ram1_data = 1'b0;
assign niu_efu_ram1_xfer_en = 1'b0;
assign niu_efu_ram_data = 1'b0;
assign niu_efu_ram_xfer_en = 1'b0;
assign niu_mio_debug_clock = 2'b00;
assign niu_mio_debug_data = 32'h00000000;
assign niu_dbg1_stall_ack = 1'b0;
assign niu_ncu_ctag_ce = 1'b0;
assign niu_ncu_ctag_ue = 1'b0;
assign niu_ncu_d_pe = 1'b0;
//assign niu_ncu_data = [31:0]
assign niu_txc_interrupts = 1'b0;
assign rdp_rdmc_mbist_scan_out = 1'b0;
assign rdp_rdmc_tcu_mbist_done = 1'b0;
assign rdp_rdmc_tcu_mbist_fail = 1'b0;
assign rdp_scan_out = 1'b0;
assign rdp_tcu_dmo_dout = 1'b0;
assign rtx_mbist_scan_out = 1'b0;
assign rtx_rxc_ipp0_tcu_mbist_done = 1'b0;
assign rtx_rxc_ipp0_tcu_mbist_fail = 1'b0;
assign rtx_rxc_ipp1_tcu_mbist_done = 1'b0;
assign rtx_rxc_ipp1_tcu_mbist_fail = 1'b0;
assign rtx_rxc_mb5_tcu_mbist_done = 1'b0;
assign rtx_rxc_mb5_tcu_mbist_fail = 1'b0;
assign rtx_rxc_mb6_tcu_mbist_done = 1'b0;
assign rtx_rxc_mb6_tcu_mbist_fail = 1'b0;
assign rtx_rxc_zcp0_tcu_mbist_done = 1'b0;
assign rtx_rxc_zcp0_tcu_mbist_fail = 1'b0;
assign rtx_rxc_zcp1_tcu_mbist_done = 1'b0;
assign rtx_rxc_zcp1_tcu_mbist_fail = 1'b0;
assign rtx_txc_txe0_tcu_mbist_done = 1'b0;
assign rtx_txc_txe0_tcu_mbist_fail = 1'b0;
assign rtx_txc_txe1_tcu_mbist_done = 1'b0;
assign rtx_txc_txe1_tcu_mbist_fail = 1'b0;
assign rtx_scan_out = 1'b0;
assign rtx_tcu_dmo_data_out = 40'h0000000000;
assign tdmc_pio_intr = 64'h0000000000000000;
assign tds_mbist_scan_out = 1'b0;
assign tds_scan_out = 1'b0;
assign tds_smx_tcu_mbist_done = 1'b0;
assign tds_smx_tcu_mbist_fail = 1'b0;
assign tds_tcu_dmo_dout = 40'h0000000000;
assign tds_tdmc_tcu_mbist_done = 1'b0;
assign tds_tdmc_tcu_mbist_fail = 1'b0;
assign xaui_act_led_0 = 1'b0;
assign xaui_act_led_1 = 1'b0;
assign xaui_link_led_0 = 1'b0;
assign xaui_link_led_1 = 1'b0;