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// OpenSPARC T2 Processor File: niu_meta_rd_tagfifo.v
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/*********************************************************************
* Parameterized synchronous fifo for buffering data and commands
* in the gpi data path, this fifo is initialized with default tags
* Original Author(s): Nimita Taneja
* Copyright (c) 2004 Sun Microsystems, Inc.
* Revision History: 03-01-2004 : Initial Release
* This verilog model is the confidential and proprietary property of
* Sun Microsystems, Inc., and the possession or use of this model
* requires a written license from Sun Microsystems, Inc.
**********************************************************************/
module niu_meta_rd_tagfifo (core_clk, reset , inc_rp, inc_wp, fifo_not_empty,
fifo_full, din, rdout, dout, count);
parameter [31:0] DEPTH = 32;
input core_clk, reset , inc_rp, inc_wp;
output fifo_not_empty, fifo_full;
output [WIDTH-1:0] rdout;
reg [WIDTH-1:0] fifo[0:DEPTH-1];
assign fifo_full = (fifosize==DEPTH[ASIZE:0]);
// synopsys translate_off
always@(posedge core_clk) begin
else if (fifo_full & inc_wp) begin
$display($time, " %m -ERROR: fifo overrun !!!!!!!!!");
repeat(10) @(posedge core_clk);
else if ((fifosize == 0) & inc_rp) begin
$display($time, " %m -ERROR: fifo underrun !!!!!!!!!");
repeat(10) @(posedge core_clk);
always@(posedge core_clk)
if (reset) fifosize <= 6'd32;
else if (inc_wp & !inc_rp) fifosize <= fifosize +1'b1;
else if (!inc_wp & inc_rp) fifosize <= fifosize -1'b1;
else fifosize <= fifosize;
assign fifo_not_empty = fifosize > 0;
assign fifo_empty = (fifosize == 0);
always@(posedge core_clk )
else if (inc_wp & !fifo_full) wp <= wp + 1'b1;
always@(posedge core_clk)
else if (inc_rp & !fifo_empty) rp <= rp + 1'b1;
always@(posedge core_clk )
// for (i=0; i<DEPTH; i=i+1) fifo[i] <= i;
for (i=0; i<DEPTH; i=i+1) fifo[i] <= fifo[i];
always@(rp or fifo[0] or fifo[1] or fifo_not_empty)
case(rp) // synopsys parallel_case
1'b0: dout = fifo[0] & {WIDTH{fifo_not_empty}};
1'b1: dout = fifo[1] & {WIDTH{fifo_not_empty}};
default: dout = fifo[0] & {WIDTH{fifo_not_empty}};
assign dout = fifo[rp] & {WIDTH{fifo_not_empty}};
always@(posedge core_clk)