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// OpenSPARC T2 Processor File: niu_ram_s_4096x9.v
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/**********************************************************
***********************************************************
File name : niu_ram_s_4096x9.v
Module(s) name : niu_ram_s_4096x9
Author's name : George Chu
************************************************************
***********************************************************/
module niu_ram_s_4096x9 (
parameter DATA_WIDTH_MINUS1 = 8;
parameter ADDR_WIDTH_MINUS1 = 11;
input reset; // if 1, reset the logic
input tcu_se_scancollar_in;
input tcu_se_scancollar_out;
input tcu_array_wr_inhibit;
input [5:0] hdr_sram_rvalue;
output [5:0] sram_hdr_read_data;
input [DATA_WIDTH_MINUS1:0] mbi_wdata;
input [ADDR_WIDTH_MINUS1:0] mbi_rw_adr;
input [DATA_WIDTH_MINUS1:0] data_inp; // data_input,
input [ADDR_WIDTH_MINUS1:0] addr_rw; // read/write_address,
input wt_enable; // write_enable, via port_B
input cs_rd; // chip_selet_rd_port
output [DATA_WIDTH_MINUS1:0] data_out; // data read out, via port_A
wire [DATA_WIDTH_MINUS1:0] data_out;
wire [5:0] sram_hdr_read_data;
wire [ADDR_WIDTH_MINUS1:0] mux_rw_adr;
wire [DATA_WIDTH_MINUS1:0] mux_wdata;
assign mux_wdata = mbi_run ? mbi_wdata : data_inp;
assign mux_rw_adr = mbi_run ? mbi_rw_adr : addr_rw;
assign mux_wr_en = mbi_run ? mbi_wr_en : wt_enable;
assign mux_rd_en = mbi_run ? mbi_rd_en : cs_rd;
n2_niu_sp_4096x9s_cust ram_4096x9_0 (
.tcu_scan_en (tcu_scan_en),
.tcu_se_scancollar_in (tcu_se_scancollar_in),
.tcu_se_scancollar_out (tcu_se_scancollar_out),
.tcu_array_wr_inhibit (tcu_array_wr_inhibit),
.hdr_sram_rvalue (hdr_sram_rvalue[5:0]),
.hdr_sram_rid (hdr_sram_rid),
.hdr_sram_wr_en (hdr_sram_wr_en),
.hdr_sram_red_clr (hdr_sram_red_clr),
.sram_hdr_read_data (sram_hdr_read_data[5:0]),
.rw_adr (mux_rw_adr[11:0]),