// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: niu_smx_pio.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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reg_timer_cfg, reg_ras_cfg, smx_pio_intr, smx_pio_status,
smx_debug_port, pio_xtb_err_inject_cfg, pio_resp_err_inject_cfg,
clk, reset_l, pio_data, pio_smx_clear_intr, pio_smx_ctrl,
pio_smx_debug_vector, tohdl_set_intr, tohdl_intr_status,
niu_sii_hdr_vld, niu_sii_reqbypass, niu_sii_datareq, sii_niu_oqdq,
sii_niu_bqdq, wreq_cmdff_rd, rdreq_cmdff_rd, wreq_dataff_rd,
wreq_cmdff_wr, rdreq_cmdff_wr, wreq_dataff_wr, sio_niu_hdr_vld,
sio_niu_datareq, niu_sio_dq, resp_cmdff_wr, resp_dataff_wr,
resp_cmdff_rd, resp_dataff_rd, meta_dmc_resp_ready,
meta_dmc_ack_ready, dmc_meta0_req, meta_dmc1_req_accept,
dmc_meta1_req, meta_dmc0_req_accept, meta_dmc0_data_req,
dmc_meta0_data_valid, sii_cs, arb_cs, rdreq_cmd_cs, wreq_cmd_cs,
wreq_dv_cs, dreq_cs, proc_cs, cmdl_cs, dv_cs
output [31:0] reg_timer_cfg;
output [1:0] reg_ras_cfg;
output smx_pio_intr; // level signal;
// once high stays high until clear by pio
output[31:0] smx_pio_status; // status info related to intr
input pio_smx_clear_intr; // a pulse
input [31:0] pio_smx_ctrl; // debug select; extra bits
// reserved within smx in case
input [31:0] pio_smx_debug_vector; // training vector
output [31:0] smx_debug_port;
input [5:0] tohdl_intr_status;
// xtb i/f (error inject)
output [2:0] pio_xtb_err_inject_cfg; // [0] - one pkt
// resp_dv i/f (err inject)
output [2:0] pio_resp_err_inject_cfg; // [0] - one pkt
input meta_dmc_resp_ready;
input meta_dmc_ack_ready;
input meta_dmc1_req_accept;
input meta_dmc0_req_accept;
input meta_dmc0_data_req;
input dmc_meta0_data_valid;
input [2:0] rdreq_cmd_cs;
// don't have anything to intr for now
// wire smx_pio_intr= 1'b0;
// wire [31:0] smx_pio_status= 32'h0;
wire [31:0] reg_timer_cfg= reg_smx_cfg;
wire [1:0] reg_ras_cfg= reg_smx_cfg[31:30];
reg [31:0] pio_smx_debug_vector_r;
reg [31:0] smx_debug_port, smx_debug_port_n;
reg [31:0] int_debug_port;
reg [5:0] pio_status_tohdl;
wire [31:0] smx_pio_status= {int_status, pio_status_tohdl};
reg [2:0] pio_xtb_err_inject_cfg;
reg [2:0] pio_resp_err_inject_cfg;
always @(posedge clk) begin
smx_pio_intr<= `SMX_PD 1'b0;
if(tohdl_set_intr) smx_pio_intr<= `SMX_PD 1'b1;
else if (pio_smx_clear_intr) smx_pio_intr<= `SMX_PD 1'b0;
always @(posedge clk) begin
pio_status_tohdl<= `SMX_PD 6'h0;
if(tohdl_set_intr) pio_status_tohdl<= `SMX_PD tohdl_intr_status;
else if (pio_smx_clear_intr) pio_status_tohdl<= `SMX_PD 6'h0;
always @(posedge clk) begin
int_status<= `SMX_PD 26'h0;
int_status<= `SMX_PD {3'h0,
rdreq_cmd_cs, wreq_cmd_cs,
proc_cs, cmdl_cs, dv_cs};
always @(posedge clk) begin
reg_smx_cfg<= `SMX_PD {32'hFFFFFFFF}; // cc 051905 to default enable
else // disable ras for now ????
// if(pio_ld) // enable when verif env chg to support ???
reg_smx_cfg<= `SMX_PD pio_data[31:0];
always @(posedge clk) begin
smx_debug_port<= `SMX_PD smx_debug_port_n;
pio_smx_debug_vector_r<= `SMX_PD pio_smx_debug_vector;
debug_sel<= `SMX_PD pio_smx_ctrl[2:0];
always @(posedge clk) begin
pio_xtb_err_inject_cfg<= `SMX_PD 3'h0;
pio_resp_err_inject_cfg<= `SMX_PD 3'h0;
pio_xtb_err_inject_cfg<= `SMX_PD pio_smx_ctrl[6:4];
pio_resp_err_inject_cfg<= `SMX_PD pio_smx_ctrl[10:8];
always @(posedge clk) begin
int_debug_port<= `SMX_PD { 6'h0,
/*AUTO_CONSTANT (`META_ARB__TRAINING_SET `MEGA_ARB__TRAINING_LOAD)*/
always @ (/*AUTOSENSE*/ debug_sel or int_debug_port or pio_smx_debug_vector_r
`SMX_TRAINING_SET: smx_debug_port_n= ~smx_debug_port;
`SMX_TRAINING_LOAD: smx_debug_port_n= pio_smx_debug_vector_r;
default: smx_debug_port_n= int_debug_port;