// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: xpcs.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
/*************************************************************************
* Author Name : Carlos Castil
* Description : This module performs 802.3ae 10Gbps pcs function
* Refer to 802.3ae Clause 36, 46, and 48
* Parent Module: xmac_2pcs_core
* Copyright (c) 2003, Sun Microsystems, Inc.
* Sun Proprietary and Confidential
*************************************************************************/
clk, // System input clock
tx_clk, // MAC TX input Clk 312 MHz (tx_clk div 2)
rbc0_a, // chan a input clock from Serdes 312 Mhz rx clock <===== NEW CLOCK
rbc0_b, // chan b input clock form Serdes 312 Mhz rx clock
rbc0_c, // chan c input clock form Serdes 312 Mhz rx clock
rbc0_d, // chan d input clock form Serdes 312 Mhz rx clock
xrx_code_group, // Serdes to xpcs receive symbols
xtx_code_group, // xpcs to Serdes transmit symbols
xlink_up_tx, // signal to on-board LED, low pulse elongated
xsignal_detect, // input from optics which indicates light ok. Inputs from Sequence Detect.
xserdes_rdy, // input from serdes to indicate that the serdes pll is locked
xpcs_rxd, // XGMII data going onto xGMII
xpcs_rxc, // XGMII receive data valid, GMII interface
xpcs_txd, // XGMII byte from MAC over GMII
xpcs_txc, // XGMII transmit enable from Mac
pio_core_reset, // pio signals
input tx_clk; // 312 Mhz reference from serdes
input rbc0_a; // 312 Mhz rx clock from serdes
input rbc0_b; // 312 Mhz rx clock from serdes
input rbc0_c; // 312 Mhz rx clock from serdes
input rbc0_d; // 312 Mhz rx clock from serdes
input [79:0] xrx_code_group; // symbol to send over link
output [79:0] xtx_code_group; // symbol to send over link
input [3:0] xsignal_detect; // Input from optics which indicates light ok.
input xserdes_rdy; // Input from Serdes to indicate pll lock
output xlink_up_tx; // signal to on-board LED, low pulse elongated
output [63:0] xpcs_rxd; // data going onto xGMII
output [7:0] xpcs_rxc; // receive data valid, xGMII interface
output [31:0] xpcs_debug;
input [63:0] xpcs_txd; // 4 bytes from MAC over xGMII
input [7:0] xpcs_txc; // xGMII transmit enable from Mac
input pio_core_reset; // hw_reset
output [31:0] rdata_xpcs;
wire csr_pulse_deskew_error;
wire [7:0] csr_ebuffer_state;
wire csr_bypass_signal_detect;
wire [3:0] csr_lane_sync_status;
wire [79:0] xrx_code_group; // symbol to send over link
wire [79:0] xtx_code_group; // symbol to send over link
wire [39:0] xtx_code_group_mux;
wire [39:0] xrx_code_group_muxout;
wire [3:0] csr_lane_sync_state0;
wire [3:0] csr_lane_sync_state1;
wire [3:0] csr_lane_sync_state2;
wire [3:0] csr_lane_sync_state3;
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire inc_tx_pkt_count_ref;
wire inc_rx_pkt_count_ref;
wire csr_enable_tx_buffers;
wire csr_trigger_transmit_fault;
wire csr_trigger_receive_fault;
wire [1:0] csr_test_pattern_sel;
wire [7:0] tx_byte_0_enc;
wire [7:0] tx_byte_1_enc;
wire [7:0] tx_byte_2_enc;
wire [7:0] tx_byte_3_enc;
wire [7:0] tx_xgmii_byte_0;
wire [7:0] tx_xgmii_byte_1;
wire [7:0] tx_xgmii_byte_2;
wire [7:0] tx_xgmii_byte_3;
wire [7:0] rx_xgmii_byte_0;
wire [7:0] rx_xgmii_byte_1;
wire [7:0] rx_xgmii_byte_2;
wire [7:0] rx_xgmii_byte_3;
wire csr_transmit_fault_ref;
wire csr_receive_fault_ref;
wire [3:0] csr_vendor_debug_sel;
wire csr_vendor_debug_io_test;
wire [31:0] training_vector;
wire rx_symbols_dft_dummy;
wire trigger_symbol_err_cnt0;
wire trigger_symbol_err_cnt1;
wire trigger_symbol_err_cnt2;
wire trigger_symbol_err_cnt3;
assign xpcs_loopback = csr_loopback;
assign xlink_up_tx = csr_link_status;
.clr_sw_reset(clr_sw_reset),
.pio_err_xpcs(pio_err_xpcs),
.xpcs_interrupt(xpcs_interrupt),
.csr_vendor_debug_sel (csr_vendor_debug_sel),
.csr_vendor_debug_io_test(csr_vendor_debug_io_test),
.training_vector (training_vector),
.csr_xpcs_enable(csr_xpcs_enable),
.csr_link_status(csr_link_status),
.csr_ebuffer_state(csr_ebuffer_state),
.csr_receive_state(csr_receive_state),
.csr_bypass_signal_detect(csr_bypass_signal_detect),
.csr_tx_test_enable(csr_tx_test_enable),
.csr_test_pattern_sel(csr_test_pattern_sel),
.inc_deskew_error(inc_deskew_error),
.inc_tx_pkt_count(inc_tx_pkt_count),
.inc_rx_pkt_count(inc_rx_pkt_count),
.csr_trigger_transmit_fault(csr_trigger_transmit_fault),
.csr_trigger_receive_fault(csr_trigger_receive_fault),
.csr_lane_sync_status(csr_lane_sync_status),
.csr_loopback(csr_loopback),
.csr_low_power(csr_low_power),
.csr_enable_tx_buffers(csr_enable_tx_buffers),
.csr_tx_state(csr_tx_state),
.csr_lane_sync_state0(csr_lane_sync_state0),
.csr_lane_sync_state1(csr_lane_sync_state1),
.csr_lane_sync_state2(csr_lane_sync_state2),
.csr_lane_sync_state3(csr_lane_sync_state3),
.trigger_symbol_err_cnt0(trigger_symbol_err_cnt0),
.trigger_symbol_err_cnt1(trigger_symbol_err_cnt1),
.trigger_symbol_err_cnt2(trigger_symbol_err_cnt2),
.trigger_symbol_err_cnt3(trigger_symbol_err_cnt3)
.reset_rxclk(reset_rxclk),
.rx_signal_detect(xsignal_detect),
.rx_special_0(rx_special_0),
.rx_special_1(rx_special_1),
.rx_special_2(rx_special_2),
.rx_special_3(rx_special_3),
.rx_symbol_a(xrx_code_group_muxout[9:0]),
.rx_symbol_b(xrx_code_group_muxout[19:10]),
.rx_symbol_c(xrx_code_group_muxout[29:20]),
.rx_symbol_d(xrx_code_group_muxout[39:30]),
.csr_lane_sync_status(csr_lane_sync_status),
.csr_lane_sync_state0(csr_lane_sync_state0),
.csr_lane_sync_state1(csr_lane_sync_state1),
.csr_lane_sync_state2(csr_lane_sync_state2),
.csr_lane_sync_state3(csr_lane_sync_state3),
.csr_link_status(csr_link_status),
.csr_link_status_rx(csr_link_status_rx),
.csr_pulse_deskew_error(csr_pulse_deskew_error),
.csr_ebuffer_state(csr_ebuffer_state) );
.reset_rxclk(reset_rxclk),
.state(csr_receive_state),
.csr_xpcs_enable(csr_xpcs_enable),
.csr_link_status_rx(csr_link_status_rx),
.csr_tx_test_enable(csr_tx_test_enable),
.csr_receive_fault_ref(csr_receive_fault_ref),
.inc_rx_pkt_count_ref(inc_rx_pkt_count_ref),
.xserdes_rdy(xserdes_rdy),
.rx_xgmii_byte_0(rx_xgmii_byte_0),
.rx_xgmii_byte_1(rx_xgmii_byte_1),
.rx_xgmii_byte_2(rx_xgmii_byte_2),
.rx_xgmii_byte_3(rx_xgmii_byte_3),
.rx_xgmii_special_0(rx_xgmii_special_0),
.rx_xgmii_special_1(rx_xgmii_special_1),
.rx_xgmii_special_2(rx_xgmii_special_2),
.rx_xgmii_special_3(rx_xgmii_special_3),
.rx_special_0(rx_special_0),
.rx_special_1(rx_special_1),
.rx_special_2(rx_special_2),
.rx_special_3(rx_special_3),
xpcs_xgmii_dpath xpcs_xgmii_dpath (
.reset_txclk (reset_txclk),
.reset_rxclk (reset_rxclk),
.tx_clk (tx_clk), // 312 mhz tx clk
.rbc0_a (rbc0_a), // 312 mhz rx clk
.xpcs_rxd(xpcs_rxd), // outputs to XMAC receive
.xpcs_txd(xpcs_txd), // inputs from XMAC transmit
// inputs from XPCS receive
.rx_xgmii_byte_0(rx_xgmii_byte_0),
.rx_xgmii_byte_1(rx_xgmii_byte_1),
.rx_xgmii_byte_2(rx_xgmii_byte_2),
.rx_xgmii_byte_3(rx_xgmii_byte_3),
.rx_xgmii_special_0(rx_xgmii_special_0),
.rx_xgmii_special_1(rx_xgmii_special_1),
.rx_xgmii_special_2(rx_xgmii_special_2),
.rx_xgmii_special_3(rx_xgmii_special_3),
// outputs to XPCS transmit
.tx_xgmii_byte_0(tx_xgmii_byte_0),
.tx_xgmii_byte_1(tx_xgmii_byte_1),
.tx_xgmii_byte_2(tx_xgmii_byte_2),
.tx_xgmii_byte_3(tx_xgmii_byte_3),
.tx_xgmii_special_0(tx_xgmii_special_0),
.tx_xgmii_special_1(tx_xgmii_special_1),
.tx_xgmii_special_2(tx_xgmii_special_2),
.tx_xgmii_special_3(tx_xgmii_special_3)
.csr_loopback(csr_loopback),
.csr_enable_tx_buffers(csr_enable_tx_buffers),
.rx_symbols_dft_dummy (rx_symbols_dft_dummy),
.tx_symbols_mux(xtx_code_group_mux),
.rx_symbols_mux({xrx_code_group[69:60], // receive in from serdes
.rx_symbols_dft({xrx_code_group[79:70], // receive in from serdes
.tx_symbols_dft({xtx_code_group[79:70],
.xrx_code_group_muxout(xrx_code_group_muxout),
.xtx_code_group({xtx_code_group[69:60], // transmit out to serdes
xpcs_tx xpcs_tx (.tx_clk(tx_clk),
.csr_link_status(csr_link_status),
.csr_tx_test_enable(csr_tx_test_enable),
.csr_test_pattern_sel(csr_test_pattern_sel),
.csr_transmit_fault_ref(csr_transmit_fault_ref),
.inc_tx_pkt_count_ref(inc_tx_pkt_count_ref),
.tx_byte_0(tx_xgmii_byte_0),
.tx_byte_1(tx_xgmii_byte_1),
.tx_byte_2(tx_xgmii_byte_2),
.tx_byte_3(tx_xgmii_byte_3),
.tx_special_0(tx_xgmii_special_0),
.tx_special_1(tx_xgmii_special_1),
.tx_special_2(tx_xgmii_special_2),
.tx_special_3(tx_xgmii_special_3),
.tx_byte_0_enc(tx_byte_0_enc),
.tx_byte_1_enc(tx_byte_1_enc),
.tx_byte_2_enc(tx_byte_2_enc),
.tx_byte_3_enc(tx_byte_3_enc),
.tx_special_0_enc(tx_special_0_enc),
.tx_special_1_enc(tx_special_1_enc),
.tx_special_2_enc(tx_special_2_enc),
.tx_special_3_enc(tx_special_3_enc),
.tx_byte_0(tx_byte_0_enc),
.tx_byte_1(tx_byte_1_enc),
.tx_byte_2(tx_byte_2_enc),
.tx_byte_3(tx_byte_3_enc),
.tx_special_0(tx_special_0_enc),
.tx_special_1(tx_special_1_enc),
.tx_special_2(tx_special_2_enc),
.tx_special_3(tx_special_3_enc),
.tx_symbol_0(xtx_code_group_mux[9:0]),
.tx_symbol_1(xtx_code_group_mux[19:10]),
.tx_symbol_2(xtx_code_group_mux[29:20]),
.tx_symbol_3(xtx_code_group_mux[39:30])
.tx_clk(tx_clk), // 312 Mhz reference from serdes
.csr_transmit_fault_ref(csr_transmit_fault_ref),
.csr_receive_fault_ref(csr_receive_fault_ref),
.csr_trigger_transmit_fault(csr_trigger_transmit_fault),
.csr_trigger_receive_fault(csr_trigger_receive_fault),
.inc_tx_pkt_count_ref(inc_tx_pkt_count_ref),
.inc_rx_pkt_count_ref(inc_rx_pkt_count_ref),
.inc_tx_pkt_count(inc_tx_pkt_count),
.inc_rx_pkt_count(inc_rx_pkt_count),
.csr_pulse_deskew_error(csr_pulse_deskew_error),
.inc_deskew_error(inc_deskew_error),
.pio_core_reset(pio_core_reset),
.reset_txclk(reset_txclk),
.reset_rxclk(reset_rxclk),
.clr_sw_reset(clr_sw_reset),
.trigger_symbol_err_cnt0(trigger_symbol_err_cnt0),
.trigger_symbol_err_cnt1(trigger_symbol_err_cnt1),
.trigger_symbol_err_cnt2(trigger_symbol_err_cnt2),
.trigger_symbol_err_cnt3(trigger_symbol_err_cnt3),
// *****************************************************
// *****************************************************
assign debug_io_test_0 = csr_bypass_signal_detect;
assign debug_io_test_1 = csr_enable_tx_buffers;
reg [39:0] xrx_code_group_muxout_dbg;
always @ (posedge rbc0_a) xrx_code_group_muxout_dbg[9:0] <= xrx_code_group_muxout[9:0];
always @ (posedge rbc0_b) xrx_code_group_muxout_dbg[19:10] <= xrx_code_group_muxout[19:10];
always @ (posedge rbc0_c) xrx_code_group_muxout_dbg[29:20] <= xrx_code_group_muxout[29:20];
always @ (posedge rbc0_d) xrx_code_group_muxout_dbg[39:30] <= xrx_code_group_muxout[39:30];
assign rx0_debug = csr_vendor_debug_io_test ?
{debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1,
debug_io_test_0, debug_io_test_1}
xrx_code_group_muxout_dbg[9:0]};
assign rx1_debug = {3'b000,
xrx_code_group_muxout_dbg[19:10]};
assign rx2_debug = {3'b000,
xrx_code_group_muxout_dbg[29:20]};
assign rx3_debug = {3'b000,
xrx_code_group_muxout_dbg[39:30]};
assign tx0_debug = {4'b0000,
xtx_code_group_mux[9:0]};
assign tx1_debug = {4'b0000,
xtx_code_group_mux[19:10]};
assign tx2_debug = {4'b0000,
xtx_code_group_mux[29:20]};
assign tx3_debug = {4'b0000,
xtx_code_group_mux[39:30]};
xpcs_dbg xpcs_dbg (.csr_vendor_debug_sel (csr_vendor_debug_sel),
.training_vector (training_vector),
.xpcs_debug (xpcs_debug) );