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// OpenSPARC T2 Processor File: xpcs_rxio_sync_deskew_fifo.v
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// ****************************************************************
// Design: IB Phy Interface
// Block: IB RX Phy Interface Controller
// Module: xpcs_rxio_sync_deskew_fifo
// File: xpcs_rxio_sync_deskew_fifo.v
// Description: This block contains a small fifo to allow
// ------------------------------------------------------------
// ------------------------------------------------------------
// 1.0 10/13/02 Fifo size is 16 symbols to accomidate
// IB spec. which allows for 24ns of
// skew....for ieee 802.3ae we need ~14ns
// ****************************************************************
module xpcs_rxio_sync_deskew_fifo (
input w_clk; // Received Clock With Data
input w_rst; // Synchronous Active Low Reset
input [7:0] w_byte; // Decode Data
input w_special; // Decode Control
input w_error; // Decode error
output [7:0] byte; // output data
output special; // output control
output error; // output error
mem_0 <= (w_ptr==3'b000) ? {w_error,w_special,w_byte} : mem_0;
mem_1 <= (w_ptr==3'b001) ? {w_error,w_special,w_byte} : mem_1;
mem_2 <= (w_ptr==3'b010) ? {w_error,w_special,w_byte} : mem_2;
mem_3 <= (w_ptr==3'b011) ? {w_error,w_special,w_byte} : mem_3;
mem_4 <= (w_ptr==3'b100) ? {w_error,w_special,w_byte} : mem_4;
mem_5 <= (w_ptr==3'b101) ? {w_error,w_special,w_byte} : mem_5;
mem_6 <= (w_ptr==3'b110) ? {w_error,w_special,w_byte} : mem_6;
mem_7 <= (w_ptr==3'b111) ? {w_error,w_special,w_byte} : mem_7;
always @ (r_ptr or mem_0 or mem_1 or mem_2 or mem_3 or
mem_4 or mem_5 or mem_6 or mem_7 )
case (r_ptr[2:0]) // synopsys parallel_case full_case infer_mux
3'b000 : {error,special,byte} = mem_0;
3'b001 : {error,special,byte} = mem_1;
3'b010 : {error,special,byte} = mem_2;
3'b011 : {error,special,byte} = mem_3;
3'b100 : {error,special,byte} = mem_4;
3'b101 : {error,special,byte} = mem_5;
3'b110 : {error,special,byte} = mem_6;
3'b111 : {error,special,byte} = mem_7;