// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: csr_sw.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
// synopsys translate_off
//====================================================
//====================================================
// synopsys translate_off
input omni_ld; // Omni write
input omni_data; // Omni write data
input omni_rw_alias; // Omni rw operation
input omni_rw1c_alias; // Omni rw1c operation
input omni_rw1s_alias; // Omni rw1s operation
input rst; // Synch reset
input rst_val; // Synch reset value
input csr_ld; // CSR load
input csr_data; // CSR data
input rw_alias; // rw operation
input rw1c_alias; // rw1c operation
input rw1s_alias; // rw1s operation
input hw_ld; // Internal logic load
input hw_data; // Internal logic data
output q; // Register out
//====================================================
//====================================================
// synopsys translate_off
wire omni_data; // Omni write data
wire omni_ld; // Omni write
wire omni_rw_alias; // Omni rw operation
wire omni_rw1c_alias; // Omni rw1c operation
wire omni_rw1s_alias; // Omni rw1s operation
wire rst_val; // Synch reset value
wire csr_data; // CSR data
wire rw_alias; // rw operation
wire rw1c_alias; // rw1c operation
wire rw1s_alias; // rw1s operation
wire hw_ld; // Internal logic load
wire hw_data; // Internal logic data
//====================================================
//====================================================
// synopsys translate_off
// synopsys translate_off
// async load ok - not synthesized
case({omni_rw_alias,omni_rw1c_alias,omni_rw1s_alias})
begin // axis tbcall_region
// vlint flag_system_call off
`ifdef PR_ERROR if ($time > 1) `PR_ERROR("csr_sw",`MON_ERROR,"acc_vio: default case of csr_sw"); `endif
// vlint flag_system_call on
end // end of tbcall_region
case({rw_alias,rw1c_alias,rw1s_alias})
3'b100: if (csr_data == 1'b1)
3'b010: if (csr_data == 1'b1)
3'b001: if (csr_data == 1'b1)
//BP N2 1-18-05 q <= 1'bx;
begin // axis tbcall_region
// vlint flag_system_call off
// synopsys translate_off
`ifdef PR_ERROR if ($time > 1) `PR_ERROR("csr_sw",`MON_ERROR,"acc_vio: default case of csr_sw"); `endif
// vlint flag_system_call on
end // end of tbcall_region
// synopsys translate_off