// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: pcie_dcm_daemon.v
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// ========== Copyright Header End ============================================
daemon_transaction_in_progress,
// synopsys translate_off
parameter ADDR_WIDTH = 27;
parameter DATA_WIDTH = 64;
// synopsys translate_off
parameter DAEMON_STATE_IDLE = 3'd0;
parameter DAEMON_STATE_RD = 3'd4; // bit 2 is mux select
parameter DAEMON_STATE_WR = 3'd5;
parameter DAEMON_STATE_WAIT_RD = 3'd6;
parameter DAEMON_STATE_WAIT_WR = 3'd7;
output daemon_csrbus_valid;
output [DATA_WIDTH-1:0] daemon_csrbus_wr_data;
output [ADDR_WIDTH-1:0] daemon_csrbus_addr;
output daemon_transaction_in_progress;
input daemon_csrbus_mapped;
input daemon_csrbus_done;
// synopsys translate_off
input [DATA_WIDTH-1:0] csrbus_read_data; // needed to return back to daemon task
input [DATA_WIDTH-1:0] csrbus_wr_data;
input [ADDR_WIDTH-1:0] csrbus_addr;
reg [ADDR_WIDTH-1:0] daemon_csrbus_addr;
reg [DATA_WIDTH-1:0] daemon_csrbus_wr_data;
wire daemon_transaction_in_progress;
// synopsys translate_off
// inputs/outputs from task
reg [ADDR_WIDTH-1:0] daemon_addr;
reg [DATA_WIDTH-1:0] daemon_wr_data;
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [DATA_WIDTH-1:0] daemon_rd_data;
// vlint flag_net_has_no_load on
// vlint flag_dangling_net_within_module on
reg [ADDR_WIDTH-1:0] daemon_addr_reg;
reg [DATA_WIDTH-1:0] daemon_wr_data_reg;
reg daemon_csrbus_done_reg;
// done signals back to verif
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
// vlint flag_variable_assign_never_reference off
// vlint flag_variable_assign_never_reference on
// vlint flag_net_has_no_load on
// vlint flag_dangling_net_within_module on
wire daemon_starting_transaction;
wire daemon_ok_to_start_transaction;
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
// vlint flag_variable_assign_never_reference off
reg [DATA_WIDTH-1:0] csrbus_read_data_reg;
// vlint flag_variable_assign_never_reference on
// vlint flag_net_has_no_load on
// vlint flag_dangling_net_within_module on
// vlint flag_unsynthesizable_initial off
daemon_state = DAEMON_STATE_IDLE;
// N2- AT: daemon_rd = 1'b0;
// N2- AT: daemon_wr = 1'b0;
daemon_wr_data = {DATA_WIDTH{1'b0}};
daemon_addr = {ADDR_WIDTH{1'b0}};
// vlint flag_unsynthesizable_initial on
daemon_wr_data_reg <= {DATA_WIDTH{1'b0}};
daemon_addr_reg <= {ADDR_WIDTH{1'b0}};
daemon_csrbus_done_reg <= 1'b0;
daemon_rd_reg <= daemon_rd;
daemon_wr_reg <= daemon_wr;
daemon_wr_data_reg <= daemon_wr_data;
daemon_addr_reg <= daemon_addr;
daemon_rd_done <= daemon_rd_done_a1;
daemon_wr_done <= daemon_wr_done_a1;
daemon_csrbus_done_reg <= daemon_csrbus_done;
end // always @ (posedge clk)
csrbus_read_data_reg <= {DATA_WIDTH{1'b0}};
csrbus_valid_d <= csrbus_valid;
csrbus_read_data_reg <= csrbus_read_data;
daemon_state <= DAEMON_STATE_IDLE;
if (daemon_rd_reg & daemon_ok_to_start_transaction) // do daemon read
if (daemon_csrbus_done_reg)
daemon_state <= DAEMON_STATE_WAIT_RD; // zero cycles
daemon_state <= DAEMON_STATE_RD; // takes more than zero cycles
else if (daemon_wr_reg & daemon_ok_to_start_transaction)
if (daemon_csrbus_done_reg)
daemon_state <= DAEMON_STATE_WAIT_WR; // less than one cycle
daemon_state <= DAEMON_STATE_WR; // slow
end // if (daemon_wr_reg)
daemon_state <= DAEMON_STATE_IDLE; // nothing to do
end // else: !if(daemon_wr_reg)
end // case: DAEMON_STATE_IDLE
DAEMON_STATE_WR: // holds a write until finished
if (daemon_csrbus_done_reg) // done or timeout
daemon_state <= DAEMON_STATE_WAIT_WR;
else if (~daemon_wr_reg) // timeout
daemon_state <= DAEMON_STATE_WAIT_WR;
daemon_state <= DAEMON_STATE_WR; // wait
end // else: !if(~daemon_wr_reg)
if (daemon_csrbus_done_reg) // done
daemon_state <= DAEMON_STATE_WAIT_RD;
daemon_state <= DAEMON_STATE_WAIT_RD;
daemon_state <= DAEMON_STATE_RD; // wait
end // case: DAEMON_STATE_RD
if (daemon_wr_reg & daemon_ok_to_start_transaction)
daemon_state <= DAEMON_STATE_WR; // more than one cycle
else if (daemon_rd_reg & daemon_ok_to_start_transaction)
daemon_state <= DAEMON_STATE_RD; // read
daemon_state <= DAEMON_STATE_IDLE; // nothing to do, go back to idle
end // case: DAEMON_STATE_WAIT_RD
if (daemon_rd_reg & daemon_ok_to_start_transaction) // new rd?
daemon_state <= DAEMON_STATE_RD;
else if (daemon_wr_reg & daemon_ok_to_start_transaction) // new write?
daemon_state <= DAEMON_STATE_WR;
daemon_state <= DAEMON_STATE_IDLE; // nothing to do, go back to idle
end // case: DAEMON_STATE_WAIT_WR
daemon_state <= daemon_state;
endcase // case(daemon_state)
end // always @ (posedge clk)
assign daemon_rd_done_a1 =
(daemon_state == DAEMON_STATE_IDLE) &
daemon_ok_to_start_transaction
(daemon_state == DAEMON_STATE_RD) &
assign daemon_wr_done_a1 =
(daemon_state == DAEMON_STATE_IDLE) &
daemon_ok_to_start_transaction
(daemon_state == DAEMON_STATE_WR) &
assign daemon_rd_data = csrbus_read_data_reg;
assign daemon_ok_to_start_transaction = ~csrbus_valid_d;
wire good_starting_state = (daemon_state == DAEMON_STATE_IDLE);
assign daemon_starting_transaction = good_starting_state &
(daemon_rd_reg | daemon_wr_reg) &
daemon_ok_to_start_transaction;
// phaser split_component_by_output
always @(csrbus_valid or csrbus_wr or csrbus_wr_data or csrbus_addr or
daemon_csrbus_done or daemon_csrbus_mapped
// synopsys translate_off
daemon_transaction_in_progress
// synopsys translate_off
if (daemon_transaction_in_progress)
daemon_csrbus_addr = daemon_addr_reg;
daemon_csrbus_wr = (daemon_state == DAEMON_STATE_WR) |
(daemon_state == DAEMON_STATE_IDLE) &
daemon_csrbus_wr_data = daemon_wr_data_reg;
(daemon_state == DAEMON_STATE_IDLE) &
(daemon_rd_reg | daemon_wr_reg)
(daemon_state == DAEMON_STATE_WR) |
(daemon_state == DAEMON_STATE_RD);
end // if (daemon_state != DAEMON_STATE_IDLE)
daemon_csrbus_wr = csrbus_wr;
daemon_csrbus_wr_data = csrbus_wr_data;
daemon_csrbus_addr = csrbus_addr;
daemon_csrbus_valid = csrbus_valid;
csrbus_done = daemon_csrbus_done;
csrbus_mapped = daemon_csrbus_mapped;
end // else: !if(daemon_state != DAEMON_STATE_IDLE)
end // always @ (csrbus_wr...
assign daemon_transaction_in_progress =
// synopsys translate_off
((daemon_state != DAEMON_STATE_IDLE) | daemon_starting_transaction ) ? 1'b1 :