# ========== Copyright Header Begin ==========================================
# OpenSPARC T2 Processor File: user_cfg.scr
# Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
# 4150 Network Circle, Santa Clara, California 95054, U.S.A.
# * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
# For the avoidance of doubt, and except that if any non-GPL license
# choice is available it will apply instead, Sun elects to use only
# the General Public License version 2 (GPLv2) at this time for any
# software where a choice of GPL license versions is made
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# CA 95054 USA or visit www.sun.com if you need additional information or
# ========== Copyright Header End ============================================
source -echo -verbose $dv_root/design/sys/synopsys/script/project_sparc_cfg.scr
libs/cl/cl_dp1/cl_dp1.behV
libs/cl/cl_sc1/cl_sc1.behV
libs/clk/rtl/clkgen_rst_cmp.v
libs/clk/rtl/clkgen_rst_io.v
libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_rst_cmp_cust/rtl/n2_clk_rst_cmp_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_rst_io_cust/rtl/n2_clk_rst_io_cust.v
design/sys/iop/rst/rtl/rst.v
design/sys/iop/rst/rtl/rst_cmp_ctl.v
design/sys/iop/rst/rtl/rst_fsm_ctl.v
design/sys/iop/rst/rtl/rst_io_ctl.v
design/sys/iop/rst/rtl/rst_l1clkhdr_ctl_macro.v
design/sys/iop/rst/rtl/rst_spare_ctl_macro__num_1.v
design/sys/iop/rst/rtl/rst_spare_ctl_macro__num_4.v
design/sys/iop/rst/rtl/rst_spare_ctl_macro__num_6.v
design/sys/iop/rst/rtl/rst_ucbbusin4_ctl.v
design/sys/iop/rst/rtl/rst_ucbbusout4_ctl.v
design/sys/iop/rst/rtl/rst_ucbflow_ctl.v
set link_library [concat $link_library \
set dont_touch_modules {\
set compile_effort "medium"
set compile_flatten_all 1
set compile_no_new_cells_at_top_level false
set default_setup_skew 0.0
set default_hold_skew 0.0
set default_clk_transition 0.05
{ gclk 350.0 0.000 0.000 0.05} \
set enforce_input_fanout_one 0
set allow_outport_drive_innodes 1
set add_lockup_latch false
set scanenable_port global_shift_enable
set scanenable_pin test_stub_no_bist/se
set long_chain_so_0_net long_chain_so_0
set short_chain_so_0_net short_chain_so_0
set insert_extra_lockup_latch 0
set extra_lockup_latch_clk_list {}