// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: ifu_ftu_byp_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
ftp_sel_mbist_itb_cycle0,
ftp_sel_mbist_itb_cycle1,
ftp_sel_mbist_itb_cycle2,
ftp_sel_mbist_itb_cycle3,
ftp_sel_itlb_tag_cntx0_c,
ftp_sel_itlb_tag_cntx1_c,
ict_itlb_way_0_tag_f_rep0,
ict_itlb_way_1_tag_f_rep0,
ict_itlb_way_2_tag_f_rep0,
ict_itlb_way_3_tag_f_rep0,
ict_itlb_way_4_tag_f_rep0,
ict_itlb_way_5_tag_f_rep0,
ict_itlb_way_6_tag_f_rep0,
ict_itlb_way_7_tag_f_rep0,
wire by_pass_i0i1_f_reg_scanin;
wire by_pass_i0i1_f_reg_scanout;
wire [32:0] by_pass_instr_1_f;
wire [32:0] by_pass_instr_0_f;
wire by_pass_i2i3_f_reg_scanin;
wire by_pass_i2i3_f_reg_scanout;
wire [32:0] by_pass_instr_3_f;
wire [32:0] by_pass_instr_2_f;
wire by_pass_i0i1_c_reg_scanin;
wire by_pass_i0i1_c_reg_scanout;
wire [32:0] by_pass_instr_1_c;
wire [32:0] by_pass_instr_0_c;
wire by_pass_i2i3_c_reg_scanin;
wire by_pass_i2i3_c_reg_scanout;
wire [32:0] by_pass_instr_3_c;
wire [32:0] by_pass_instr_2_c;
wire [32:0] icd_bus_2_instr_reordered_c;
wire [32:0] icd_bus_3_instr_reordered_c;
wire asi_word_muxx_scanin;
wire asi_word_muxx_scanout;
wire asi_tag_mux_scanout;
wire asi_itlb_mux_scanin;
wire asi_itlb_mux_scanout;
wire itlb_bist_mux_scanin;
wire itlb_bist_mux_scanout;
wire [7:0] mbist_wdata_3_ff;
wire [31:0] itt_itd_cmp_data;
wire [65:0] tag_mbist_wdata;
wire [37:0] data_mbist_wdata;
wire itlb_w_bist_data_mux_scanin;
wire itlb_w_bist_data_mux_scanout;
wire [31:0] mbist_cmp_data_4_ff;
wire bist_data_stage_a_scanin;
wire bist_data_stage_a_scanout;
wire [7:0] mbist_wdata_2_ff;
wire bist_data_stage_b_scanin;
wire bist_data_stage_b_scanout;
wire [7:0] mbist_wdata_4_ff;
wire bist_data_stage_dup_b_scanin;
wire bist_data_stage_dup_b_scanout;
wire [7:0] mbist_wdata_4_dup_ff;
wire bist_data_stage_c_scanin;
wire bist_data_stage_c_scanout;
wire mbist_itb_read_en_2_ff;
wire mbist_itb_read_en_3_ff;
wire mbist_icd_read_en_2_ff;
wire mbist_icd_read_en_3_ff;
wire mbist_ict_read_en_2_ff;
wire mbist_itb_read_en_4_ff;
wire mbist_icd_read_en_4_ff;
wire mbist_ict_read_en_3_ff;
wire ict_mbist_fail_unq_l;
wire icd_mbist_fail_31_0_l;
wire mbist_it_fail_unq_l;
wire icd_mbist_fail_31_0;
wire sel_mbist_itb_cycle1_l;
wire sel_mbist_itb_cycle1_l_ff;
wire itb_data_for_cam_scanin;
wire itb_data_for_cam_scanout;
wire [5:0] itb_tte_data_1;
input tcu_se_scancollar_out ;
input tcu_pce_ov; // scan signals
input [7:0] agd_mbist_wdata_bf;
input ftp_mbi_icd_read_en_bf;
input ftp_mbi_ict_read_en_bf;
input itc_mbi_itb_read_en;
input [32:0] cmu_fill_inst0;
input [32:0] cmu_fill_inst1;
input [32:0] cmu_fill_inst2;
input [32:0] cmu_fill_inst3;
input [32:0] icd_bus_0_instr_c ;
input [32:0] icd_bus_1_instr_c ;
input [32:0] icd_bus_2_instr_c ;
input [32:0] icd_bus_3_instr_c ;
input [2:0] agc_instr_bp_sel_c ;
input [3:0] agc_asi_sel_word_c ;
input [7:0] agc_sel_tg_data_f;
input [29:0] ict_itlb_way_0_tag_f;
input [29:0] ict_itlb_way_1_tag_f;
input [29:0] ict_itlb_way_2_tag_f;
input [29:0] ict_itlb_way_3_tag_f;
input [29:0] ict_itlb_way_4_tag_f;
input [29:0] ict_itlb_way_5_tag_f;
input [29:0] ict_itlb_way_6_tag_f;
input [29:0] ict_itlb_way_7_tag_f;
input [37:0] itb_tte_data;
input [65:0] itb_tte_tag;
input itb_tte_data_parity;
input agc_itb_tag_perr_c;
input ftp_sel_mbist_itb_cycle0;
input ftp_sel_mbist_itb_cycle1;
input ftp_sel_mbist_itb_cycle2;
input ftp_sel_mbist_itb_cycle3;
input ftp_sel_itlb_tag_cntx0_c;
input ftp_sel_itlb_tag_cntx1_c;
input ftp_sel_itlb_data_c;
output [32:0] ftu_instr_0_c ;
output [32:0] ftu_instr_1_c ;
output [32:0] ftu_instr_2_c ;
output [32:0] ftu_instr_3_c ;
output [32:0] ic_rd_data ;
output [32:0] ic_dmo_rd_data;
output [29:0] tg_rd_data ;
output [63:0] it_rd_data ;
output ftu_mbi_icd_fail ;
output ftu_mbi_itb_fail ;
output ftu_mbi_tlb_data_cmp ;
output ftu_mbi_tlb_valid;
output [28:0] ict_itlb_way_0_tag_f_rep0;
output [28:0] ict_itlb_way_1_tag_f_rep0;
output [28:0] ict_itlb_way_2_tag_f_rep0;
output [28:0] ict_itlb_way_3_tag_f_rep0;
output [28:0] ict_itlb_way_4_tag_f_rep0;
output [28:0] ict_itlb_way_5_tag_f_rep0;
output [28:0] ict_itlb_way_6_tag_f_rep0;
output [28:0] ict_itlb_way_7_tag_f_rep0;
`define TAG_VA_47_28_HI 48
`define TAG_VA_47_28_LO 29
`define TAG_VA_27_22_HI 28
`define TAG_VA_27_22_LO 23
`define TAG_VA_21_16_HI 21
`define TAG_VA_21_16_LO 16
`define TAG_VA_15_13_HI 15
`define TAG_VA_15_13_LO 13
`define DATA_PA_39_28_HI 35
`define DATA_PA_39_28_LO 24
`define DATA_PA_27_22_HI 23
`define DATA_PA_27_22_LO 18
`define DATA_VA_27_22_V 17
`define DATA_PA_21_16_HI 16
`define DATA_PA_21_16_LO 11
`define DATA_VA_21_16_V 10
`define DATA_PA_15_13_HI 9
`define DATA_PA_15_13_LO 7
`define DATA_VA_15_13_V 6
// assign pce_ov = tcu_pce_ov;
// assign siclk = spc_aclk;
// assign soclk = spc_bclk;
assign test = tcu_dectest ;
ifu_ftu_byp_dp_buff_macro__dbuff_32x__stack_none__width_4 test_rep0 (
.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
.dout({se,pce_ov,siclk,soclk})
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
// Flop the by_pass instructions from CMU
///////////////////////////////////////////////////////////////////////
ifu_ftu_byp_dp_msff_macro__stack_66c__width_66 by_pass_i0i1_f_reg (
.scan_in(by_pass_i0i1_f_reg_scanin),
.scan_out(by_pass_i0i1_f_reg_scanout),
.din ( {cmu_fill_inst1[32:0], cmu_fill_inst0[32:0]}),
.dout( {by_pass_instr_1_f[32:0], by_pass_instr_0_f[32:0]} ),
//msff_macro by_pass_i1_f_reg (width=33,stack=34c) (
// .scan_in(by_pass_i1_f_reg_scanin),
// .scan_out(by_pass_i1_f_reg_scanout),
// .din ( cmu_fill_inst1[32:0]),
// .dout( by_pass_instr_1_f[32:0] ));
ifu_ftu_byp_dp_msff_macro__stack_66c__width_66 by_pass_i2i3_f_reg (
.scan_in(by_pass_i2i3_f_reg_scanin),
.scan_out(by_pass_i2i3_f_reg_scanout),
.din ( {cmu_fill_inst3[32:0], cmu_fill_inst2[32:0]}),
.dout( {by_pass_instr_3_f[32:0], by_pass_instr_2_f[32:0]} ),
//msff_macro by_pass_i3_f_reg (width=33,stack=34c) (
// .scan_in(by_pass_i3_f_reg_scanin),
// .scan_out(by_pass_i3_f_reg_scanout),
// .din ( cmu_fill_inst3[32:0]),
// .dout( by_pass_instr_3_f[32:0] ));
///////////////////////////////////////////////////////////////////////
// The following flops and muxes can be folded into the IC array. //
///////////////////////////////////////////////////////////////////////
ifu_ftu_byp_dp_msff_macro__stack_66c__width_66 by_pass_i0i1_c_reg (
.scan_in(by_pass_i0i1_c_reg_scanin),
.scan_out(by_pass_i0i1_c_reg_scanout),
.din ( {by_pass_instr_1_f[32:0],by_pass_instr_0_f[32:0]}),
.dout( {by_pass_instr_1_c[32:0],by_pass_instr_0_c[32:0]} ),
// msff_macro by_pass_i1_c_reg (width=33,stack=34c) (
// .scan_in(by_pass_i1_c_reg_scanin),
// .scan_out(by_pass_i1_c_reg_scanout),
// .din ( by_pass_instr_1_f[32:0]),
// .dout( by_pass_instr_1_c[32:0] ));
ifu_ftu_byp_dp_msff_macro__stack_66c__width_66 by_pass_i2i3_c_reg (
.scan_in(by_pass_i2i3_c_reg_scanin),
.scan_out(by_pass_i2i3_c_reg_scanout),
.din ( {by_pass_instr_3_f[32:0],by_pass_instr_2_f[32:0]}),
.dout( {by_pass_instr_3_c[32:0],by_pass_instr_2_c[32:0]} ),
// msff_macro by_pass_i3_c_reg (width=33,stack=34c) (
// .scan_in(by_pass_i3_c_reg_scanin),
// .scan_out(by_pass_i3_c_reg_scanout),
// .din ( by_pass_instr_3_f[32:0]),
// .dout( by_pass_instr_3_c[32:0] ));
ifu_ftu_byp_dp_buff_macro__dbuff_48x__width_1 tst_mux_rep0 (
.dout( tcu_muxtest_rep0 ));
ifu_ftu_byp_dp_mux_macro__mux_pgpe__ports_4__stack_66c__width_66 inst_01_bp_mux (
.din0( {icd_bus_1_instr_c[32:0],icd_bus_0_instr_c[32:0]}),
.din1( {by_pass_instr_1_f[32:0],by_pass_instr_0_f[32:0]}),
.din2( {by_pass_instr_1_c[32:0],by_pass_instr_0_c[32:0]}),
.din3( {cmu_fill_inst1[32:0],cmu_fill_inst0[32:0]}),
.muxtst(tcu_muxtest_rep0),
.sel0( agc_instr_bp_sel_c[0]),
.sel1( agc_instr_bp_sel_c[1]),
.sel2( agc_instr_bp_sel_c[2]),
.dout( {ftu_instr_1_c[32:0],ftu_instr_0_c[32:0]} ),
//mux_macro inst_1_bp_mux (width=33,ports=5,mux=aonpe,stack=34c) (
// .din0( icd_bus_1_instr_c[32:0]),
// .din1( 33'h001000000),
// .din2( cmu_fill_inst1[32:0]),
// .din3( by_pass_instr_1_f[32:0]),
// .din4( by_pass_instr_1_c[32:0]),
// .sel0( agc_instr_bp_sel_c[0]),
// .sel1( agc_instr_bp_sel_c[1]),
// .sel2( agc_instr_bp_sel_c[2]),
// .sel3( agc_instr_bp_sel_c[3]),
// .sel4( agc_instr_bp_sel_c[4]),
// .dout( ftu_instr_1_c[32:0] ));
ifu_ftu_byp_dp_buff_macro__dbuff_48x__width_1 tst_mux_rep1 (
.dout( tcu_muxtest_rep1 ));
ifu_ftu_byp_dp_mux_macro__dmux_8x__mux_pgpe__ports_4__stack_66c__width_66 inst_23_bp_mux (
.din0( {icd_bus_3_instr_c[32:0],icd_bus_2_instr_c[32:0]}),
.din1( {by_pass_instr_3_f[32:0],by_pass_instr_2_f[32:0]}),
.din2( {by_pass_instr_3_c[32:0],by_pass_instr_2_c[32:0]}),
.din3( {cmu_fill_inst3[32:0],cmu_fill_inst2[32:0]}),
.muxtst(tcu_muxtest_rep1),
.sel0( agc_instr_bp_sel_c[0]),
.sel1( agc_instr_bp_sel_c[1]),
.sel2( agc_instr_bp_sel_c[2]),
.dout( {ftu_instr_3_c[32:0],ftu_instr_2_c[32:0]} ),
// buff_macro icd_bus_01_instr_rep0 (width=66,stack=66c,dbuff=48x) (
// .din ({icd_bus_1_instr_c[32:0],icd_bus_0_instr_c[32:0]} ),
// .dout({icd_bus_1_instr_c_rep0[32:0], icd_bus_0_instr_c_rep0[32:0]})
// buff_macro icd_bus_23_instr_rep0 (width=66,stack=66c,dbuff=48x) (
// .din ({icd_bus_3_instr_c[32:0], icd_bus_2_instr_c[32:0] } ),
// .dout({icd_bus_3_instr_c_rep0[32:0], icd_bus_2_instr_c_rep0[32:0]})
//mux_macro inst_3_bp_mux (width=33,ports=5,mux=aonpe,stack=34c) (
// .din0( icd_bus_3_instr_c[32:0]),
// .din1( 33'h001000000),
// .din2( cmu_fill_inst3[32:0]),
// .din3( by_pass_instr_3_f[32:0]),
// .din4( by_pass_instr_3_c[32:0]),
// .sel0( agc_instr_bp_sel_c[0]),
// .sel1( agc_instr_bp_sel_c[1]),
// .sel2( agc_instr_bp_sel_c[2]),
// .sel3( agc_instr_bp_sel_c[3]),
// .sel4( agc_instr_bp_sel_c[4]),
// .dout( ftu_instr_3_c[32:0] ));
assign icd_bus_2_instr_reordered_c[32:0] = {icd_bus_2_instr_c[0], icd_bus_2_instr_c[1] ,icd_bus_2_instr_c[2] ,icd_bus_2_instr_c[3],
icd_bus_2_instr_c[4], icd_bus_2_instr_c[5] ,icd_bus_2_instr_c[6] ,icd_bus_2_instr_c[7],
icd_bus_2_instr_c[8], icd_bus_2_instr_c[9] ,icd_bus_2_instr_c[10],icd_bus_2_instr_c[11],
icd_bus_2_instr_c[12], icd_bus_2_instr_c[13],icd_bus_2_instr_c[14],icd_bus_2_instr_c[15],
icd_bus_2_instr_c[16], icd_bus_2_instr_c[17],icd_bus_2_instr_c[18],icd_bus_2_instr_c[19],
icd_bus_2_instr_c[20], icd_bus_2_instr_c[21],icd_bus_2_instr_c[22],icd_bus_2_instr_c[23],
icd_bus_2_instr_c[24], icd_bus_2_instr_c[25],icd_bus_2_instr_c[26],icd_bus_2_instr_c[27],
icd_bus_2_instr_c[28], icd_bus_2_instr_c[29],icd_bus_2_instr_c[30],icd_bus_2_instr_c[31],
assign icd_bus_3_instr_reordered_c[32:0] = {icd_bus_3_instr_c[0], icd_bus_3_instr_c[1] ,icd_bus_3_instr_c[2] ,icd_bus_3_instr_c[3],
icd_bus_3_instr_c[4], icd_bus_3_instr_c[5] ,icd_bus_3_instr_c[6] ,icd_bus_3_instr_c[7],
icd_bus_3_instr_c[8], icd_bus_3_instr_c[9] ,icd_bus_3_instr_c[10],icd_bus_3_instr_c[11],
icd_bus_3_instr_c[12], icd_bus_3_instr_c[13],icd_bus_3_instr_c[14],icd_bus_3_instr_c[15],
icd_bus_3_instr_c[16], icd_bus_3_instr_c[17],icd_bus_3_instr_c[18],icd_bus_3_instr_c[19],
icd_bus_3_instr_c[20], icd_bus_3_instr_c[21],icd_bus_3_instr_c[22],icd_bus_3_instr_c[23],
icd_bus_3_instr_c[24], icd_bus_3_instr_c[25],icd_bus_3_instr_c[26],icd_bus_3_instr_c[27],
icd_bus_3_instr_c[28], icd_bus_3_instr_c[29],icd_bus_3_instr_c[30],icd_bus_3_instr_c[31],
ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_4__stack_34c__width_33 asi_word_muxx (
.scan_in(asi_word_muxx_scanin),
.scan_out(asi_word_muxx_scanout),
.se ( tcu_se_scancollar_out ) ,
.din0( icd_bus_0_instr_c[32:0]),
.din1( icd_bus_1_instr_c[32:0]),
.din2( icd_bus_2_instr_reordered_c[32:0]),
.din3( icd_bus_3_instr_reordered_c[32:0]),
.sel0( agc_asi_sel_word_c[0]),
.sel1( agc_asi_sel_word_c[1]),
.sel2( agc_asi_sel_word_c[2]),
.sel3( agc_asi_sel_word_c[3]),
.dout( ic_rd_data[32:0] ),
ifu_ftu_byp_dp_buff_macro__dbuff_16x__rep_1__stack_34c__width_33 ic_dmo_rd_data_buf (
.din (ic_rd_data[32:0] ),
.dout(ic_dmo_rd_data[32:0])
ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_0_tag_buff_rep0 (
.din (ict_itlb_way_0_tag_f[28:0] ),
.dout(ict_itlb_way_0_tag_f_rep0[28:0])
ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_1_tag_buff_rep0 (
.din (ict_itlb_way_1_tag_f[28:0] ),
.dout(ict_itlb_way_1_tag_f_rep0[28:0])
ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_2_tag_buff_rep0 (
.din (ict_itlb_way_2_tag_f[28:0] ),
.dout(ict_itlb_way_2_tag_f_rep0[28:0])
ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_3_tag_buff_rep0 (
.din (ict_itlb_way_3_tag_f[28:0] ),
.dout(ict_itlb_way_3_tag_f_rep0[28:0])
ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_4_tag_buff_rep0 (
.din (ict_itlb_way_4_tag_f[28:0] ),
.dout(ict_itlb_way_4_tag_f_rep0[28:0])
ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_5_tag_buff_rep0 (
.din (ict_itlb_way_5_tag_f[28:0] ),
.dout(ict_itlb_way_5_tag_f_rep0[28:0])
ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_6_tag_buff_rep0 (
.din (ict_itlb_way_6_tag_f[28:0] ),
.dout(ict_itlb_way_6_tag_f_rep0[28:0])
ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 way_7_tag_buff_rep0 (
.din (ict_itlb_way_7_tag_f[28:0] ),
.dout(ict_itlb_way_7_tag_f_rep0[28:0])
ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_8__stack_32c__width_30 asi_tag_mux (
.scan_in(asi_tag_mux_scanin),
.scan_out(asi_tag_mux_scanout),
.se ( tcu_se_scancollar_out ) ,
.din0( ict_itlb_way_0_tag_f[29:0]),
.din1( ict_itlb_way_1_tag_f[29:0]),
.din2( ict_itlb_way_2_tag_f[29:0]),
.din3( ict_itlb_way_3_tag_f[29:0]),
.din4( ict_itlb_way_4_tag_f[29:0]),
.din5( ict_itlb_way_5_tag_f[29:0]),
.din6( ict_itlb_way_6_tag_f[29:0]),
.din7( ict_itlb_way_7_tag_f[29:0]),
.sel0( agc_sel_tg_data_f[0]),
.sel1( agc_sel_tg_data_f[1]),
.sel2( agc_sel_tg_data_f[2]),
.sel3( agc_sel_tg_data_f[3]),
.sel4( agc_sel_tg_data_f[4]),
.sel5( agc_sel_tg_data_f[5]),
.sel6( agc_sel_tg_data_f[6]),
.sel7( agc_sel_tg_data_f[7]),
.dout( tg_rd_data[29:0] ),
// msff_macro itb_cam_hit_reg (width=4) (
// .scan_in(itb_cam_hit_reg_scanin),
// .scan_out(itb_cam_hit_reg_scanout),
// agc_itb_tag_perr_c}) ,
ifu_ftu_byp_dp_msff_macro__minbuff_1__mux_aonpe__ports_4__stack_64c__width_64 asi_itlb_mux (
.scan_in(asi_itlb_mux_scanin),
.scan_out(asi_itlb_mux_scanout),
.se ( tcu_se_scancollar_out ) ,
.din0 ({itb_tte_tag[`TAG_PID_HI:`TAG_PID_LO], // PID
itb_tte_tag[`TAG_REAL], // REAL
itb_tte_data[`TAG_PARITY], // PARITY
itb_tte_tag[`TAG_VA_47_28_HI:`TAG_VA_27_22_LO],
itb_tte_tag[`TAG_VA_21_16_HI:`TAG_VA_21_16_LO],
itb_tte_tag[`TAG_VA_15_13_HI:`TAG_VA_15_13_LO],
itb_tte_tag[`TAG_CNTX0_HI:`TAG_CNTX0_LO] // context
.din1 ({itb_tte_tag[`TAG_PID_HI:`TAG_PID_LO], // PID
itb_tte_tag[`TAG_REAL], // REAL
itb_tte_data[`TAG_PARITY], // PARITY
itb_tte_tag[`TAG_VA_47_28_HI:`TAG_VA_27_22_LO],
itb_tte_tag[`TAG_VA_21_16_HI:`TAG_VA_21_16_LO],
itb_tte_tag[`TAG_VA_15_13_HI:`TAG_VA_15_13_LO],
itb_tte_tag[`TAG_CNTX1_HI:`TAG_CNTX1_LO] // context
.din2 ({itb_tte_tag[`TAG_V], // V
itb_tte_data[`DATA_NFO], // NFO
itb_tte_data[`DATA_PARITY], // PARITY
itb_tte_data[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], // PA
itb_tte_data[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO],
itb_tte_data[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO],
itb_tte_data[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO],
itb_tte_data[`DATA_IE], // IE
itb_tte_data[`DATA_E], // E
itb_tte_data[`DATA_CP], // CP
itb_tte_data[`DATA_P], // P
itb_tte_data[`DATA_W], // W
itb_tte_data[`DATA_VA_27_22_V], // SZ
itc_itb_data_sz_1,itb_tte_data[`DATA_VA_15_13_V] // SZ
.din3( {itb_cam_hit_c, itb_itb_mhit_c, agc_itb_tag_perr_c, itb_tte_data_parity, 20'b0,ftu_paddr[39:13],13'b0}),
.sel0( ftp_sel_itlb_tag_cntx0_c),
.sel1( ftp_sel_itlb_tag_cntx1_c),
.sel2( ftp_sel_itlb_data_c),
.sel3( ftp_sel_itlb_pa_c),
.dout( it_rd_data[63:0] ),
// mbist_wdata[68:0] = { mbist_wdata_bf[1:0], mbist_wdata_bf[7:0],mbist_wdata_bf[7:6], // [68:56]
// mbist_wdata_bf[4:2], // [55:53]
// mbist_wdata_bf[0],{3{mbist_wdata_bf[7:0]}},mbist_wdata_bf[7], // [51:26]
// mbist_wdata_bf[6:0], // [24:18]
// mbist_wdata_bf[7:5], // [16:14]
// mbist_wdata_bf[4:0],mbist_wdata_bf[7:0]}; // [12:0]
// data_mbist_wdata[37:0] = { mbist_wdata_bf[4:0],mbist_wdata_bf[7:1], // [37:26]
// mbist_wdata_bf[0],mbist_wdata_bf[7:2], // [24:18]
// mbist_wdata_bf[0], mbist_wdata_bf[7:6], // [16:14]
// mbist_wdata_bf[4:0],mbist_wdata_bf[7:0]}; // [12:0]
// ifu_agd_pc_bf[47:13] = ({itd_tag[51:32],
// tte_tag[65:0] = ({itd_tag[68:52], // [65:49] ---> itd_tag[68:52]--> mbist_wdata_bf[2:0],
// mbist_wdata_bf[7:0],mbist_data[7:6],mbist_data[4:2],1'b0
// ifu_agd_pc_bf[47:22], // [48:23] ---> itd_tag[51:26]--> mbist_data[0],{3{mbist_wdata_bf[7:0]}},mbist_wdata_bf[7]
// itd_tag[24], // [22] ---> itd_tag[24]-----> mbist_data[6]
// ifu_agd_pc_bf[21:16], // [21:16] ---> itd_tag[23:18]--> mbist_data[5:0]
// ifu_agd_pc_bf[15:13], // [15:13] ---> itd_tag[16:14]--> mbist_data[7:5]
// itd_tag[12:0]}), // [12:0] ---> itd_tag[12:0]---> mbist_data[4:0],mbist_data[7:0]
ifu_ftu_byp_dp_msff_macro__minbuff_1__mux_aonpe__ports_4__stack_32c__width_32 itlb_bist_mux (
.scan_in(itlb_bist_mux_scanin),
.scan_out(itlb_bist_mux_scanout),
.se ( tcu_se_scancollar_out ) ,
.din0 ( itb_tte_tag[31:0]),
.din1 ( itb_tte_tag[63:32]),
.din2 ( itb_tte_data[31:0] ),
.din3 ( {mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:1],itb_tte_u_bit,
itb_tte_tag[65:64],itb_tte_data[37:32]} ),
.sel0 ( ftp_sel_mbist_itb_cycle0),
.sel1 ( ftp_sel_mbist_itb_cycle1),
.sel2 ( ftp_sel_mbist_itb_cycle2),
.sel3 ( ftp_sel_mbist_itb_cycle3),
.dout( itt_itd_cmp_data[31:0] ),
assign tag_mbist_wdata[65:0] = ({mbist_wdata_3_ff[1:0],mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:5],mbist_wdata_3_ff[4:2],1'b0, // [65:49]
mbist_wdata_3_ff[0],{3{mbist_wdata_3_ff[7:0]}},mbist_wdata_3_ff[7], // [48:23]
mbist_wdata_3_ff[6], // [22]
mbist_wdata_3_ff[5:0], // [21:16]
mbist_wdata_3_ff[7:5], // [15:13]
mbist_wdata_3_ff[4:0],mbist_wdata_3_ff[7:0] }) ; // [12:0]
assign data_mbist_wdata[37:0] = { mbist_wdata_3_ff[5:0],mbist_wdata_3_ff[7:2], // [37:26]
mbist_wdata_3_ff[1], // [25]
mbist_wdata_3_ff[0],mbist_wdata_3_ff[7:2], // [24:18]
mbist_wdata_3_ff[1], // [17]
mbist_wdata_3_ff[0], mbist_wdata_3_ff[7:6], // [16:14]
mbist_wdata_3_ff[5], // [13]
mbist_wdata_3_ff[4:0],mbist_wdata_3_ff[7:0]}; // [12:0]
ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_4__stack_32c__width_32 itlb_w_bist_data_mux (
.scan_in(itlb_w_bist_data_mux_scanin),
.scan_out(itlb_w_bist_data_mux_scanout),
.se ( tcu_se_scancollar_out ) ,
.din0 ( tag_mbist_wdata[31:0]),
.din1 ( tag_mbist_wdata[63:32]),
.din2 ( data_mbist_wdata[31:0] ),
.din3 ( {mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0],
tag_mbist_wdata[65:64],data_mbist_wdata[37:32]} ),
.sel0 ( ftp_sel_mbist_itb_cycle0),
.sel1 ( ftp_sel_mbist_itb_cycle1),
.sel2 ( ftp_sel_mbist_itb_cycle2),
.sel3 ( ftp_sel_mbist_itb_cycle3),
.dout( mbist_cmp_data_4_ff[31:0] ),
ifu_ftu_byp_dp_msff_macro__stack_16c__width_16 bist_data_stage_a (
.scan_in(bist_data_stage_a_scanin),
.scan_out(bist_data_stage_a_scanout),
.din ({agd_mbist_wdata_bf[7:0],mbist_wdata_2_ff[7:3],mbi_cambist_run,mbi_addr[5:4]}),
.dout ({mbist_wdata_2_ff[7:0], mbist_wdata_3_ff[7:3],cambist_run_ff,mbist_addr_1[5:4]}),
ifu_ftu_byp_dp_msff_macro__stack_16c__width_15 bist_data_stage_b (
.scan_in(bist_data_stage_b_scanin),
.scan_out(bist_data_stage_b_scanout),
.din ({mbist_wdata_2_ff[2:0],mbist_wdata_3_ff[7:0],mbi_addr[3:0] }),
.dout ({mbist_wdata_3_ff[2:0],mbist_wdata_4_ff[7:0],mbist_addr_1[3:0] } ),
ifu_ftu_byp_dp_msff_macro__stack_16c__width_14 bist_data_stage_dup_b (
.scan_in(bist_data_stage_dup_b_scanin),
.scan_out(bist_data_stage_dup_b_scanout),
.din ({mbist_wdata_3_ff[7:0], mbist_addr_1[5:0] }),
.dout ({mbist_wdata_4_dup_ff[7:0], mbist_addr_2[5:0] } ),
ifu_ftu_byp_dp_msff_macro__stack_16c__width_16 bist_data_stage_c (
.scan_in(bist_data_stage_c_scanin),
.scan_out(bist_data_stage_c_scanout),
.din ({ mbist_itb_read_en_2_ff,mbist_itb_read_en_3_ff,
it_mbist_fail_q ,ftp_mbi_icd_read_en_bf, mbist_icd_read_en_2_ff,
mbist_icd_read_en_3_ff, ict_mbist_fail_q,icd_mbist_fail_q,
itc_mbi_itb_read_en,ftp_mbi_ict_read_en_bf,mbist_ict_read_en_2_ff,mbist_addr_3[4:0] }),
.dout ({ mbist_itb_read_en_3_ff, mbist_itb_read_en_4_ff,
ftu_mbi_itb_fail, mbist_icd_read_en_2_ff , mbist_icd_read_en_3_ff,
mbist_icd_read_en_4_ff, ftu_mbi_ict_fail,ftu_mbi_icd_fail,
mbist_itb_read_en_2_ff,mbist_ict_read_en_2_ff,mbist_ict_read_en_3_ff,mbist_addr_4[4:0]}),
// mux_macro cmp_data_mux (width=33,ports=2,mux=aonpe,stack=34c) (
// .din0( {mbist_wdata_3_ff[0],mbist_wdata_3_ff[7:6],tg_rd_data[29:0]}),
// .din1( ic_rd_data[32:0]),
// .sel0( mbist_ict_read_en_3_ff),
// .sel1( mbist_icd_read_en_4_ff),
// .dout( ict_icd_cmp_data[32:0] ));
ifu_ftu_byp_dp_cmp_macro__dcmp_8x__width_32 ict_fail_detect (
.dout( ict_mbist_fail_unq_l),
.din0( {mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0],mbist_wdata_3_ff[7:0]}),
.din1( {mbist_wdata_3_ff[7:6],tg_rd_data[29:0]})
// mux_macro itb_cmp_data_mux_1 (width=16,ports=2,mux=aope,stack=16c) (
// .din0( {mbist_wdata_4_ff[7:2],it_rd_data[57:48]}),
// .din1( it_rd_data[31:16]),
// .sel0( cmpsel_4_ff[0]),
// .dout( itt_itd_cmp_data[31:16] ));
// mux_macro itb_cmp_data_mux_0 (width=16,ports=2,mux=aope,stack=16c) (
// .din0( it_rd_data[47:32]),
// .din1( it_rd_data[15:0]),
// .sel0( cmpsel_4_ff[0]),
// .dout( itt_itd_cmp_data[15:0] ));
ifu_ftu_byp_dp_cmp_macro__dcmp_8x__width_32 icd_fail_detect (
.dout( icd_mbist_fail_31_0_l),
.din0( {mbist_wdata_4_dup_ff[7:0],mbist_wdata_4_dup_ff[7:0],mbist_wdata_4_dup_ff[7:0],mbist_wdata_4_dup_ff[7:0]}),
ifu_ftu_byp_dp_xor_macro__ports_2__width_1 icd_fail_detect_xnor (
.din0( mbist_wdata_4_ff[0]) ,
.dout( icd_mbist_fail_32)) ;
ifu_ftu_byp_dp_cmp_macro__dcmp_8x__width_32 it_fail_detect (
.dout( mbist_it_fail_unq_l),
.din0( mbist_cmp_data_4_ff[31:0]),
.din1( itt_itd_cmp_data[31:0])
ifu_ftu_byp_dp_inv_macro__width_5 ict_fail_macro (
.dout( {ict_mbist_fail_unq,icd_mbist_fail_31_0, mbist_it_fail_unq,cambist_run_ff_l,sel_mbist_itb_cycle1_l}),
.din( {ict_mbist_fail_unq_l,icd_mbist_fail_31_0_l, mbist_it_fail_unq_l,cambist_run_ff,ftp_sel_mbist_itb_cycle1})
ifu_ftu_byp_dp_or_macro__ports_2__width_1 icd_final_fail (
.din0 (icd_mbist_fail_32),
.din1 (icd_mbist_fail_31_0) ,
.dout (icd_mbist_fail_unq)) ;
// or_macro read_or_macro (width=2,ports=2) (
// .dout( {mbist_read_en,mbist_it_read_en}),
// .din0( {mbist_ict_read_en_3_ff,1'b0}),
// .din1( {mbist_icd_read_en_4_ff,mbist_itb_read_en_3_ff})
// assign mbist_it_read_en = mbist_itb_read_en_4_ff ;
ifu_ftu_byp_dp_and_macro__width_5 fail_qual (
.dout( {ict_mbist_fail_q,icd_mbist_fail_q,it_mbist_fail_q,mbist_it_read_en,rbit_modify_unused}),
.din0( {ict_mbist_fail_unq,icd_mbist_fail_unq,mbist_it_fail_unq,cambist_run_ff_l,sel_mbist_itb_cycle1_l_ff}),
.din1( {mbist_ict_read_en_3_ff,mbist_icd_read_en_4_ff,mbist_it_read_en,mbist_itb_read_en_4_ff,mbist_wdata_4_ff[1]})) ;
// assign ftu_mbi_icd_fail = ftu_mbi_ict_fail ;
ifu_ftu_byp_dp_msff_macro__minbuff_1__stack_16c__width_16 itb_data_for_cam (
.scan_in(itb_data_for_cam_scanin),
.scan_out(itb_data_for_cam_scanout),
.din ({itb_tte_data[5:0] , itb_tte_u_bit , itb_tte_tag[`TAG_V],mbist_addr_2[5:0],sel_mbist_itb_cycle1_l,mbist_addr_3[5]}),
.dout ({itb_tte_data_1[5:0], ftu_mbi_tlb_used, ftu_mbi_tlb_valid,mbist_addr_3[5:0] , sel_mbist_itb_cycle1_l_ff,mbist_addr_4[5]} ),
ifu_ftu_byp_dp_cmp_macro__width_8 cambist_cmp (
.din0 ({2'b0,mbist_addr_4[5:0]}),
.din1 ({2'b0,itb_tte_data_1[5:0]}),
.dout (ftu_mbi_tlb_data_cmp)
// assign se = tcu_scan_en ;
assign by_pass_i0i1_f_reg_scanin = scan_in ;
assign by_pass_i2i3_f_reg_scanin = by_pass_i0i1_f_reg_scanout;
assign by_pass_i0i1_c_reg_scanin = by_pass_i2i3_f_reg_scanout;
assign by_pass_i2i3_c_reg_scanin = by_pass_i0i1_c_reg_scanout;
assign asi_word_muxx_scanin = by_pass_i2i3_c_reg_scanout;
assign asi_tag_mux_scanin = asi_word_muxx_scanout ;
assign asi_itlb_mux_scanin = asi_tag_mux_scanout ;
assign itlb_bist_mux_scanin = asi_itlb_mux_scanout ;
assign itlb_w_bist_data_mux_scanin = itlb_bist_mux_scanout ;
assign bist_data_stage_a_scanin = itlb_w_bist_data_mux_scanout;
assign bist_data_stage_b_scanin = bist_data_stage_a_scanout;
assign bist_data_stage_dup_b_scanin = bist_data_stage_b_scanout;
assign bist_data_stage_c_scanin = bist_data_stage_dup_b_scanout;
assign itb_data_for_cam_scanin = bist_data_stage_c_scanout;
assign scan_out = itb_data_for_cam_scanout ;
module ifu_ftu_byp_dp_buff_macro__dbuff_32x__stack_none__width_4 (
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_msff_macro__stack_66c__width_66 (
.so({so[64:0],scan_out}),
module ifu_ftu_byp_dp_buff_macro__dbuff_48x__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_mux_macro__mux_pgpe__ports_4__stack_66c__width_66 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_mux_macro__dmux_8x__mux_pgpe__ports_4__stack_66c__width_66 (
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_4__stack_34c__width_33 (
cl_dp1_muxbuff4_8x c1_0 (
.so({so[31:0],scan_out}),
module ifu_ftu_byp_dp_buff_macro__dbuff_16x__rep_1__stack_34c__width_33 (
module ifu_ftu_byp_dp_buff_macro__dbuff_48x__rep_1__stack_30c__width_29 (
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_8__stack_32c__width_30 (
cl_dp1_muxbuff8_8x c1_0 (
.so({so[28:0],scan_out}),
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_msff_macro__minbuff_1__mux_aonpe__ports_4__stack_64c__width_64 (
cl_dp1_muxbuff4_8x c1_0 (
.so({so[62:0],scan_out}),
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_msff_macro__minbuff_1__mux_aonpe__ports_4__stack_32c__width_32 (
cl_dp1_muxbuff4_8x c1_0 (
.so({so[30:0],scan_out}),
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_msff_macro__mux_aonpe__ports_4__stack_32c__width_32 (
cl_dp1_muxbuff4_8x c1_0 (
.so({so[30:0],scan_out}),
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_msff_macro__stack_16c__width_16 (
.so({so[14:0],scan_out}),
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_msff_macro__stack_16c__width_15 (
.so({so[13:0],scan_out}),
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_msff_macro__stack_16c__width_14 (
.so({so[12:0],scan_out}),
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module ifu_ftu_byp_dp_cmp_macro__dcmp_8x__width_32 (
// xor macro for ports = 2,3
module ifu_ftu_byp_dp_xor_macro__ports_2__width_1 (
module ifu_ftu_byp_dp_inv_macro__width_5 (
// or macro for ports = 2,3
module ifu_ftu_byp_dp_or_macro__ports_2__width_1 (
// and macro for ports = 2,3,4
module ifu_ftu_byp_dp_and_macro__width_5 (
// any PARAMS parms go into naming of macro
module ifu_ftu_byp_dp_msff_macro__minbuff_1__stack_16c__width_16 (
.so({so[14:0],scan_out}),
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module ifu_ftu_byp_dp_cmp_macro__width_8 (