// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: lsu_cid_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
wire [145:0] cpq_read_data;
wire [145:0] cpq_mx_data;
wire [145:0] cpq_data_out;
wire [144:129] cid_pkt_data_e;
wire dff_cmp_data_scanin;
wire dff_cmp_data_scanout;
wire [7:0] bist_cmp_data;
wire [72:0] fifo_cmp_data;
input [145:0] cpq_rdata; // Read data from CPQ
input [145:0] cpx_spc_data_cx; // CPX packet
output [127:0] cid_fill_data_e; // Fill data for dcache
output [4:0] cid_pkt_type;
output [2:0] cid_tid_unbuf;
output [10:3] cid_st_addr; // Store update address
output [15:0] cid_st_vector; // Store invalidate vector
output [7:0] cid_st_bmask; // Store byte mask
output [1:0] cid_st_way; // Dcache way to which store data gets written
output [17:0] cid_inv_vec; // Invalidation data
output [10:6] cid_inv_index; // Cache index for invalidation
output [145:0] cid_cpq_wdata;
output [4:0] cid_d1_rtntyp;
output [2:0] cid_d1_cpuid;
output [1:0] cid_d1_inval;
// Flopped versions to IFU
output [127:0] lsu_cpx_data;
output [17:0] lsu_cpx_cpkt;
input tcu_pce_ov; // scan signals
input tcu_se_scancollar_out;
input [7:0] bist_wdata_1;
lsu_cid_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 (
.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
.dout({se,pce_ov,siclk,soclk})
assign in_data[145:0] = cpx_spc_data_cx[145:0];
lsu_cid_dp_msff_macro__stack_64c__width_64 dff_d1_0 (
.scan_in(dff_d1_0_scanin),
.scan_out(dff_d1_0_scanout),
.se (tcu_se_scancollar_out),
lsu_cid_dp_msff_macro__stack_64c__width_64 dff_d1_1 (
.scan_in(dff_d1_1_scanin),
.scan_out(dff_d1_1_scanout),
.se (tcu_se_scancollar_out),
lsu_cid_dp_msff_macro__stack_10l__width_9 dff_d1_2 (
.scan_in(dff_d1_2_scanin),
.scan_out(dff_d1_2_scanout),
.se (tcu_se_scancollar_out),
.din ({in_data[128],in_data[130],in_data[132],in_data[134],in_data[136],in_data[138],
in_data[140],in_data[142],in_data[144]}),
.dout ({data_d1[128],data_d1[130],data_d1[132],data_d1[134],data_d1[136],data_d1[138],
data_d1[140],data_d1[142],data_d1[144]}),
lsu_cid_dp_msff_macro__stack_10l__width_9 dff_d1_3 (
.scan_in(dff_d1_3_scanin),
.scan_out(dff_d1_3_scanout),
.se (tcu_se_scancollar_out),
.din ({in_data[129],in_data[131],in_data[133],in_data[135],in_data[137],in_data[139],
in_data[141],in_data[143],in_data[145]}),
.dout ({data_d1[129],data_d1[131],data_d1[133],data_d1[135],data_d1[137],data_d1[139],
data_d1[141],data_d1[143],data_d1[145]}),
assign cid_d1_rtntyp[4:0] = data_d1[145:141];
assign cid_d1_tid[2:0] = data_d1[136:134];
assign cid_d1_wv = data_d1[133];
assign cid_d1_pref = data_d1[128];
assign cid_d1_rmo = lsu_cpx_data[125];
assign cid_d1_cpuid[2:0] = lsu_cpx_data[120:118];
assign cid_d1_inval[1:0] = lsu_cpx_data[124:123];
lsu_cid_dp_buff_macro__stack_64c__width_64 d1_data_buf_0 (
.dout (lsu_cpx_data[63:0])
lsu_cid_dp_buff_macro__stack_64c__width_64 d1_data_buf_1 (
.dout (lsu_cpx_data[127:64])
lsu_cid_dp_buff_macro__stack_10l__width_9 d1_data_buf_2 (
.din ({data_d1[128], data_d1[130], data_d1[132], data_d1[134], data_d1[136],
data_d1[138], data_d1[140], data_d1[142], data_d1[144]}),
.dout ({lsu_cpx_cpkt[0],lsu_cpx_cpkt[2],lsu_cpx_cpkt[4],lsu_cpx_cpkt[6],lsu_cpx_cpkt[8],
lsu_cpx_cpkt[10],lsu_cpx_cpkt[12],lsu_cpx_cpkt[15],lsu_cpx_cpkt[17]})
lsu_cid_dp_buff_macro__stack_10l__width_9 d1_data_buf_3 (
.din ({data_d1[129], data_d1[131], data_d1[133], data_d1[135],
data_d1[137], data_d1[139], data_d1[141], data_d1[143], data_d1[145]}),
.dout ({lsu_cpx_cpkt[1],lsu_cpx_cpkt[3],lsu_cpx_cpkt[5],lsu_cpx_cpkt[7],
lsu_cpx_cpkt[9],lsu_cpx_cpkt[11],lsu_cpx_cpkt[14],lsu_cpx_cpkt[16],lsu_cpx_valid})
assign lsu_cpx_cpkt[13] = 1'b0;
lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_64c__width_64 cpq_data_buf_0 (
.dout (cpq_read_data[63:0])
lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_64c__width_64 cpq_data_buf_1 (
.din (cpq_rdata[127:64]),
.dout (cpq_read_data[127:64])
lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_10l__width_9 cpq_data_buf_2 (
.din ({cpq_rdata[128],cpq_rdata[130],cpq_rdata[132],cpq_rdata[134],cpq_rdata[136],cpq_rdata[138],
cpq_rdata[140],cpq_rdata[142],cpq_rdata[144]}),
.dout ({cpq_read_data[128],cpq_read_data[130],cpq_read_data[132],cpq_read_data[134],cpq_read_data[136],cpq_read_data[138],
cpq_read_data[140],cpq_read_data[142],cpq_read_data[144]})
lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_10l__width_9 cpq_data_buf_3 (
.din ({cpq_rdata[129],cpq_rdata[131],cpq_rdata[133],cpq_rdata[135],cpq_rdata[137],cpq_rdata[139],
cpq_rdata[141],cpq_rdata[143],cpq_rdata[145]}),
.dout ({cpq_read_data[129],cpq_read_data[131],cpq_read_data[133],cpq_read_data[135],cpq_read_data[137],cpq_read_data[139],
cpq_read_data[141],cpq_read_data[143],cpq_read_data[145]})
lsu_cid_dp_msff_macro__stack_64c__width_64 dff_fifo_0 (
.scan_in(dff_fifo_0_scanin),
.scan_out(dff_fifo_0_scanout),
.se (tcu_se_scancollar_out),
.din (cpq_read_data[63:0]),
lsu_cid_dp_msff_macro__stack_64c__width_64 dff_fifo_1 (
.scan_in(dff_fifo_1_scanin),
.scan_out(dff_fifo_1_scanout),
.se (tcu_se_scancollar_out),
.din (cpq_read_data[127:64]),
.dout (fifo_data[127:64]),
lsu_cid_dp_msff_macro__stack_10l__width_9 dff_fifo_2 (
.scan_in(dff_fifo_2_scanin),
.scan_out(dff_fifo_2_scanout),
.se (tcu_se_scancollar_out),
.din ({cpq_read_data[128],cpq_read_data[130],cpq_read_data[132],cpq_read_data[134],cpq_read_data[136],cpq_read_data[138],
cpq_read_data[140],cpq_read_data[142],cpq_read_data[144]}),
.dout ({fifo_data[128],fifo_data[130],fifo_data[132],fifo_data[134],fifo_data[136],fifo_data[138],
fifo_data[140],fifo_data[142],fifo_data[144]}),
lsu_cid_dp_msff_macro__stack_10l__width_9 dff_fifo_3 (
.scan_in(dff_fifo_3_scanin),
.scan_out(dff_fifo_3_scanout),
.se (tcu_se_scancollar_out),
.din ({cpq_read_data[129],cpq_read_data[131],cpq_read_data[133],cpq_read_data[135],cpq_read_data[137],cpq_read_data[139],
cpq_read_data[141],cpq_read_data[143],cpq_read_data[145]}),
.dout ({fifo_data[129],fifo_data[131],fifo_data[133],fifo_data[135],fifo_data[137],fifo_data[139],
fifo_data[141],fifo_data[143],fifo_data[145]}),
lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 cpq_mx_0 (
.din1 (cpq_read_data[63:0]),
.dout (cpq_mx_data[63:0])
lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 cpq_mx_1 (
.din0 (fifo_data[127:64]),
.din1 (cpq_read_data[127:64]),
.dout (cpq_mx_data[127:64])
lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_10l__width_9 cpq_mx_2 (
.din0 ({fifo_data[128],fifo_data[130],fifo_data[132],fifo_data[134],fifo_data[136],fifo_data[138],
fifo_data[140],fifo_data[142],fifo_data[144]}),
.din1 ({cpq_read_data[128],cpq_read_data[130],cpq_read_data[132],cpq_read_data[134],cpq_read_data[136],cpq_read_data[138],
cpq_read_data[140],cpq_read_data[142],cpq_read_data[144]}),
.din2 ({data_d1[128],data_d1[130],data_d1[132],data_d1[134],data_d1[136],data_d1[138],
data_d1[140],data_d1[142],data_d1[144]}),
.din3 ({in_data[128],in_data[130],in_data[132],in_data[134],in_data[136],in_data[138],
in_data[140],in_data[142],in_data[144]}),
.dout ({cpq_mx_data[128],cpq_mx_data[130],cpq_mx_data[132],cpq_mx_data[134],cpq_mx_data[136],cpq_mx_data[138],
cpq_mx_data[140],cpq_mx_data[142],cpq_mx_data[144]})
lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_10l__width_9 cpq_mx_3 (
.din0 ({fifo_data[129],fifo_data[131],fifo_data[133],fifo_data[135],fifo_data[137],fifo_data[139],
fifo_data[141],fifo_data[143],fifo_data[145]}),
.din1 ({cpq_read_data[129],cpq_read_data[131],cpq_read_data[133],cpq_read_data[135],cpq_read_data[137],cpq_read_data[139],
cpq_read_data[141],cpq_read_data[143],cpq_read_data[145]}),
.din2 ({data_d1[129],data_d1[131],data_d1[133],data_d1[135],data_d1[137],data_d1[139],
data_d1[141],data_d1[143],data_d1[145]}),
.din3 ({in_data[129],in_data[131],in_data[133],in_data[135],in_data[137],in_data[139],
in_data[141],in_data[143],in_data[145]}),
.dout ({cpq_mx_data[129],cpq_mx_data[131],cpq_mx_data[133],cpq_mx_data[135],cpq_mx_data[137],cpq_mx_data[139],
cpq_mx_data[141],cpq_mx_data[143],cpq_mx_data[145]})
lsu_cid_dp_msff_macro__stack_64c__width_64 dff_out_0 (
.scan_in(dff_out_0_scanin),
.scan_out(dff_out_0_scanout),
.se (tcu_se_scancollar_out),
.en (1'b1), // should have PM here, but need enough time to see incoming packet
.din (cpq_mx_data[63:0]),
.dout (cpq_data_out[63:0]),
lsu_cid_dp_msff_macro__stack_64c__width_64 dff_out_1 (
.scan_in(dff_out_1_scanin),
.scan_out(dff_out_1_scanout),
.se (tcu_se_scancollar_out),
.din (cpq_mx_data[127:64]),
.dout (cpq_data_out[127:64]),
lsu_cid_dp_msff_macro__stack_10l__width_9 dff_out_2 (
.scan_in(dff_out_2_scanin),
.scan_out(dff_out_2_scanout),
.se (tcu_se_scancollar_out),
.din ({cpq_mx_data[128],cpq_mx_data[130],cpq_mx_data[132],cpq_mx_data[134],cpq_mx_data[136],cpq_mx_data[138],
cpq_mx_data[140],cpq_mx_data[142],cpq_mx_data[144]}),
.dout ({cpq_data_out[128],cpq_data_out[130],cpq_data_out[132],cpq_data_out[134],cpq_data_out[136],cpq_data_out[138],
cpq_data_out[140],cpq_data_out[142],cpq_data_out[144]}),
lsu_cid_dp_msff_macro__stack_10l__width_10 dff_out_3 (
.scan_in(dff_out_3_scanin),
.scan_out(dff_out_3_scanout),
.se (tcu_se_scancollar_out),
.din ({cpq_mx_data[143],cpq_mx_data[129],cpq_mx_data[131],cpq_mx_data[133],cpq_mx_data[135],cpq_mx_data[137],
cpq_mx_data[139],cpq_mx_data[141],cpq_mx_data[143],cpq_mx_data[145]}),
.dout ({cid_st_data_sel, cpq_data_out[129],cpq_data_out[131],cpq_data_out[133],cpq_data_out[135],cpq_data_out[137],
cpq_data_out[139],cpq_data_out[141],cpq_data_out[143],cpq_data_out[145]}),
assign cid_tid_unbuf[2:0] = cpq_data_out[136:134];
assign cid_pref = cpq_data_out[128];
assign cid_pkt_type[4:0] = cpq_data_out[145:141];
assign cid_atomic_unbuf = cpq_data_out[129];
lsu_cid_dp_buff_macro__dbuff_16x__rep_1__stack_64c__width_64 fill_data_buf_0 (
.din (cpq_data_out[63:0]),
.dout (cid_fill_data_e[63:0])
lsu_cid_dp_buff_macro__dbuff_16x__rep_1__stack_64c__width_64 fill_data_buf_1 (
.din (cpq_data_out[127:64]),
.dout (cid_fill_data_e[127:64])
lsu_cid_dp_buff_macro__rep_1__stack_10l__width_9 fill_data_buf_2 (
.din ({1'b0, cpq_data_out[130], cpq_data_out[132], cpq_data_out[134], cpq_data_out[136],
cpq_data_out[138], cpq_data_out[140], 1'b0, cpq_data_out[144]}),
.dout ({buf_unused[0],cid_pkt_data_e[130],cid_pkt_data_e[132],cid_pkt_data_e[134],cid_pkt_data_e[136],
cid_pkt_data_e[138],cid_pkt_data_e[140],buf_unused[1],cid_pkt_data_e[144]})
lsu_cid_dp_buff_macro__rep_1__stack_10l__width_9 fill_data_buf_3 (
.din ({cpq_data_out[129], cpq_data_out[131], cpq_data_out[133], cpq_data_out[135],
cpq_data_out[137], cpq_data_out[139], 1'b0, cpq_data_out[143], 1'b0}),
.dout ({cid_pkt_data_e[129],cid_pkt_data_e[131],cid_pkt_data_e[133],cid_pkt_data_e[135],
cid_pkt_data_e[137],cid_pkt_data_e[139],buf_unused[2],cid_pkt_data_e[143],buf_unused[3]})
lsu_cid_dp_buff_macro__width_3 misc_data_buf (
.din (cpq_data_out[120:118]),
assign cid_rmo_ack = cid_fill_data_e[125];
assign cid_set_icinval = cid_fill_data_e[124];
assign cid_set_inval = cid_fill_data_e[123];
assign cid_st_addr[5:4] = cid_fill_data_e[122:121];
assign cid_st_addr[10:6] = cid_fill_data_e[116:112];
assign cid_st_addr[3] = cid_fill_data_e[104];
assign cid_st_bmask[7:0] = cid_fill_data_e[103:96];
assign cid_st_vector[15:0]= {cid_fill_data_e[93:92],cid_fill_data_e[89:88],cid_fill_data_e[85:84],cid_fill_data_e[81:80],
cid_fill_data_e[77:76],cid_fill_data_e[73:72],cid_fill_data_e[69:68],cid_fill_data_e[65:64]};
assign cid_inv_index[10:6] = cid_st_addr[10:6];
assign cid_dcsoc_err_e = cid_pkt_data_e[144];
assign cid_pkt_unused = cid_pkt_data_e[143];
assign cid_l2miss = cid_pkt_data_e[140];
assign cid_err[1:0] = cid_pkt_data_e[139:138];
assign cid_ncache = cid_pkt_data_e[137];
assign cid_tid[2:0] = cid_pkt_data_e[136:134];
assign cid_xinval = cid_pkt_data_e[133];
assign cid_xway[1:0] = cid_pkt_data_e[132:131];
assign cid_unused[1] = cid_pkt_data_e[130];
assign cid_atomic = cid_pkt_data_e[129];
////////////////////////////////////////////////////////////////////////////////
// Invalidation vectors have the following format.
// Vectors for store ack packets contain the first 32 bits only.
// [31:0] = {cpu7[3:0],cpu6[3:0],...,cpu1[3:0],cpu0[3:0]} for addr[5:4]=00
// [55:32] = {cpu7[2:0],cpu6[2:0],...,cpu1[2:0],cpu0[2:0]} for addr[5:4]=01
// [87:56] = {cpu7[3:0],cpu6[3:0],...,cpu1[3:0],cpu0[3:0]} for addr[5:4]=10
// [111:88] = {cpu7[2:0],cpu6[2:0],...,cpu1[2:0],cpu0[2:0]} for addr[5:4]=11
//Select the invalidation info specific to this cpu
lsu_cid_dp_mux_macro__mux_aodec__ports_8__stack_18l__width_18 inv_vec_mx (
.din0 ({cid_fill_data_e[67:64],cid_fill_data_e[90:88],cid_fill_data_e[59:56],cid_fill_data_e[34:32],cid_fill_data_e[3:0]}),
.din1 ({cid_fill_data_e[71:68],cid_fill_data_e[93:91],cid_fill_data_e[63:60],cid_fill_data_e[37:35],cid_fill_data_e[7:4]}),
.din2 ({cid_fill_data_e[75:72],cid_fill_data_e[96:94],cid_fill_data_e[67:64],cid_fill_data_e[40:38],cid_fill_data_e[11:8]}),
.din3 ({cid_fill_data_e[79:76],cid_fill_data_e[99:97],cid_fill_data_e[71:68],cid_fill_data_e[43:41],cid_fill_data_e[15:12]}),
.din4 ({cid_fill_data_e[83:80],cid_fill_data_e[102:100],cid_fill_data_e[75:72],cid_fill_data_e[46:44],cid_fill_data_e[19:16]}),
.din5 ({cid_fill_data_e[87:84],cid_fill_data_e[105:103],cid_fill_data_e[79:76],cid_fill_data_e[49:47],cid_fill_data_e[23:20]}),
.din6 ({cid_fill_data_e[91:88],cid_fill_data_e[108:106],cid_fill_data_e[83:80],cid_fill_data_e[52:50],cid_fill_data_e[27:24]}),
.din7 ({cid_fill_data_e[95:92],cid_fill_data_e[111:109],cid_fill_data_e[87:84],cid_fill_data_e[55:53],cid_fill_data_e[31:28]}),
lsu_cid_dp_buff_macro__stack_18l__width_18 inv_vec_buf (
.dout (cid_inv_vec[17:0])
assign cid_st_way[1:0] = cid_inv_vec[17:16];
////////////////////////////////////////////////////////////////////////////////
lsu_cid_dp_msff_macro__stack_8l__width_8 dff_cmp_data (
.scan_in(dff_cmp_data_scanin),
.scan_out(dff_cmp_data_scanout),
.din (bist_wdata_1[7:0]),
.dout (bist_cmp_data[7:0]),
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 bist_wdata_mx_0 (
.din0 ({8{mbi_wdata[7:0]}}),
.dout (cid_cpq_wdata[63:0])
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 bist_wdata_mx_1 (
.din0 ({8{mbi_wdata[7:0]}}),
.dout (cid_cpq_wdata[127:64])
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_10l__width_9 bist_wdata_mx_2 (
.din0 ({mbi_wdata[0],mbi_wdata[7:0]}),
.din1 ({in_data[128],in_data[130],in_data[132],in_data[134],in_data[136],in_data[138],
in_data[140],in_data[142],in_data[144]}),
.dout ({cid_cpq_wdata[128],cid_cpq_wdata[130],cid_cpq_wdata[132],cid_cpq_wdata[134],cid_cpq_wdata[136],
cid_cpq_wdata[138],cid_cpq_wdata[140],cid_cpq_wdata[142],cid_cpq_wdata[144]})
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_10l__width_9 bist_wdata_mx_3 (
.din0 ({mbi_wdata[0],mbi_wdata[7:0]}),
.din1 ({in_data[129],in_data[131],in_data[133],in_data[135],in_data[137],in_data[139],
in_data[141],in_data[143],in_data[145]}),
.dout ({cid_cpq_wdata[129],cid_cpq_wdata[131],cid_cpq_wdata[133],cid_cpq_wdata[135],cid_cpq_wdata[137],
cid_cpq_wdata[139],cid_cpq_wdata[141],cid_cpq_wdata[143],cid_cpq_wdata[145]})
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 cpq_bist_mx_0 (
.din0 (fifo_data[127:64]),
.dout (fifo_cmp_data[63:0])
lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_10l__width_9 cpq_bist_mx_2 (
.din0 ({fifo_data[129],fifo_data[131],fifo_data[133],fifo_data[135],fifo_data[137],fifo_data[139],
fifo_data[141],fifo_data[143],fifo_data[145]}),
.din1 ({fifo_data[128],fifo_data[130],fifo_data[132],fifo_data[134],fifo_data[136],fifo_data[138],
fifo_data[140],fifo_data[142],fifo_data[144]}),
.dout (fifo_cmp_data[72:64])
lsu_cid_dp_cmp_macro__width_64 bist_cmp1 (
.din0 ({8{bist_cmp_data[7:0]}}),
.din1 ({fifo_cmp_data[63:0]}),
lsu_cid_dp_cmp_macro__width_16 bist_cmp2 (
.din0 ({2{bist_cmp_data[7:0]}}),
.din1 ({bist_cmp_data[7:1],fifo_cmp_data[72:64]}),
assign cid_cpq_cmp_3 = 1'b1;
assign dff_d1_0_scanin = scan_in ;
assign dff_d1_1_scanin = dff_d1_0_scanout ;
assign dff_d1_2_scanin = dff_d1_1_scanout ;
assign dff_d1_3_scanin = dff_d1_2_scanout ;
assign dff_fifo_0_scanin = dff_d1_3_scanout ;
assign dff_fifo_1_scanin = dff_fifo_0_scanout ;
assign dff_fifo_2_scanin = dff_fifo_1_scanout ;
assign dff_fifo_3_scanin = dff_fifo_2_scanout ;
assign dff_out_0_scanin = dff_fifo_3_scanout ;
assign dff_out_1_scanin = dff_out_0_scanout ;
assign dff_out_2_scanin = dff_out_1_scanout ;
assign dff_out_3_scanin = dff_out_2_scanout ;
assign dff_cmp_data_scanin = dff_out_3_scanout ;
assign scan_out = dff_cmp_data_scanout ;
module lsu_cid_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
// any PARAMS parms go into naming of macro
module lsu_cid_dp_msff_macro__stack_64c__width_64 (
.so({so[62:0],scan_out}),
// any PARAMS parms go into naming of macro
module lsu_cid_dp_msff_macro__stack_10l__width_9 (
module lsu_cid_dp_buff_macro__stack_64c__width_64 (
module lsu_cid_dp_buff_macro__stack_10l__width_9 (
module lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_64c__width_64 (
module lsu_cid_dp_buff_macro__dbuff_4x__minbuff_1__stack_10l__width_9 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 (
cl_dp1_muxbuff4_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_cid_dp_mux_macro__mux_aonpe__ports_4__stack_10l__width_9 (
cl_dp1_muxbuff4_8x c0_0 (
// any PARAMS parms go into naming of macro
module lsu_cid_dp_msff_macro__stack_10l__width_10 (
module lsu_cid_dp_buff_macro__dbuff_16x__rep_1__stack_64c__width_64 (
module lsu_cid_dp_buff_macro__rep_1__stack_10l__width_9 (
module lsu_cid_dp_buff_macro__width_3 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_cid_dp_mux_macro__mux_aodec__ports_8__stack_18l__width_18 (
module lsu_cid_dp_buff_macro__stack_18l__width_18 (
// any PARAMS parms go into naming of macro
module lsu_cid_dp_msff_macro__stack_8l__width_8 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_cid_dp_mux_macro__mux_aope__ports_2__stack_10l__width_9 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module lsu_cid_dp_cmp_macro__width_64 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module lsu_cid_dp_cmp_macro__width_16 (