// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: lsu_dcd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ========== Copyright Header End ============================================
wire [63:0] prealign_load_data;
wire [7:0] bist_cmp_data_local;
wire mmu_va_b_lat_scanin;
wire mmu_va_b_lat_scanout;
input tcu_pce_ov; // scan signals
input [63:0] dca_ld_data_b; // data from dcache array
// Sign/zero extend controls
input [7:1] dac_byte_one_extend;
input [7:1] dac_byte_sel_data;
// Byte alignment controls
// Outputs to exu and fgu
output [63:0] lsu_exu_ld_data_b;
output [63:0] lsu_fgu_fld_data_b;
input [7:0] bist_cmp_data;
output [1:0] dcd_dca_data_compare;
input [47:0] lsu_mmu_va_m;
output [47:0] lsu_mmu_va_b;
assign pce_ov = tcu_pce_ov;
assign prealign_load_data[63:0] = dca_ld_data_b[63:0];
//=========================================================================================
// Alignment of Load Return Data
//=========================================================================================
// All data returning to the register files must be aligned
// and sign extended here. Formatting occurs in two steps.
// 1st: Swizzle the bytes based on endianess, size, and address.
// 2nd: Pass the data or replace with zero/one extention.
// In the layout, bits should be interleaved to (1) minmize wire
// usage and (2) keep msb's close to the dac block.
// Because the fgu is flipped in the spc floorplan, it's alignment muxes are separate
// so that the mux ordering matches the fgu bit ordering.
assign byte7[7:0] = prealign_load_data[63:56];
assign byte6[7:0] = prealign_load_data[55:48];
assign byte5[7:0] = prealign_load_data[47:40];
assign byte4[7:0] = prealign_load_data[39:32];
assign byte3[7:0] = prealign_load_data[31:24];
assign byte2[7:0] = prealign_load_data[23:16];
assign byte1[7:0] = prealign_load_data[15:8];
assign byte0[7:0] = prealign_load_data[7:0];
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_8__stack_8c__width_8 i_swap_byte0 (
.sel0 (dac_swap0_byte0_r),
.sel1 (dac_swap0_byte1_r),
.sel2 (dac_swap0_byte2_r),
.sel3 (dac_swap0_byte3_r),
.sel4 (dac_swap0_byte4_r),
.sel5 (dac_swap0_byte5_r),
.sel6 (dac_swap0_byte6_r),
.sel7 (dac_swap0_byte7_r),
// No sign-extension for byte0. It always has "real" data.
assign final_data[7:0] = align_byte0[7:0];
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_8__stack_8c__width_8 i_swap_byte1 (
.sel0 (dac_swap1_byte0_r),
.sel1 (dac_swap1_byte1_r),
.sel2 (dac_swap1_byte2_r),
.sel3 (dac_swap1_byte3_r),
.sel4 (dac_swap1_byte4_r),
.sel5 (dac_swap1_byte5_r),
.sel6 (dac_swap1_byte6_r),
.sel7 (dac_swap1_byte7_r),
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte1 (
.din0 (align_byte1[7:0]),
.sel0 (dac_byte_sel_data[1]),
.sel1 (dac_byte_one_extend[1]),
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte2 (
.sel0 (dac_swap2_byte1_r),
.sel1 (dac_swap2_byte2_r),
.sel2 (dac_swap2_byte5_r),
.sel3 (dac_swap2_byte6_r),
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte2 (
.din0 (align_byte2[7:0]),
.sel0 (dac_byte_sel_data[2]),
.sel1 (dac_byte_one_extend[2]),
.dout (final_data[23:16])
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte3 (
.sel0 (dac_swap3_byte0_r),
.sel1 (dac_swap3_byte3_r),
.sel2 (dac_swap3_byte4_r),
.sel3 (dac_swap3_byte7_r),
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte3 (
.din0 (align_byte3[7:0]),
.sel0 (dac_byte_sel_data[3]),
.sel1 (dac_byte_one_extend[3]),
.dout (final_data[31:24])
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte4 (
.sel0 (dac_swap4_byte0_l),
.sel1 (dac_swap4_byte3_l),
.sel2 (dac_swap4_byte4_l),
.sel3 (dac_swap4_byte7_l),
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte4 (
.din0 (align_byte4[7:0]),
.sel0 (dac_byte_sel_data[4]),
.sel1 (dac_byte_one_extend[4]),
.dout (final_data[39:32])
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte5 (
.sel0 (dac_swap5_byte1_l),
.sel1 (dac_swap5_byte2_l),
.sel2 (dac_swap5_byte5_l),
.sel3 (dac_swap5_byte6_l),
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte5 (
.din0 (align_byte5[7:0]),
.sel0 (dac_byte_sel_data[5]),
.sel1 (dac_byte_one_extend[5]),
.dout (final_data[47:40])
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte6 (
.sel0 (dac_swap6_byte1_l),
.sel1 (dac_swap6_byte2_l),
.sel2 (dac_swap6_byte5_l),
.sel3 (dac_swap6_byte6_l),
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte6 (
.din0 (align_byte6[7:0]),
.sel0 (dac_byte_sel_data[6]),
.sel1 (dac_byte_one_extend[6]),
.dout (final_data[55:48])
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 i_swap_byte7 (
.sel0 (dac_swap7_byte0_l),
.sel1 (dac_swap7_byte3_l),
.sel2 (dac_swap7_byte4_l),
.sel3 (dac_swap7_byte7_l),
lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 sext_byte7 (
.din0 (align_byte7[7:0]),
.sel0 (dac_byte_sel_data[7]),
.sel1 (dac_byte_one_extend[7]),
.dout (final_data[63:56])
lsu_dcd_dp_buff_macro__dbuff_32x__rep_1__width_64 exu_data (
.dout (lsu_exu_ld_data_b[63:0])
lsu_dcd_dp_buff_macro__dbuff_32x__rep_1__width_64 fgu_data (
.din ({align_byte7[7:0],align_byte6[7:0],align_byte5[7:0],align_byte4[7:0],
align_byte3[7:0],align_byte2[7:0],align_byte1[7:0],align_byte0[7:0]}),
.dout (lsu_fgu_fld_data_b[63:0])
lsu_dcd_dp_buff_macro__width_10 cmp_buff (
.din ({ data_compare[1:0],bist_cmp_data[7:0]}),
.dout ({dcd_dca_data_compare[1:0],bist_cmp_data_local[7:0]})
lsu_dcd_dp_cmp_macro__width_32 bist_cmp0 (
.din0 ({4{bist_cmp_data_local[7:0]}}),
.din1 (dca_ld_data_b[63:32]),
lsu_dcd_dp_cmp_macro__width_32 bist_cmp1 (
.din0 ({4{bist_cmp_data_local[7:0]}}),
.din1 (dca_ld_data_b[31:0]),
//////////////////////////////
// Flop for VA to send to MMU
lsu_dcd_dp_msff_macro__minbuff_1__stack_48c__width_48 mmu_va_b_lat (
.scan_in(mmu_va_b_lat_scanin),
.scan_out(mmu_va_b_lat_scanout),
.din (lsu_mmu_va_m[47:0]),
lsu_dcd_dp_buff_macro__dbuff_32x__stack_48c__width_48 mmu_va_b_buf (
.dout (lsu_mmu_va_b[47:0])
assign mmu_va_b_lat_scanin = scan_in ;
assign scan_out = mmu_va_b_lat_scanout ;
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_8__stack_8c__width_8 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_8c__width_8 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_dcd_dp_mux_macro__buffsel_none__mux_aonpe__ports_4__stack_8c__width_8 (
module lsu_dcd_dp_buff_macro__dbuff_32x__rep_1__width_64 (
module lsu_dcd_dp_buff_macro__width_10 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module lsu_dcd_dp_cmp_macro__width_32 (
// any PARAMS parms go into naming of macro
module lsu_dcd_dp_msff_macro__minbuff_1__stack_48c__width_48 (
.so({so[46:0],scan_out}),
module lsu_dcd_dp_buff_macro__dbuff_32x__stack_48c__width_48 (