// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: lsu_lmd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
wire [12:11] lsu_va_b_unused;
wire [63:0] rd_update_pkt0;
wire [63:0] rd_update_pkt1;
wire [63:0] rd_update_pkt2;
wire [63:0] rd_update_pkt3;
wire [63:0] rd_update_pkt4;
wire [63:0] rd_update_pkt5;
wire [63:0] rd_update_pkt6;
wire [63:0] rd_update_pkt7;
wire [10:5] ifu_ld_index;
wire [44:0] lmq0_or_diag;
wire [44:0] lmd_muxdata_e;
wire [30:2] diag_data_w_buf;
wire [39:11] diag_addr_e;
wire dff_lmq_data_m_scanin;
wire dff_lmq_data_m_scanout;
wire [63:0] stb_ram_data_buf;
wire [63:0] stb_ldxa_asi_data_w_buf;
wire [63:0] ard_pid_data_buf;
wire [63:0] dcs_ldxa_asi_data_w_buf;
wire [63:0] lmq0_bypass_data;
wire [63:0] lmq1_bypass_data;
wire [63:0] lmq2_bypass_data;
wire [63:0] lmq3_bypass_data;
wire [63:0] lmq4_bypass_data;
wire [63:0] lmq5_bypass_data;
wire [63:0] lmq6_bypass_data;
wire [63:0] lmq7_bypass_data;
wire [63:0] bypass_data_m;
wire dff_st_data_w_scanin;
wire dff_st_data_w_scanout;
wire [127:0] fill_data_e;
wire byp_half_sel_scanin;
wire byp_half_sel_scanout;
input [7:0] lmc_lmq_enable_b; // Load enables for LMQ flops (threaded)
input [7:0] lmc_lmq_bypass_en; // Load enables for LMQ bypass registers
input [7:0] lmc_pcx_sel_p4; // Mux the selected thread
input [7:0] lmc_byp_sel_e; // Thread select for fill/bypass
input [7:0] lmc_thrd_byp_sel_m; // Thread select for bypass register
input [4:0] lmc_lmq0_byp_sel; // source selects for load bypass registers
input [4:0] lmc_lmq1_byp_sel; // source selects for load bypass registers
input [4:0] lmc_lmq2_byp_sel; // source selects for load bypass registers
input [4:0] lmc_lmq3_byp_sel; // source selects for load bypass registers
input [4:0] lmc_lmq4_byp_sel; // source selects for load bypass registers
input [4:0] lmc_lmq5_byp_sel; // source selects for load bypass registers
input [4:0] lmc_lmq6_byp_sel; // source selects for load bypass registers
input [4:0] lmc_lmq7_byp_sel; // source selects for load bypass registers
input [1:0] lmc_bld_addr54; // Block load address modifier
input lmc_bld_req; // Current request is for block load
input [7:0] lmc_rd_update;
input [7:0] lmc_ld_unfilled;
input lmc_bist_or_diag_e;
input lmc_byp_data_enable;
input [60:40] dcc_ld_miss_ctl; // Load miss packet info
input [1:0] dcc_perr_enc_b; // D$ parity error encoding
input dcc_cache_diag_wr_b;
input [63:0] stb_ram_data; // stb data for RAW bypass
input [63:0] ard_pid_data; // asi load data
input [39:13] stb_st_addr_b; // should be equal to tlb_pgnum for normal loads
input [12:11] sbd_st_addr_b;
input [63:0] sbd_st_data_b; // for CAS
input [63:0] stb_ldxa_asi_data_w;
input [127:0] cid_fill_data_e; // cpx fill data
input [8:6] lsu_cpx_cpkt;
input [63:0] dcs_ldxa_asi_data_w;
input cic_diag_data_sel_e;
output [7:0] lmd_asi_ld; // ASI type flag for each thread
output [7:0] lmd_asi_indet; // ASI type flag for each thread
output [7:0] lmd_sec_cmp_b; // Secondary load indicators
// Data for fills and bypass
output [2:0] lmd_ld_addr_m;
output lmd_bendian_m; // Endian bit for load misses
output lmd_sxt_fsr_m; // Sign extend / LDFSR for load misses
output [1:0] lmd_fill_way_e; // Replacement way for fill data write
output [1:0] lmd_fill_way_m; // Replacement way for fill data write
output [1:0] lmd_sz_m; // Size bits from LMQ
output lmd_fpld_m; // Load was floating point
output [2:1] lmd_rd_e; // Dest. register address
output [4:0] lmd_rd_m; // Dest. register address
output [63:0] lmd_bypass_data_m;
output [127:0] lmd_fill_data_e;
output [63:0] lmd_fill_or_byp_data_m;
output [7:0] lmd_misc_msb_m;
output [39:3] lmd_fill_addr_e;
output [10:4] lmd_fill_addr_m;
output lmd_wrtag_parity_e;
output [2:0] lmd_pcx_rqtyp;
output [1:0] lmd_pcx_rway;
output [39:0] lmd_pcx_addr;
output [1:0] lmd_asi_type;
output [7:0] lmd_asi_asi;
output [1:0] lmd_dc_err_e;
output [10:5] lsu_ifu_ld_index;
output [1:0] lsu_ext_int_type;
output [5:0] lsu_ext_int_vec;
output [2:0] lsu_ext_int_tid;
input tcu_pce_ov; // scan signals
lsu_lmd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 (
.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
.dout({se,pce_ov,siclk,soclk})
////////////////////////////////////////////////////////////////////////////////
// Format of the load miss buffer
// 63:62 - parity error info
// 60 - ASI - (==0 for memory access)
// 59 - fpodd32 - 32 bit fp load to odd Rd
// 58 - fp32 - 32 bit fp load
// 57 - fp_ld - load is floating point
// 56 - sign_ext/fsr - data requires sign extension or is LDFSR
// 55 - bendian - big endian access
// 54:50 - rd[4:0] - destination register
// 49 - ldst_dbl - instruction is LDD (requires two returns)
// 48:47 - sz[1:0] - size
// 46:44 - rqtyp[2:0] - request type
// 43 - nc - non-cacheable load
// 42 - prefetch - prefetch instruction
// 41:40 - way[1:0] - replacement way
// 39:13 - pgnum[39:13] - translated addr.
// 60 - ASI - (==1 for ASI access)
// 56 - indeterminate flag
// 55 - fast/local ring - 1=fast
// 49:48 - ASI type (00-ASI,01-ASR,10-PR,11-HPR)
lsu_lmd_dp_buff_macro__rep_1__stack_64c__width_40 ld_addr_buf (
.din ({stb_st_addr_b[39:13],sbd_st_addr_b[12:11],lsu_va_b[10:0]}),
// Leave lsu_va_b[12:11] at this level because verfication bench needs it.
assign lsu_va_b_unused[12:11] = lsu_va_b[12:11];
////////////////////////////////////////////////////////////////////////////////
// LMQ flops. One for each thread.
////////////////////////////////////////////////////////////////////////////////
// Miss packet construction
lsu_lmd_dp_buff_macro__dbuff_32x__rep_1__stack_24c__width_24 miss_pkt_buf (
.din ({dcc_perr_enc_b[1:0],wrtag_parity_b,dcc_ld_miss_ctl[60:44],lmc_lmd_ncache_b,dcc_ld_miss_ctl[42:40]}),
.dout (ld_miss_pkt[63:40])
assign ctl_unused=dcc_ld_miss_ctl[43];
assign ld_miss_pkt[39:0] = ld_addr_b[39:0];
lsu_lmd_dp_prty_macro__width_32 wrtag_prty (
.din ({ld_miss_pkt[39:32],3'b000,ld_miss_pkt[31:11]}),
// Library incrementer is too big and is more than I need. Build a simple one for each thread.
lsu_lmd_dp_inv_macro__width_8 rd_incr0 (
.din ({lmq7_pkt[`LMQ_RD_LO],lmq6_pkt[`LMQ_RD_LO],lmq5_pkt[`LMQ_RD_LO],lmq4_pkt[`LMQ_RD_LO],
lmq3_pkt[`LMQ_RD_LO],lmq2_pkt[`LMQ_RD_LO],lmq1_pkt[`LMQ_RD_LO],lmq0_pkt[`LMQ_RD_LO]}),
.dout ({rd7_plus1[0],rd6_plus1[0],rd5_plus1[0],rd4_plus1[0],rd3_plus1[0],rd2_plus1[0],rd1_plus1[0],rd0_plus1[0]})
lsu_lmd_dp_xor_macro__ports_2__width_8 rd_incr1 (
.din0 ({lmq7_pkt[`LMQ_RD_LO],lmq6_pkt[`LMQ_RD_LO],lmq5_pkt[`LMQ_RD_LO],lmq4_pkt[`LMQ_RD_LO],
lmq3_pkt[`LMQ_RD_LO],lmq2_pkt[`LMQ_RD_LO],lmq1_pkt[`LMQ_RD_LO],lmq0_pkt[`LMQ_RD_LO]}),
.din1 ({lmq7_pkt[`LMQ_RD_LO + 1],lmq6_pkt[`LMQ_RD_LO + 1],lmq5_pkt[`LMQ_RD_LO + 1],lmq4_pkt[`LMQ_RD_LO + 1],
lmq3_pkt[`LMQ_RD_LO + 1],lmq2_pkt[`LMQ_RD_LO + 1],lmq1_pkt[`LMQ_RD_LO + 1],lmq0_pkt[`LMQ_RD_LO + 1]}),
.dout ({rd7_plus1[1],rd6_plus1[1],rd5_plus1[1],rd4_plus1[1],rd3_plus1[1],rd2_plus1[1],rd1_plus1[1],rd0_plus1[1]})
lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_0 (
.din0 (lmq0_pkt[`LMQ_RD_LO]),
.sel0 (lmq0_pkt[`LMQ_RD_LO + 1]),
.din1 (lmq0_pkt[`LMQ_RD_LO + 2]),
lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_1 (
.din0 (lmq1_pkt[`LMQ_RD_LO]),
.sel0 (lmq1_pkt[`LMQ_RD_LO + 1]),
.din1 (lmq1_pkt[`LMQ_RD_LO + 2]),
lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_2 (
.din0 (lmq2_pkt[`LMQ_RD_LO]),
.sel0 (lmq2_pkt[`LMQ_RD_LO + 1]),
.din1 (lmq2_pkt[`LMQ_RD_LO + 2]),
lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_3 (
.din0 (lmq3_pkt[`LMQ_RD_LO]),
.sel0 (lmq3_pkt[`LMQ_RD_LO + 1]),
.din1 (lmq3_pkt[`LMQ_RD_LO + 2]),
lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_4 (
.din0 (lmq4_pkt[`LMQ_RD_LO]),
.sel0 (lmq4_pkt[`LMQ_RD_LO + 1]),
.din1 (lmq4_pkt[`LMQ_RD_LO + 2]),
lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_5 (
.din0 (lmq5_pkt[`LMQ_RD_LO]),
.sel0 (lmq5_pkt[`LMQ_RD_LO + 1]),
.din1 (lmq5_pkt[`LMQ_RD_LO + 2]),
lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_6 (
.din0 (lmq6_pkt[`LMQ_RD_LO]),
.sel0 (lmq6_pkt[`LMQ_RD_LO + 1]),
.din1 (lmq6_pkt[`LMQ_RD_LO + 2]),
lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 rd_incr2_7 (
.din0 (lmq7_pkt[`LMQ_RD_LO]),
.sel0 (lmq7_pkt[`LMQ_RD_LO + 1]),
.din1 (lmq7_pkt[`LMQ_RD_LO + 2]),
assign rd_update_pkt0[63:0] = {lmq0_pkt[63:53],rd0_plus1[2:0],lmq0_pkt[49:0]};
assign rd_update_pkt1[63:0] = {lmq1_pkt[63:53],rd1_plus1[2:0],lmq1_pkt[49:0]};
assign rd_update_pkt2[63:0] = {lmq2_pkt[63:53],rd2_plus1[2:0],lmq2_pkt[49:0]};
assign rd_update_pkt3[63:0] = {lmq3_pkt[63:53],rd3_plus1[2:0],lmq3_pkt[49:0]};
assign rd_update_pkt4[63:0] = {lmq4_pkt[63:53],rd4_plus1[2:0],lmq4_pkt[49:0]};
assign rd_update_pkt5[63:0] = {lmq5_pkt[63:53],rd5_plus1[2:0],lmq5_pkt[49:0]};
assign rd_update_pkt6[63:0] = {lmq6_pkt[63:53],rd6_plus1[2:0],lmq6_pkt[49:0]};
assign rd_update_pkt7[63:0] = {lmq7_pkt[63:53],rd7_plus1[2:0],lmq7_pkt[49:0]};
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq0 (
.scan_in(dff_lmq0_scanin),
.scan_out(dff_lmq0_scanout),
.din0 (rd_update_pkt0[63:0]),
.din1 (ld_miss_pkt[63:0]),
.sel0 (lmc_rd_update[0]),
.en (lmc_lmq_enable_b[0]),
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq1 (
.scan_in(dff_lmq1_scanin),
.scan_out(dff_lmq1_scanout),
.din0 (rd_update_pkt1[63:0]),
.din1 (ld_miss_pkt[63:0]),
.sel0 (lmc_rd_update[1]),
.en (lmc_lmq_enable_b[1]),
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq2 (
.scan_in(dff_lmq2_scanin),
.scan_out(dff_lmq2_scanout),
.din0 (rd_update_pkt2[63:0]),
.din1 (ld_miss_pkt[63:0]),
.sel0 (lmc_rd_update[2]),
.en (lmc_lmq_enable_b[2]),
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq3 (
.scan_in(dff_lmq3_scanin),
.scan_out(dff_lmq3_scanout),
.din0 (rd_update_pkt3[63:0]),
.din1 (ld_miss_pkt[63:0]),
.sel0 (lmc_rd_update[3]),
.en (lmc_lmq_enable_b[3]),
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq4 (
.scan_in(dff_lmq4_scanin),
.scan_out(dff_lmq4_scanout),
.din0 (rd_update_pkt4[63:0]),
.din1 (ld_miss_pkt[63:0]),
.sel0 (lmc_rd_update[4]),
.en (lmc_lmq_enable_b[4]),
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq5 (
.scan_in(dff_lmq5_scanin),
.scan_out(dff_lmq5_scanout),
.din0 (rd_update_pkt5[63:0]),
.din1 (ld_miss_pkt[63:0]),
.sel0 (lmc_rd_update[5]),
.en (lmc_lmq_enable_b[5]),
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq6 (
.scan_in(dff_lmq6_scanin),
.scan_out(dff_lmq6_scanout),
.din0 (rd_update_pkt6[63:0]),
.din1 (ld_miss_pkt[63:0]),
.sel0 (lmc_rd_update[6]),
.en (lmc_lmq_enable_b[6]),
lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 dff_lmq7 (
.scan_in(dff_lmq7_scanin),
.scan_out(dff_lmq7_scanout),
.din0 (rd_update_pkt7[63:0]),
.din1 (ld_miss_pkt[63:0]),
.sel0 (lmc_rd_update[7]),
.en (lmc_lmq_enable_b[7]),
// Export ASI flags to LMQ control
lsu_lmd_dp_buff_macro__width_8 asi_ld_buf (
.din ({lmq7_pkt[`LMQ_ASI],lmq6_pkt[`LMQ_ASI],lmq5_pkt[`LMQ_ASI],lmq4_pkt[`LMQ_ASI],
lmq3_pkt[`LMQ_ASI],lmq2_pkt[`LMQ_ASI],lmq1_pkt[`LMQ_ASI],lmq0_pkt[`LMQ_ASI]}),
// Export ASI indeterminate flags to LMQ control
lsu_lmd_dp_buff_macro__width_8 asi_indet_buf (
.din ({lmq7_pkt[`LMQ_ASI_IND],lmq6_pkt[`LMQ_ASI_IND],lmq5_pkt[`LMQ_ASI_IND],lmq4_pkt[`LMQ_ASI_IND],
lmq3_pkt[`LMQ_ASI_IND],lmq2_pkt[`LMQ_ASI_IND],lmq1_pkt[`LMQ_ASI_IND],lmq0_pkt[`LMQ_ASI_IND]}),
.dout (lmd_asi_indet[7:0])
// Mux out the index of the load miss address for I$ to use for xinval
lsu_lmd_dp_mux_macro__mux_aodec__ports_8__stack_6l__width_6 xinval_indx_mx (
.sel (lsu_cpx_cpkt[8:6]),
.dout (ifu_ld_index[10:5])
lsu_lmd_dp_buff_macro__stack_6l__width_6 xinval_indx_buf (
.din (ifu_ld_index[10:5]),
.dout (lsu_ifu_ld_index[10:5])
////////////////////////////////////////////////////////////////////////////////
// Secondary miss comparators
////////////////////////////////////////////////////////////////////////////////
assign cmp_addr[39:4] = ld_addr_b[39:4];
lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_0 (
.din0 ({4'b0000,cmp_addr[31:4]}),
.din1 ({4'b0000,lmq0_pkt[31:4]}),
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_0 (
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_0 (
.din2 (lmc_ld_unfilled[0]),
lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_1 (
.din0 ({4'b0000,cmp_addr[31:4]}),
.din1 ({4'b0000,lmq1_pkt[31:4]}),
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_1 (
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_1 (
.din2 (lmc_ld_unfilled[1]),
lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_2 (
.din0 ({4'b0000,cmp_addr[31:4]}),
.din1 ({4'b0000,lmq2_pkt[31:4]}),
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_2 (
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_2 (
.din2 (lmc_ld_unfilled[2]),
lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_3 (
.din0 ({4'b0000,cmp_addr[31:4]}),
.din1 ({4'b0000,lmq3_pkt[31:4]}),
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_3 (
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_3 (
.din2 (lmc_ld_unfilled[3]),
lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_4 (
.din0 ({4'b0000,cmp_addr[31:4]}),
.din1 ({4'b0000,lmq4_pkt[31:4]}),
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_4 (
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_4 (
.din2 (lmc_ld_unfilled[4]),
lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_5 (
.din0 ({4'b0000,cmp_addr[31:4]}),
.din1 ({4'b0000,lmq5_pkt[31:4]}),
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_5 (
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_5 (
.din2 (lmc_ld_unfilled[5]),
lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_6 (
.din0 ({4'b0000,cmp_addr[31:4]}),
.din1 ({4'b0000,lmq6_pkt[31:4]}),
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_6 (
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_6 (
.din2 (lmc_ld_unfilled[6]),
lsu_lmd_dp_cmp_macro__width_32 cmp_sec_lo_7 (
.din0 ({4'b0000,cmp_addr[31:4]}),
.din1 ({4'b0000,lmq7_pkt[31:4]}),
lsu_lmd_dp_cmp_macro__width_8 cmp_sec_hi_7 (
lsu_lmd_dp_and_macro__ports_3__width_1 cmp_sec_cmp_7 (
.din2 (lmc_ld_unfilled[7]),
////////////////////////////////////////////////////////////////////////////////
// Select one thread to issue to the pcx or asi interface
////////////////////////////////////////////////////////////////////////////////
lsu_lmd_dp_mux_macro__mux_aonpe__ports_8__stack_64c__width_51 lmq_pcx_mux (
.din0 ({lmq0_pkt[55],lmq0_pkt[49:0]}),
.din1 ({lmq1_pkt[55],lmq1_pkt[49:0]}),
.din2 ({lmq2_pkt[55],lmq2_pkt[49:0]}),
.din3 ({lmq3_pkt[55],lmq3_pkt[49:0]}),
.din4 ({lmq4_pkt[55],lmq4_pkt[49:0]}),
.din5 ({lmq5_pkt[55],lmq5_pkt[49:0]}),
.din6 ({lmq6_pkt[55],lmq6_pkt[49:0]}),
.din7 ({lmq7_pkt[55],lmq7_pkt[49:0]}),
.sel0 (lmc_pcx_sel_p4[0]),
.sel1 (lmc_pcx_sel_p4[1]),
.sel2 (lmc_pcx_sel_p4[2]),
.sel3 (lmc_pcx_sel_p4[3]),
.sel4 (lmc_pcx_sel_p4[4]),
.sel5 (lmc_pcx_sel_p4[5]),
.sel6 (lmc_pcx_sel_p4[6]),
.sel7 (lmc_pcx_sel_p4[7]),
.dout ({pcx_pkt_b55,pcx_pkt[49:6],pcx_addr[5:4],pcx_pkt[3:0]})
lsu_lmd_dp_buff_macro__stack_64c__width_51 lmq_pcx_buf (
.din ({pcx_pkt_b55,pcx_pkt[49:0]}),
.dout ({lmd_asi_rngf,lmd_pcx_pkt[49:0]})
assign lmd_pcx_rqtyp[2:0] = lmd_pcx_pkt[`LMQ_RQ_HI:`LMQ_RQ_LO]; // 46:44
assign lmd_pcx_nc = lmd_pcx_pkt[`LMQ_NC]; // 43
assign lmd_pcx_pref = lmd_pcx_pkt[`LMQ_PREF]; // 42
assign lmd_pcx_rway[1:0] = lmd_pcx_pkt[`LMQ_WY_HI:`LMQ_WY_LO]; // 41:40
assign lmd_pcx_addr[39:0] = lmd_pcx_pkt[`LMQ_AD_HI:`LMQ_AD_LO]; // 39:0
assign lmd_asi_type[1:0] = lmd_pcx_pkt[`LMQ_ASI_TYPE + 1:`LMQ_ASI_TYPE]; // 49:48
assign lmd_ldbl = lmd_pcx_pkt[`LMQ_LDD]; // 49
assign lmd_asi_asi[7:0] = lmd_pcx_pkt[`LMQ_ASI_HI:`LMQ_ASI_LO]; // 47:40
assign lmd_sz_b1 = lmd_pcx_pkt[`LMQ_SZ_LO + 1]; // 48
assign lmd_sz_b0 = lmd_pcx_pkt[`LMQ_SZ_LO]; // 47
assign lmd_addrb2 = lmd_pcx_pkt[2];
lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_64c__width_2 bld_addr_mux (
.din0 (lmc_bld_addr54[1:0]),
////////////////////////////////////////////////////////////////////////////////
// Data for fills and bypass
////////////////////////////////////////////////////////////////////////////////
lsu_lmd_dp_mux_macro__dbuff_32x__dmux_4x__mux_aonpe__ports_8__stack_64c__width_15 lmq_data_mux_e (
.din0 ({lmq0_pkt[59:50],lmq0_pkt[48:47],lmq0_pkt[2:0]}),
.din1 ({lmq1_pkt[59:50],lmq1_pkt[48:47],lmq1_pkt[2:0]}),
.din2 ({lmq2_pkt[59:50],lmq2_pkt[48:47],lmq2_pkt[2:0]}),
.din3 ({lmq3_pkt[59:50],lmq3_pkt[48:47],lmq3_pkt[2:0]}),
.din4 ({lmq4_pkt[59:50],lmq4_pkt[48:47],lmq4_pkt[2:0]}),
.din5 ({lmq5_pkt[59:50],lmq5_pkt[48:47],lmq5_pkt[2:0]}),
.din6 ({lmq6_pkt[59:50],lmq6_pkt[48:47],lmq6_pkt[2:0]}),
.din7 ({lmq7_pkt[59:50],lmq7_pkt[48:47],lmq7_pkt[2:0]}),
.sel0 (lmc_byp_sel_e[0]),
.sel1 (lmc_byp_sel_e[1]),
.sel2 (lmc_byp_sel_e[2]),
.sel3 (lmc_byp_sel_e[3]),
.sel4 (lmc_byp_sel_e[4]),
.sel5 (lmc_byp_sel_e[5]),
.sel6 (lmc_byp_sel_e[6]),
.sel7 (lmc_byp_sel_e[7]),
.dout ({lmd_fpodd32b_e,lmd_fp32b_e,lmd_fpld_e,lmd_sxt_fsr_e,lmd_bendian_e,
rd_e[4:0],lmd_sz_e[1:0],ld_addr_e[2:0]})
lsu_lmd_dp_mux_macro__mux_aodec__ports_8__width_45 lmq_mux_e (
.din0 (lmq0_or_diag[44:0]),
.din1 ({lmq1_pkt[63:62],lmq1_pkt[`LMQ_TPAR],lmq1_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
lmq1_pkt[`LMQ_SZ_LO],lmq1_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq1_pkt[39:3]}),
.din2 ({lmq2_pkt[63:62],lmq2_pkt[`LMQ_TPAR],lmq2_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
lmq2_pkt[`LMQ_SZ_LO],lmq2_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq2_pkt[39:3]}),
.din3 ({lmq3_pkt[63:62],lmq3_pkt[`LMQ_TPAR],lmq3_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
lmq3_pkt[`LMQ_SZ_LO],lmq3_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq3_pkt[39:3]}),
.din4 ({lmq4_pkt[63:62],lmq4_pkt[`LMQ_TPAR],lmq4_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
lmq4_pkt[`LMQ_SZ_LO],lmq4_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq4_pkt[39:3]}),
.din5 ({lmq5_pkt[63:62],lmq5_pkt[`LMQ_TPAR],lmq5_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
lmq5_pkt[`LMQ_SZ_LO],lmq5_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq5_pkt[39:3]}),
.din6 ({lmq6_pkt[63:62],lmq6_pkt[`LMQ_TPAR],lmq6_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
lmq6_pkt[`LMQ_SZ_LO],lmq6_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq6_pkt[39:3]}),
.din7 ({lmq7_pkt[63:62],lmq7_pkt[`LMQ_TPAR],lmq7_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],
lmq7_pkt[`LMQ_SZ_LO],lmq7_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq7_pkt[39:3]}),
.dout (lmd_muxdata_e[44:0])
// Must mux in bist and diag write data for tag portion
lsu_lmd_dp_mux_macro__left_11__mux_aope__ports_2__stack_64c__width_29 bist_mx (
.din0 ({mbi_wdata[4:0],{3{mbi_wdata[7:0]}}}),
.din1 (diag_data_w_buf[30:2]),
.dout (diag_addr_e[39:11])
assign lmq0_or_diag[44:43] = lmq0_pkt[63:62];
assign lmq0_or_diag[41:39] = {lmq0_pkt[`LMQ_RD_LO + 2:`LMQ_RD_LO + 1],lmq0_pkt[`LMQ_SZ_LO]};
lsu_lmd_dp_mux_macro__left_3__mux_aope__ports_2__stack_64c__width_40 diag_mx (
.din0 ({wrtag_parity_w,lsu_va_w[12:11],diag_addr_e[39:11],lsu_va_w[10:3]}),
.din1 ({lmq0_pkt[`LMQ_TPAR],lmq0_pkt[`LMQ_WY_HI:`LMQ_WY_LO],lmq0_pkt[39:3]}),
.sel0 (lmc_bist_or_diag_e),
.dout ({lmq0_or_diag[42],lmq0_or_diag[38:0]})
lsu_lmd_dp_buff_macro__width_45 lmq_buf_e (
.din (lmd_muxdata_e[44:0]),
.dout ({lmd_dc_err_e[1:0],lmd_wrtag_parity_e,lmd_rd_e[2:1],lmd_fill_sz_b0_e,
lmd_fill_way_e[1:0], lmd_fill_addr_e[39:3]})
lsu_lmd_dp_msff_macro__stack_64c__width_25 dff_lmq_data_m (
.scan_in(dff_lmq_data_m_scanin),
.scan_out(dff_lmq_data_m_scanout),
lmd_fpodd32b_e,lmd_fp32b_e,lmd_fpld_e,lmd_sxt_fsr_e,lmd_bendian_e,
rd_e[4:0],lmd_sz_e[1:0],lmd_fill_way_e[1:0],lmd_fill_addr_e[10:4],ld_addr_e[2:0]}),
lmd_fpodd32b_m,lmd_fp32b_m,lmd_fpld_m,lmd_sxt_fsr_m,lmd_bendian_m,
lmd_rd_m[4:0],lmd_sz_m[1:0],lmd_fill_way_m[1:0],lmd_fill_addr_m[10:4],lmd_ld_addr_m[2:0]}),
////////////////////////////////////////////////////////////////////////////////
// Bypass registers can hold the following data
// 0 - swap data for CAS instructions
// 1 - load data for ASI ring operations
// 2 - RAW bypass data from STB
// 3 - load data for LSU ASI registers (non-STB)
// 4 - load data for LSU ASI registers (STB)
// 5 - parity update for STB CAM read
////////////////////////////////////////////////////////////////////////////////
// These come from the other side of LSU so buffer off the load of the eight muxes
lsu_lmd_dp_buff_macro__rep_1__width_64 st_data_buf (
.din (sbd_st_data_b[63:0]),
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_stb_ram_data (
.din (stb_ram_data[63:0]),
.dout (stb_ram_data_buf[63:0])
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_stb_asi_data (
.din (stb_ldxa_asi_data_w[63:0]),
.dout (stb_ldxa_asi_data_w_buf[63:0])
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_ard_pid_data (
.din (ard_pid_data[63:0]),
.dout (ard_pid_data_buf[63:0])
// Rebuffer for the load of the eight muxes
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_dcs_asi_data (
.din (dcs_ldxa_asi_data_w[63:0]),
.dout (dcs_ldxa_asi_data_w_buf[63:0])
lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp0 (
.scan_in(dff_ldbyp0_scanin),
.scan_out(dff_ldbyp0_scanout),
.din1 (ard_pid_data_buf[63:0]),
.din2 (stb_ram_data_buf[63:0]),
.din3 (dcs_ldxa_asi_data_w_buf[63:0]),
.din4 (stb_ldxa_asi_data_w_buf[63:0]),
.sel0 (lmc_lmq0_byp_sel[0]),
.sel1 (lmc_lmq0_byp_sel[1]),
.sel2 (lmc_lmq0_byp_sel[2]),
.sel3 (lmc_lmq0_byp_sel[3]),
.sel4 (lmc_lmq0_byp_sel[4]),
.dout (lmq0_bypass_data[63:0]),
.en (lmc_lmq_bypass_en[0]),
lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp1 (
.scan_in(dff_ldbyp1_scanin),
.scan_out(dff_ldbyp1_scanout),
.din1 (ard_pid_data_buf[63:0]),
.din2 (stb_ram_data_buf[63:0]),
.din3 (dcs_ldxa_asi_data_w_buf[63:0]),
.din4 (stb_ldxa_asi_data_w_buf[63:0]),
.sel0 (lmc_lmq1_byp_sel[0]),
.sel1 (lmc_lmq1_byp_sel[1]),
.sel2 (lmc_lmq1_byp_sel[2]),
.sel3 (lmc_lmq1_byp_sel[3]),
.sel4 (lmc_lmq1_byp_sel[4]),
.dout (lmq1_bypass_data[63:0]),
.en (lmc_lmq_bypass_en[1]),
lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp2 (
.scan_in(dff_ldbyp2_scanin),
.scan_out(dff_ldbyp2_scanout),
.din1 (ard_pid_data_buf[63:0]),
.din2 (stb_ram_data_buf[63:0]),
.din3 (dcs_ldxa_asi_data_w_buf[63:0]),
.din4 (stb_ldxa_asi_data_w_buf[63:0]),
.sel0 (lmc_lmq2_byp_sel[0]),
.sel1 (lmc_lmq2_byp_sel[1]),
.sel2 (lmc_lmq2_byp_sel[2]),
.sel3 (lmc_lmq2_byp_sel[3]),
.sel4 (lmc_lmq2_byp_sel[4]),
.dout (lmq2_bypass_data[63:0]),
.en (lmc_lmq_bypass_en[2]),
lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp3 (
.scan_in(dff_ldbyp3_scanin),
.scan_out(dff_ldbyp3_scanout),
.din1 (ard_pid_data_buf[63:0]),
.din2 (stb_ram_data_buf[63:0]),
.din3 (dcs_ldxa_asi_data_w_buf[63:0]),
.din4 (stb_ldxa_asi_data_w_buf[63:0]),
.sel0 (lmc_lmq3_byp_sel[0]),
.sel1 (lmc_lmq3_byp_sel[1]),
.sel2 (lmc_lmq3_byp_sel[2]),
.sel3 (lmc_lmq3_byp_sel[3]),
.sel4 (lmc_lmq3_byp_sel[4]),
.dout (lmq3_bypass_data[63:0]),
.en (lmc_lmq_bypass_en[3]),
lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp4 (
.scan_in(dff_ldbyp4_scanin),
.scan_out(dff_ldbyp4_scanout),
.din1 (ard_pid_data_buf[63:0]),
.din2 (stb_ram_data_buf[63:0]),
.din3 (dcs_ldxa_asi_data_w_buf[63:0]),
.din4 (stb_ldxa_asi_data_w_buf[63:0]),
.sel0 (lmc_lmq4_byp_sel[0]),
.sel1 (lmc_lmq4_byp_sel[1]),
.sel2 (lmc_lmq4_byp_sel[2]),
.sel3 (lmc_lmq4_byp_sel[3]),
.sel4 (lmc_lmq4_byp_sel[4]),
.dout (lmq4_bypass_data[63:0]),
.en (lmc_lmq_bypass_en[4]),
lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp5 (
.scan_in(dff_ldbyp5_scanin),
.scan_out(dff_ldbyp5_scanout),
.din1 (ard_pid_data_buf[63:0]),
.din2 (stb_ram_data_buf[63:0]),
.din3 (dcs_ldxa_asi_data_w_buf[63:0]),
.din4 (stb_ldxa_asi_data_w_buf[63:0]),
.sel0 (lmc_lmq5_byp_sel[0]),
.sel1 (lmc_lmq5_byp_sel[1]),
.sel2 (lmc_lmq5_byp_sel[2]),
.sel3 (lmc_lmq5_byp_sel[3]),
.sel4 (lmc_lmq5_byp_sel[4]),
.dout (lmq5_bypass_data[63:0]),
.en (lmc_lmq_bypass_en[5]),
lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp6 (
.scan_in(dff_ldbyp6_scanin),
.scan_out(dff_ldbyp6_scanout),
.din1 (ard_pid_data_buf[63:0]),
.din2 (stb_ram_data_buf[63:0]),
.din3 (dcs_ldxa_asi_data_w_buf[63:0]),
.din4 (stb_ldxa_asi_data_w_buf[63:0]),
.sel0 (lmc_lmq6_byp_sel[0]),
.sel1 (lmc_lmq6_byp_sel[1]),
.sel2 (lmc_lmq6_byp_sel[2]),
.sel3 (lmc_lmq6_byp_sel[3]),
.sel4 (lmc_lmq6_byp_sel[4]),
.dout (lmq6_bypass_data[63:0]),
.en (lmc_lmq_bypass_en[6]),
lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 dff_ldbyp7 (
.scan_in(dff_ldbyp7_scanin),
.scan_out(dff_ldbyp7_scanout),
.din1 (ard_pid_data_buf[63:0]),
.din2 (stb_ram_data_buf[63:0]),
.din3 (dcs_ldxa_asi_data_w_buf[63:0]),
.din4 (stb_ldxa_asi_data_w_buf[63:0]),
.sel0 (lmc_lmq7_byp_sel[0]),
.sel1 (lmc_lmq7_byp_sel[1]),
.sel2 (lmc_lmq7_byp_sel[2]),
.sel3 (lmc_lmq7_byp_sel[3]),
.sel4 (lmc_lmq7_byp_sel[4]),
.dout (lmq7_bypass_data[63:0]),
.en (lmc_lmq_bypass_en[7]),
// 0in bits_on -var lmc_thrd_byp_sel_m[7:0] -max 1
lsu_lmd_dp_mux_macro__dmux_4x__mux_aonpe__ports_8__stack_64c__width_64 ldbyp_data_mux (
.din0 (lmq0_bypass_data[63:0]),
.din1 (lmq1_bypass_data[63:0]),
.din2 (lmq2_bypass_data[63:0]),
.din3 (lmq3_bypass_data[63:0]),
.din4 (lmq4_bypass_data[63:0]),
.din5 (lmq5_bypass_data[63:0]),
.din6 (lmq6_bypass_data[63:0]),
.din7 (lmq7_bypass_data[63:0]),
.sel0 (lmc_thrd_byp_sel_m[0]),
.sel1 (lmc_thrd_byp_sel_m[1]),
.sel2 (lmc_thrd_byp_sel_m[2]),
.sel3 (lmc_thrd_byp_sel_m[3]),
.sel4 (lmc_thrd_byp_sel_m[4]),
.sel5 (lmc_thrd_byp_sel_m[5]),
.sel6 (lmc_thrd_byp_sel_m[6]),
.sel7 (lmc_thrd_byp_sel_m[7]),
.dout (bypass_data_m[63:0])
lsu_lmd_dp_buff_macro__rep_1__stack_64c__width_64 ldbyp_data_buf (
.din (bypass_data_m[63:0]),
.dout (lmd_bypass_data_m[63:0])
////////////////////////////////////////////////////////////////////////////////
// Normal fill data comes from cid. Diagnostic store data will come from the
////////////////////////////////////////////////////////////////////////////////
lsu_lmd_dp_msff_macro__width_64 dff_st_data_w (
.scan_in(dff_st_data_w_scanin),
.scan_out(dff_st_data_w_scanout),
.dout (diag_data_w[63:0]),
.en (dcc_cache_diag_wr_b),
lsu_lmd_dp_buff_macro__left_11__rep_1__stack_64c__width_29 diag_data_buf (
.din (diag_data_w[30:2]),
.dout (diag_data_w_buf[30:2])
lsu_lmd_dp_mux_macro__mux_aope__ports_3__width_64 mx_fill_data_hi (
.din0 (diag_data_w[63:0]),
.din1 (cid_fill_data_e[63:0]),
.din2 (cid_fill_data_e[127:64]),
.sel0 (cic_diag_data_sel_e),
.dout (fill_data_e[127:64])
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_fill_data_hi (
.din (fill_data_e[127:64]),
.dout (lmd_fill_data_e[127:64])
lsu_lmd_dp_mux_macro__mux_aope__ports_2__width_64 mx_fill_data_lo (
.din0 (diag_data_w[63:0]),
.din1 (cid_fill_data_e[63:0]),
.sel0 (cic_diag_data_sel_e),
.dout (fill_data_e[63:0])
lsu_lmd_dp_buff_macro__rep_1__width_64 buf_fill_data_lo (
.din (fill_data_e[63:0]),
.dout (lmd_fill_data_e[63:0])
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Select the correct dword for bypassing
lsu_lmd_dp_msff_macro__mux_aope__ports_2__width_64 byp_half_sel (
.scan_in(byp_half_sel_scanin),
.scan_out(byp_half_sel_scanout),
.din0 (cid_fill_data_e[127:64]),
.din1 (cid_fill_data_e[63:0]),
.dout (fill_data_m[63:0]),
.en (lmc_byp_data_enable),
lsu_lmd_dp_buff_macro__width_11 int_buf (
.din ({fill_data_m[15:14],fill_data_m[10:8],fill_data_m[5:0]}),
.dout ({lsu_ext_int_type[1:0],lsu_ext_int_tid[2:0],lsu_ext_int_vec[5:0]})
lsu_lmd_dp_mux_macro__mux_pgpe__ports_2__width_64 stgb_l2fd (
.din0 (fill_data_m[63:0]),
.din1 (lmd_bypass_data_m[63:0]),
.dout (lmd_fill_or_byp_data_m[63:0]),
lsu_lmd_dp_buff_macro__width_8 msb_buf (
.din ({lmd_fill_or_byp_data_m[63],lmd_fill_or_byp_data_m[55],
lmd_fill_or_byp_data_m[47],lmd_fill_or_byp_data_m[39],
lmd_fill_or_byp_data_m[31],lmd_fill_or_byp_data_m[23],
lmd_fill_or_byp_data_m[15],lmd_fill_or_byp_data_m[7]}),
.dout (lmd_misc_msb_m[7:0])
assign dff_lmq0_scanin = scan_in ;
assign dff_lmq1_scanin = dff_lmq0_scanout ;
assign dff_lmq2_scanin = dff_lmq1_scanout ;
assign dff_lmq3_scanin = dff_lmq2_scanout ;
assign dff_lmq4_scanin = dff_lmq3_scanout ;
assign dff_lmq5_scanin = dff_lmq4_scanout ;
assign dff_lmq6_scanin = dff_lmq5_scanout ;
assign dff_lmq7_scanin = dff_lmq6_scanout ;
assign dff_lmq_data_m_scanin = dff_lmq7_scanout ;
assign dff_ldbyp0_scanin = dff_lmq_data_m_scanout ;
assign dff_ldbyp1_scanin = dff_ldbyp0_scanout ;
assign dff_ldbyp2_scanin = dff_ldbyp1_scanout ;
assign dff_ldbyp3_scanin = dff_ldbyp2_scanout ;
assign dff_ldbyp4_scanin = dff_ldbyp3_scanout ;
assign dff_ldbyp5_scanin = dff_ldbyp4_scanout ;
assign dff_ldbyp6_scanin = dff_ldbyp5_scanout ;
assign dff_ldbyp7_scanin = dff_ldbyp6_scanout ;
assign dff_st_data_w_scanin = dff_ldbyp7_scanout ;
assign byp_half_sel_scanin = dff_st_data_w_scanout ;
assign scan_out = byp_half_sel_scanout ;
module lsu_lmd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
module lsu_lmd_dp_buff_macro__rep_1__stack_64c__width_40 (
module lsu_lmd_dp_buff_macro__dbuff_32x__rep_1__stack_24c__width_24 (
// parity macro (even parity)
module lsu_lmd_dp_prty_macro__width_32 (
module lsu_lmd_dp_inv_macro__width_8 (
// xor macro for ports = 2,3
module lsu_lmd_dp_xor_macro__ports_2__width_8 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_1 (
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 (
.so({so[62:0],scan_out}),
module lsu_lmd_dp_buff_macro__width_8 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__mux_aodec__ports_8__stack_6l__width_6 (
module lsu_lmd_dp_buff_macro__stack_6l__width_6 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module lsu_lmd_dp_cmp_macro__width_32 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module lsu_lmd_dp_cmp_macro__width_8 (
// and macro for ports = 2,3,4
module lsu_lmd_dp_and_macro__ports_3__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__mux_aonpe__ports_8__stack_64c__width_51 (
cl_dp1_muxbuff8_8x c0_0 (
module lsu_lmd_dp_buff_macro__stack_64c__width_51 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__stack_64c__width_2 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__dbuff_32x__dmux_4x__mux_aonpe__ports_8__stack_64c__width_15 (
cl_dp1_muxbuff8_32x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__mux_aodec__ports_8__width_45 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__left_11__mux_aope__ports_2__stack_64c__width_29 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__left_3__mux_aope__ports_2__stack_64c__width_40 (
module lsu_lmd_dp_buff_macro__width_45 (
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_msff_macro__stack_64c__width_25 (
.so({so[23:0],scan_out}),
module lsu_lmd_dp_buff_macro__rep_1__width_64 (
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_msff_macro__mux_aonpe__ports_5__stack_64c__width_64 (
cl_dp1_muxbuff5_8x c1_0 (
.so({so[62:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__dmux_4x__mux_aonpe__ports_8__stack_64c__width_64 (
cl_dp1_muxbuff8_8x c0_0 (
module lsu_lmd_dp_buff_macro__rep_1__stack_64c__width_64 (
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_msff_macro__width_64 (
.so({so[62:0],scan_out}),
module lsu_lmd_dp_buff_macro__left_11__rep_1__stack_64c__width_29 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__mux_aope__ports_3__width_64 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__mux_aope__ports_2__width_64 (
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_msff_macro__mux_aope__ports_2__width_64 (
.so({so[62:0],scan_out}),
module lsu_lmd_dp_buff_macro__width_11 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_lmd_dp_mux_macro__mux_pgpe__ports_2__width_64 (