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// OpenSPARC T2 Processor File: lsu_rep_dp.v
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lmd_fill_or_byp_data_m_rep1,
exu_lsu_store_data_e_rep0,
wire [63:0] lmd_fill_or_byp_data_m_rep0;
input [63:0] lmd_fill_or_byp_data_m;
output [63:0] lmd_fill_or_byp_data_m_rep1;
input [63:0] stb_ram_data;
output [63:0] stb_ram_data_rep0;
input [44:0] stb_cam_data;
output [44:0] stb_cam_data_rep0;
input [63:0] sbd_st_data2_b;
output [63:0] sbd_st_data2_b_rep0;
input [47:0] sbd_st_predata_b;
output [47:0] sbd_st_predata_b_rep0;
input [7:0] bist_cmp_data;
output [7:0] bist_cmp_data_rep0;
output tlb_tte_ie_b_rep00;
output tlb_tte_ie_b_rep01;
input [3:0] tlb_cache_way_hit_b;
output [3:0] cache_way_hit_top_b;
output [3:0] cache_way_hit_bot_b;
input [63:0] exu_lsu_store_data_e;
output [63:0] exu_lsu_store_data_e_rep0;
input [10:4] exu_lsu_address_e;
output [10:4] exu_lsu_address_e_rep0;
lsu_rep_dp_buff_macro__rep_1__width_64 fill_or_byp_data_rep0 (
.din (lmd_fill_or_byp_data_m[63:0]),
.dout (lmd_fill_or_byp_data_m_rep0[63:0])
lsu_rep_dp_buff_macro__rep_1__width_64 fill_or_byp_data_rep1 (
.din (lmd_fill_or_byp_data_m_rep0[63:0]),
.dout (lmd_fill_or_byp_data_m_rep1[63:0])
// STB RAM read data (flopped)
lsu_rep_dp_buff_macro__rep_1__stack_32c__width_32 i0_stb_ram_data_rep0 (
.din (stb_ram_data[63:32]),
.dout (stb_ram_data_rep0[63:32])
lsu_rep_dp_buff_macro__rep_1__stack_32c__width_32 i1_stb_ram_data_rep0 (
.din (stb_ram_data[31:0]),
.dout (stb_ram_data_rep0[31:0])
lsu_rep_dp_buff_macro__rep_1__width_45 i_stb_cam_data_rep0 (
.din (stb_cam_data[44:0]),
.dout (stb_cam_data_rep0[44:0])
// Prealigned data from store buffer
lsu_rep_dp_buff_macro__rep_1__width_48 st_predata_b_rep0 (
.din (sbd_st_predata_b[47:0]),
.dout (sbd_st_predata_b_rep0[47:0])
// Aligned data from store buffer
lsu_rep_dp_buff_macro__rep_1__width_64 st_data2_b_rep0 (
.din (sbd_st_data2_b[63:0]),
.dout (sbd_st_data2_b_rep0[63:0])
lsu_rep_dp_buff_macro__rep_1__width_8 i_bist_cmp_data_rep0 (
.din (bist_cmp_data[7:0]),
.dout (bist_cmp_data_rep0[7:0])
lsu_rep_dp_buff_macro__rep_1__width_1 tte_ie_rep00 ( // to sbs
.dout (tlb_tte_ie_b_rep00)
lsu_rep_dp_buff_macro__rep_1__width_1 tte_ie_rep01 ( // to dcc
.dout (tlb_tte_ie_b_rep01)
// stb_cam_hit; very critical to dcc, buffer off load to lmc
lsu_rep_dp_buff_macro__rep_1__width_1 i_stb_cam_hit_rep0 ( // to dcc
// one copy of cache_way_hit goes up, one goes down
lsu_rep_dp_buff_macro__rep_1__width_4 i_cache_way_hit_top ( // to dac
.din (tlb_cache_way_hit_b[3:0]),
.dout (cache_way_hit_top_b[3:0])
lsu_rep_dp_buff_macro__rep_1__width_4 i_cache_way_hit_bot ( // to dcc
.din (tlb_cache_way_hit_b[3:0]),
.dout (cache_way_hit_bot_b[3:0])
lsu_rep_dp_buff_macro__rep_1__width_64 store_data_rep0 (
.din (exu_lsu_store_data_e[63:0]),
.dout (exu_lsu_store_data_e_rep0[63:0])
lsu_rep_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_7 exu_address_rep0 (
.din (exu_lsu_address_e[10:4]),
.dout (exu_lsu_address_e_rep0[10:4])
module lsu_rep_dp_buff_macro__rep_1__width_64 (
module lsu_rep_dp_buff_macro__rep_1__stack_32c__width_32 (
module lsu_rep_dp_buff_macro__rep_1__width_45 (
module lsu_rep_dp_buff_macro__rep_1__width_48 (
module lsu_rep_dp_buff_macro__rep_1__width_8 (
module lsu_rep_dp_buff_macro__rep_1__width_1 (
module lsu_rep_dp_buff_macro__rep_1__width_4 (
module lsu_rep_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_7 (