design/sys/synopsys/script/run.scr

# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: run.scr
# Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
# 4150 Network Circle, Santa Clara, California 95054, U.S.A.
#
# * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
#
# For the avoidance of doubt, and except that if any non-GPL license
# choice is available it will apply instead, Sun elects to use only
# the General Public License version 2 (GPLv2) at this time for any
# software where a choice of GPL license versions is made
# available with the language indicating that GPLv2 or any later version
# may be used, or where a choice of which version of the GPL is applied is
# otherwise unspecified.
#
# Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
# CA 95054 USA or visit www.sun.com if you need additional information or
# have any questions.
#
# ========== Copyright Header End ============================================
sh date
sh hostname
sh uptime

remove_design -all

if {[file exists template]} {
   sh rm -rf template
}
sh mkdir template
if {![file exists gate]} {
   sh mkdir gate
}
if {![file exists log]} {
   sh mkdir log
}

###########################################################################
# 1. Setup from environment variables
###########################################################################

set dv_root [sh echo \$DV_ROOT]
set syn_home [sh echo \$SYN_LIB]

source -echo -verbose script/user_cfg.scr

set search_path [concat $search_path script/]

set search_path [concat $syn_home \
   $search_path ]

foreach include_path $include_paths {
   set search_path [concat $search_path $dv_root/$include_path]
}

sh date

set link_library [concat $link_library \
                         $mem_libs \
                         $black_box_designs]

set target_library $syn_home/lsi_10k.db

set target_library [concat $target_library \
                           $mem_libs]
set hdlin_enable_vpp true
set hdlin_auto_save_templates false
define_design_lib WORK -path .template
set verilogout_single_bit false
set hdlout_internal_busses true
set bus_naming_style {%s[%d]}
set bus_inference_style $bus_naming_style

echo $search_path


###########################################################################
# 2. Read Designs
###########################################################################

set all_rtl_files  { }
foreach rtl_file $rtl_files {
    set full_file_path $dv_root/$rtl_file
    set all_rtl_files [concat $all_rtl_files $full_file_path ]
}

    analyze -format verilog -define RUNDC $all_rtl_files
    elaborate $top_module

#####

if {[info exists mix_files] && ($mix_files != {}) } {
   foreach mix_file $mix_files {
      set index_beg [expr {[string last "/" $mix_file] + 1}]
      set mix_file_name [string range $mix_file $index_beg end]
      read_file -format verilog -define RUNDC gate/${mix_file_name}.exp
   }
}
set design_list [list]
foreach_in_collection design_object [get_designs] {
   set design_name [get_object_name $design_object]
   lappend design_list $design_name
}
sh date
current_design $top_module

echo $top_module

if {[get_designs -hier $dont_touch_modules] != {}} {
   set_dont_touch $dont_touch_modules
}

set dc_shell_status [ link ]
if {$dc_shell_status == 0} {
   echo "****************************************************"
   echo "* ERROR!!!! Failed to Link...exiting prematurely.  *"
   echo "****************************************************"
   quit
}

###########################################################################
# 3. Set up design constraints
###########################################################################

current_design $top_module
echo $top_module
set clk_name_list [list]
set ideal_inputs [list]
foreach clk_spec $clk_list {
   set listcnt 0
   set clk_port_pin {}
   set clk_name {}
   set clk_freq 0.0
   set setup_skew $default_setup_skew
   set hold_skew  $default_hold_skew
   set clock_transition  $default_clk_transition
   set clk_is_port 1
   foreach element $clk_spec {
      if {$listcnt == 0} {
         set clk_port_pin $element
         set clk_name $element
      }
      if {$listcnt == 1} {
         set clk_freq $element
      }
      if {$listcnt == 2} {
         set setup_skew $element
      }
      if {$listcnt == 3} {
         set hold_skew $element
      }
      if {$listcnt == 4} {
         set clock_transition $element
      }
      if {$listcnt == 5} {
         set clk_name $element
         set clk_is_port 0
      }
      set listcnt [expr $listcnt + 1]
   }
   if {$clk_is_port == 1} {
      set clk_exists [sizeof_collection [find port $clk_port_pin]]
   } else {
      set clk_exists [sizeof_collection [find pin $clk_port_pin]]
   }
   if {$clk_exists != 0} {
      set clk_period [expr 1000.0 / $clk_freq / 1.0]
      set high_time [expr $clk_period / 2.0]
      create_clock $clk_port_pin -period $clk_period -waveform [list 0 $high_time] -name $clk_name
      set_clock_uncertainty -setup $setup_skew [find clock $clk_name]
      set_clock_uncertainty -hold $hold_skew [find clock $clk_name]
      set_clock_transition $clock_transition [find clock $clk_name]
      set_dont_touch_network $clk_name
      if {$clk_is_port == 1} {
         set_drive 0.0 $clk_name
         lappend ideal_inputs $clk_name
      }
      set clk_name_list [concat  $clk_name_list $clk_name]
   }
}
if {$clk_name_list == {} } {
   echo "\[WARNING\] No clock is defined,create a virtual one -- $default_clk..."
   set clk_name $default_clk
   set clk_freq $default_clk_freq
   set clk_period [expr 1000.0 / $clk_freq / 1.0]
   set high_time [expr $clk_period / 2.0]
   set setup_skew $default_setup_skew
   set hold_skew  $default_hold_skew
   set clock_transition  $default_clk_transition
   create_clock -name $clk_name -period $clk_period -waveform [list 0 $high_time]
   set_clock_uncertainty -setup $setup_skew $clk_name
   set_clock_uncertainty -hold $hold_skew $clk_name
}
set non_ideal_inputs [list]
foreach_in_collection input_object [all_inputs] {
   set input_name [get_object_name $input_object]
   set input_is_ideal [lsearch -exact $ideal_net_list $input_name]
   if {$input_is_ideal == -1} {
      lappend non_ideal_inputs $input_name
   } else {
      lappend ideal_inputs $input_name
   }
}

echo $ideal_inputs
echo $non_ideal_inputs

set_input_delay $default_input_delay -clock $clk_name $non_ideal_inputs
set_output_delay $default_output_delay -clock $clk_name [all_outputs]

if {$clk_name_list != {} } {
   group_path -name "reg2reg" -critical_range $critical_range -from [ all_registers -clock_pins ] -to [ all_registers -data_pins ]
   group_path -name "in2reg"  -from $non_ideal_inputs -to [ all_registers -data_pins ]
   group_path -name "reg2out" -from [ all_registers -clock_pins ] -to [all_outputs]
}
   group_path -name "in2out"  -from $non_ideal_inputs -to [all_outputs]
if {[info exists false_path_list] && ($false_path_list != {}) } {
        set_false_path -through $false_path_list
}

if {[info exists enforce_input_fanout_one] && ($enforce_input_fanout_one  == 1)} {
   set_max_fanout 1 $non_ideal_inputs
}

# Load custom constraint file for the unit
# This will overwrite the default constraints


###########################################################################
# 4. More constraints and setup before compile
###########################################################################
# This is to prevent assign statements from generated in the netlist
# Certain rtl coding conventions need to be followed. For IO blocks only
# write_name_nets_same_as_ports
if {[info exists project_io_cfg] && ($project_io_cfg == 1) } {
   foreach_in_collection design [ get_designs "*" ] {
      current_design $design
      set_fix_multiple_port_nets -outputs -feedthroughs
   }
   current_design $top_module
}

# Check timing constraints


###########################################################################
# 5. Compile
###########################################################################

# Disable cells that we don't want to use in the library
if {$dont_use_cells != 0} {
   if {[info exists my_dont_use_cell_list] && ($my_dont_use_cell_list != {}) } {
      set dont_use_cell_list [concat $dont_use_cell_list $my_dont_use_cell_list]
   }
   foreach dont_use_cell $dont_use_cell_list {
      set_dont_use [find lib_cell $dont_use_cell]
   }
}

sh date
sh uptime

# Don't remove sequential cells with constant outputs
set compile_seqmap_propagate_constants false

# Switch off the dont_touch attribute globally for set_size_only cells
set dont_touch_nets_with_size_only_cells false

## Source user compile options

   #if set to 1, the whole design will be flattened. default 1 for cmp
   if {[info exists compile_flatten_all] && ($compile_flatten_all  == 1)} {
      ungroup -flatten -all
   }

   # compile !!
   if {[info exists project_io_cfg] && ($project_io_cfg == 1) } {
      set dc_shell_status [ compile -boundary_optimization -exact_map -map_effort $compile_effort ]
   }

   if {[info exists project_sparc_cfg] && ($project_sparc_cfg == 1) } {
      if {[info exists use_physopt] && ($use_physopt == 1)} {
         set_fix_multiple_port_nets -all -buffer_constants
      }
      set dc_shell_status [ compile -boundary_optimization -exact_map -map_effort $compile_effort ]
   }

   if {$dc_shell_status == 0} {
      echo "*******************************************************"
      echo "* ERROR!!!! Failed to compile...exiting prematurely.  *"
      echo "*******************************************************"
      quit
   }

sh date

###########################################################################
# 6. Insert Scan - Hook up the scan chain.
###########################################################################
if {[info exists use_physopt] && ($use_physopt == 1)} {
   set skip_scan 1
}
if {[info exists skip_scan] && ($skip_scan == 1)} {
   ######  skip section 5e.
} else {

current_design $top_module

## Tell DC the design is "scan ready"
## We do this because we already instantiate scan flops in the rtl
set_attribute $top_module is_test_ready true -type boolean
foreach_in_collection design_object [get_designs] {
   current_design $design_object
   # make sure the module has FFs in it to prevent warning messages
   if { [all_registers] != {} } {
      set_attribute [all_registers] scanned_by_test_compiler true -type boolean
   }
}

current_design $top_module


# Tell DC not to optimize away spare FF's
set compile_delete_unloaded_sequential_cells false

# Disable cells that we don't want to use in the library
if {$dont_use_cells != 0} {
   foreach dont_use_cell $dont_use_cell_list {
      set_dont_use [find lib_cell $dont_use_cell]
   }
}

# Insert scan chain with number of chains specified by user
# Allow scan chain to hook up flops clocked by different clocks
# Add lockup latches between clock domains
set_scan_configuration -add_lockup $add_lockup_latch -chain_count $chain_count -clock_mixing mix_clocks

# This should prevent assign statements from generated in the netlist
# at the cost of extra compile time. For cmp only
if {[info exists project_sparc_cfg] && ($project_sparc_cfg == 1) } {
   foreach_in_collection design [ get_designs "*" ] {
      current_design $design
      set_fix_multiple_port_nets -all -buffer_constants
   }

   current_design $top_module

   # allow_outport_drive_innodes is used by sparc units but not IO units
   # set this switch to 0 to make sure output port doesn't driving internal nodes
   if {[info exists allow_outport_drive_innodes] && ($allow_outport_drive_innodes == 0)} {
      set_isolate_ports -type inverter [all_outputs]
   }

   current_design $top_module
   compile -inc
}


### section 5e. will be skipped if user want to use PC flow
}


###########################################################################
# 7. Write Out netlist
###########################################################################

# Remove don't touch modules from the design
# It caused unmatching hierarchy between rtl and netlist
if { [get_designs -hier $dont_touch_modules] != {} } {
   remove_design $dont_touch_modules
}

# remove dont_touch attribute before flattening the design
if { [get_designs -hier $dont_touch_modules] != {} } {
   set_dont_touch $dont_touch_modules false
}

current_design $top_module
ungroup -all -flatten

# Make sure flat netlist does not have "/" in signal names
define_name_rules hier_change -restricted "/" -replacement_char "_"
change_names -rule hier_change -hierarchy

# Write out netlist.
write -format verilog -output [format "%s%s%s"  gate/ $top_module .vSyn]

# Report flattened results
redirect [format "%s%s%s" log/ $top_module _area.rep] { report_area }
redirect -append [format "%s%s%s" log/ $top_module _area.rep] { report_reference }


###########################################################################
# 8. Check design and Detect unmapped design
###########################################################################

set unmapped_designs [get_designs -filter "is_unmapped == true" $top_module]

if {  [sizeof_collection $unmapped_designs] != 0 } {
   echo "****************************************************"
   echo "* ERROR!!!! Compile finished with unmapped logic.  *"
   echo "****************************************************"
   quit
}


###########################################################################
# 9. Done
###########################################################################
sh date

echo "run.scr completed successfully"

quit