// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: cl_u1.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi12_16x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi12_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Dec 6,2001 at 02:09:00 PM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi12_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi12_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi12_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Nov 29,2001 at 11:51:25 AM PST
// --------------------------------------------------
assign out = ~(( in10 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi21_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_u1_aoi21_16x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_u1_aoi21_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_u1_aoi21_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_u1_aoi21_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_u1_aoi21_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:15 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 ));
// --------------------------------------------------
// File: cl_u1_aoi22_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:16 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi22_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:32 PM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi22_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:16 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi22_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:16 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi22_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:16 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 ) | ( in00 & in01 ));
// --------------------------------------------------
// File: cl_u1_aoi33_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Thursday Dec 6,2001 at 02:09:02 PM PST
// --------------------------------------------------
assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
// --------------------------------------------------
// File: cl_u1_aoi33_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:18 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
// --------------------------------------------------
// File: cl_u1_aoi33_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:18 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
// --------------------------------------------------
// File: cl_u1_aoi33_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:18 AM PDT
// --------------------------------------------------
assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 ));
module cl_u1_rep_lvt_32x (
module cl_u1_rep_lvt_48x (
module cl_u1_rep_dcp2x_32x (
module cl_u1_rep_dcp2x_16x (
module cl_u1_rep_dcp2x_24x (
module cl_u1_rep_dcp2x_40x (
module cl_u1_rep_dcp2x_48x (
module cl_u1_rep_dcp_32x (
module cl_u1_rep_dcp_16x (
module cl_u1_rep_dcp_24x (
module cl_u1_rep_dcp_40x (
module cl_u1_rep_dcp_48x (
module cl_u1_rep_dcp50k_48x (
module cl_u1_rep_dcp50k_32x (
module cl_u1_rep_dcp50k_40x (
module cl_u1_bufmin_15ps_32x (
module cl_u1_bufmin_16x (
module cl_u1_bufmin_32x (
assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2);
assign sum = (in0 ^ in1 ^ in2);
assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2);
assign sum = (in0 ^ in1 ^ in2);
assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2);
assign sum = (in0 ^ in1 ^ in2);
assign cout = (in1 & in2) | (in0 & in2) | (in0 & in1);
assign sum = (~in0 & ~in1 & ~in2 & ~in3 & cin) |
(~in0 & ~in1 & ~in2 & in3 & ~cin) |
(~in0 & ~in1 & in2 & ~in3 & ~cin) |
(~in0 & ~in1 & in2 & in3 & cin) |
(~in0 & in1 & ~in2 & ~in3 & ~cin) |
(~in0 & in1 & ~in2 & in3 & cin) |
(~in0 & in1 & in2 & ~in3 & cin) |
(~in0 & in1 & in2 & in3 & ~cin) |
( in0 & ~in1 & ~in2 & ~in3 & ~cin) |
( in0 & ~in1 & ~in2 & in3 & cin) |
( in0 & ~in1 & in2 & ~in3 & cin) |
( in0 & ~in1 & in2 & in3 & ~cin) |
( in0 & in1 & ~in2 & ~in3 & cin) |
( in0 & in1 & ~in2 & in3 & ~cin) |
( in0 & in1 & in2 & ~in3 & ~cin) |
( in0 & in1 & in2 & in3 & cin);
assign carry = (~in0 & ~in1 & ~in2 & ~in3 & 1'b0) |
(~in0 & ~in1 & ~in2 & in3 & cin) |
(~in0 & ~in1 & in2 & ~in3 & cin) |
(~in0 & ~in1 & in2 & in3 & 1'b1) |
(~in0 & in1 & ~in2 & ~in3 & cin) |
(~in0 & in1 & ~in2 & in3 & 1'b1) |
(~in0 & in1 & in2 & ~in3 & 1'b0) |
(~in0 & in1 & in2 & in3 & cin) |
( in0 & ~in1 & ~in2 & ~in3 & cin) |
( in0 & ~in1 & ~in2 & in3 & 1'b1) |
( in0 & ~in1 & in2 & ~in3 & 1'b0) |
( in0 & ~in1 & in2 & in3 & cin) |
( in0 & in1 & ~in2 & ~in3 & 1'b0) |
( in0 & in1 & ~in2 & in3 & cin) |
( in0 & in1 & in2 & ~in3 & cin) |
( in0 & in1 & in2 & in3 & 1'b1);
assign cout = (in1 & in2) | (in0 & in2) | (in0 & in1);
assign sum = (~in0 & ~in1 & ~in2 & ~in3 & cin) |
(~in0 & ~in1 & ~in2 & in3 & ~cin) |
(~in0 & ~in1 & in2 & ~in3 & ~cin) |
(~in0 & ~in1 & in2 & in3 & cin) |
(~in0 & in1 & ~in2 & ~in3 & ~cin) |
(~in0 & in1 & ~in2 & in3 & cin) |
(~in0 & in1 & in2 & ~in3 & cin) |
(~in0 & in1 & in2 & in3 & ~cin) |
( in0 & ~in1 & ~in2 & ~in3 & ~cin) |
( in0 & ~in1 & ~in2 & in3 & cin) |
( in0 & ~in1 & in2 & ~in3 & cin) |
( in0 & ~in1 & in2 & in3 & ~cin) |
( in0 & in1 & ~in2 & ~in3 & cin) |
( in0 & in1 & ~in2 & in3 & ~cin) |
( in0 & in1 & in2 & ~in3 & ~cin) |
( in0 & in1 & in2 & in3 & cin);
assign carry = (~in0 & ~in1 & ~in2 & ~in3 & 1'b0) |
(~in0 & ~in1 & ~in2 & in3 & cin) |
(~in0 & ~in1 & in2 & ~in3 & cin) |
(~in0 & ~in1 & in2 & in3 & 1'b1) |
(~in0 & in1 & ~in2 & ~in3 & cin) |
(~in0 & in1 & ~in2 & in3 & 1'b1) |
(~in0 & in1 & in2 & ~in3 & 1'b0) |
(~in0 & in1 & in2 & in3 & cin) |
( in0 & ~in1 & ~in2 & ~in3 & cin) |
( in0 & ~in1 & ~in2 & in3 & 1'b1) |
( in0 & ~in1 & in2 & ~in3 & 1'b0) |
( in0 & ~in1 & in2 & in3 & cin) |
( in0 & in1 & ~in2 & ~in3 & 1'b0) |
( in0 & in1 & ~in2 & in3 & cin) |
( in0 & in1 & in2 & ~in3 & cin) |
( in0 & in1 & in2 & in3 & 1'b1);
assign cout = (in1 & in2) | (in0 & in2) | (in0 & in1);
assign sum = (~in0 & ~in1 & ~in2 & ~in3 & cin) |
(~in0 & ~in1 & ~in2 & in3 & ~cin) |
(~in0 & ~in1 & in2 & ~in3 & ~cin) |
(~in0 & ~in1 & in2 & in3 & cin) |
(~in0 & in1 & ~in2 & ~in3 & ~cin) |
(~in0 & in1 & ~in2 & in3 & cin) |
(~in0 & in1 & in2 & ~in3 & cin) |
(~in0 & in1 & in2 & in3 & ~cin) |
( in0 & ~in1 & ~in2 & ~in3 & ~cin) |
( in0 & ~in1 & ~in2 & in3 & cin) |
( in0 & ~in1 & in2 & ~in3 & cin) |
( in0 & ~in1 & in2 & in3 & ~cin) |
( in0 & in1 & ~in2 & ~in3 & cin) |
( in0 & in1 & ~in2 & in3 & ~cin) |
( in0 & in1 & in2 & ~in3 & ~cin) |
( in0 & in1 & in2 & in3 & cin);
assign carry = (~in0 & ~in1 & ~in2 & ~in3 & 1'b0) |
(~in0 & ~in1 & ~in2 & in3 & cin) |
(~in0 & ~in1 & in2 & ~in3 & cin) |
(~in0 & ~in1 & in2 & in3 & 1'b1) |
(~in0 & in1 & ~in2 & ~in3 & cin) |
(~in0 & in1 & ~in2 & in3 & 1'b1) |
(~in0 & in1 & in2 & ~in3 & 1'b0) |
(~in0 & in1 & in2 & in3 & cin) |
( in0 & ~in1 & ~in2 & ~in3 & cin) |
( in0 & ~in1 & ~in2 & in3 & 1'b1) |
( in0 & ~in1 & in2 & ~in3 & 1'b0) |
( in0 & ~in1 & in2 & in3 & cin) |
( in0 & in1 & ~in2 & ~in3 & 1'b0) |
( in0 & in1 & ~in2 & in3 & cin) |
( in0 & in1 & in2 & ~in3 & cin) |
( in0 & in1 & in2 & in3 & 1'b1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 & in1 & in2 & in3);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1);
assign out = ~(in0 | in1 | in2);
assign out = ~(in0 | in1 | in2);
assign out = ~(in0 | in1 | in2);
// --------------------------------------------------
// File: cl_u1_oai12_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai12_16x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai12_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai12_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai12_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai12_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:34 PM PDT
// --------------------------------------------------
assign out = ~(( in10 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai21_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_u1_oai21_16x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_u1_oai21_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Friday Mar 15,2002 at 02:53:58 PM PST
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_u1_oai21_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:23 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_u1_oai21_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:23 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_u1_oai21_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:23 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 ));
// --------------------------------------------------
// File: cl_u1_oai22_12x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai22_16x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai22_1x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Wednesday May 29,2002 at 04:04:35 PM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai22_2x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:24 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai22_4x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:24 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
// --------------------------------------------------
// File: cl_u1_oai22_8x.behV
// Auto generated verilog module by HnBCellAuto
// Created: Monday Oct 8,2001 at 11:32:24 AM PDT
// --------------------------------------------------
assign out = ~(( in10 | in11 ) & ( in00 | in01 ));
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1);
assign out = ~(in0 ^ in1 ^ in2);
assign out = ~(in0 ^ in1 ^ in2);
assign out = ~(in0 ^ in1 ^ in2);
assign out = ~(in0 ^ in1 ^ in2);
assign out = ~(in0 ^ in1 ^ in2);
assign out = ~(in0 ^ in1 ^ in2);
assign out = in0 ^ in1 ^ in2;
assign out = in0 ^ in1 ^ in2;
assign out = in0 ^ in1 ^ in2;
assign out = in0 ^ in1 ^ in2;
assign out = in0 ^ in1 ^ in2;
assign out = in0 ^ in1 ^ in2;
reg chop_aclk, chop_bclk;
always @(posedge tck) begin
always @(negedge tck) begin
module cl_u1_muxprotect_2x (
assign e0 = scan_en | d0;
assign e1= ~scan_en & d1;
assign e2= ~scan_en & d2;
assign e3= ~scan_en & d3;