// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: n2_com_64x132async_dp_cust_array.v
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module n2_com_64x132async_dp_cust_array (
input wr_clk; // write clk
input [5:0] wr_addr_array; // write port address in
input wr_en_array; // write port enable
input [131:0] din_array; // data in
input rd_clk; // read clk
input [5:0] rd_addr_array; // read port address in
input rd_en_array; // read port enable
output [131:0] dout_array; // data out
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// checker to verify on accesses's that no bits are x
// 0in kndr -var rd_addr_array
// 0in kndr -var wr_addr_array
// 0in kndr -var rd_en_array
// 0in kndr -var wr_en_array
reg [131:0] array_ram [0:63];
for (i=0; i<64; i=i+1) begin
dout_array[131:0] = 132'b0; // N2+ Bug 103693
// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
always @(rd_clk or rd_en_array or rd_addr_array ) begin
dout_array[131:0] <= array_ram[rd_addr_array[5:0]];
always @(rd_clk or rd_en_array or rd_addr_array or wr_en_array or
if (wr_en_array & (rd_addr_array == wr_addr_array)) // 0in < fire -severity 1 -message "Detected rd/wr collision in PEU I/EHB RAM, dout driven as X's" -group mbist_mode
dout_array[131:0] <= {132{1'bx}} ;
dout_array[131:0] <= array_ram[rd_addr_array[5:0]];
// ----------------------------------------------------------------------------
// Write the array, note: it is written when the clock is low
// ----------------------------------------------------------------------------
always @(wr_en_array or wr_addr_array or wr_clk or din_array ) begin
array_ram[wr_addr_array[5:0]] <= din_array[131:0];
endmodule // n2_com_64x132async_dp_cust_array