// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: n2_com_dp_64x84_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
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// ========== Copyright Header End ============================================
module n2_com_dp_64x84_cust (
wire dff_wr_addr_scanout;
wire [5:1] dff_rd_addr_scan;
wire dff_rd_addr_scanout;
wire [5:0] rd_adr_mq_l_unused;
wire [5:0] rd_adr_q_unused;
wire [5:0] rd_adr_q_l_unused;
wire [41:1] dff_din_hi_scan;
wire [41:1] dff_din_lo_scan;
input tcu_array_wr_inhibit;
input tcu_se_scancollar_in;
// synopsys translate_off
wire pce_ov = tcu_pce_ov;
//================================================
//================================================
cl_mc1_bistlatch_4x rd_pce_lat (
cl_mc1_bistlatch_4x wr_pce_lat (
cl_mc1_bistl1hdr_8x rch_in (
.se (tcu_se_scancollar_in),
.clksel (bist_clk_mux_sel),
cl_mc1_bistl1hdr_8x wch_in (
.se (tcu_se_scancollar_in),
.clksel (bist_clk_mux_sel),
cl_mc1_bistl1hdr_8x rch_free (
.clksel (bist_clk_mux_sel),
cl_mc1_bistl1hdr_8x wch_free (
.clksel (bist_clk_mux_sel),
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
n2_com_dp_64x84_cust_msff_ctl_macro__width_6 dff_wr_addr (
.scan_in (dff_wr_addr_scanin),
.scan_out (dff_wr_addr_scanout),
n2_com_dp_64x84_cust_sram_msff_mo_macro__fs_1__width_6 dff_rd_addr (
.scan_in ({dff_rd_addr_scan[5:1],dff_rd_addr_scanin}),
.scan_out ({dff_rd_addr_scanout,dff_rd_addr_scan[5:1]}),
.mq_l (rd_adr_mq_l_unused[5:0]),
.q (rd_adr_q_unused[5:0]),
.q_l (rd_adr_q_l_unused[5:0]),
n2_com_dp_64x84_cust_sram_msff_mo_macro__width_1 dff_rd_en (
.scan_in (dff_rd_en_scanin),
.scan_out (dff_rd_en_scanout),
.mq_l (rd_en_mq_l_unused),
n2_com_dp_64x84_cust_msff_ctl_macro__width_1 dff_wr_en (
.scan_in (dff_wr_en_scanin),
.scan_out (dff_wr_en_scanout),
n2_com_dp_64x84_cust_msff_ctl_macro__fs_1__width_42 dff_din_hi (
.scan_in ({dff_din_hi_scan[41:1],dff_din_hi_scanin}),
.scan_out ({dff_din_hi_scanout,dff_din_hi_scan[41:1]}),
n2_com_dp_64x84_cust_msff_ctl_macro__fs_1__width_42 dff_din_lo (
.scan_in ({dff_din_lo_scan[41:1],dff_din_lo_scanin}),
.scan_out ({dff_din_lo_scanout,dff_din_lo_scan[41:1]}),
n2_com_dp_64x84_cust_inv_macro__width_1 wr_inh_inv (
.din (tcu_array_wr_inhibit),
n2_com_dp_64x84_cust_and_macro__width_2 enable_qual (
.din1 ({rd_en_d1,wr_en_d1}),
.dout ({rd_en_d1_qual,wr_en_d1_qual})
n2_com_dp_64x84_cust_n2_com_array_macro__rows_64__width_84__z_array array (
.wr_adr (wr_adr_d1[5:0]),
.rd_adr (rd_adr_d1[5:0]),
assign dout[83:0] = local_dout[83:0];
assign dff_dout_scanout = dff_dout_scanin;
assign dff_wr_addr_scanin = scan_in ;
assign dff_rd_addr_scanin = dff_wr_addr_scanout ;
assign dff_wr_en_scanin = dff_rd_addr_scanout ;
assign dff_rd_en_scanin = dff_wr_en_scanout ;
assign dff_din_lo_scanin = dff_rd_en_scanout ;
assign dff_din_hi_scanin = dff_din_lo_scanout ;
assign dff_dout_scanin = dff_din_hi_scanout ;
assign scan_out = dff_dout_scanout ;
// any PARAMS parms go into naming of macro
module n2_com_dp_64x84_cust_msff_ctl_macro__width_6 (
assign fdin[5:0] = din[5:0];
// macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
module n2_com_dp_64x84_cust_sram_msff_mo_macro__fs_1__width_6 (
//place::generic_place($width,$stack,$left);
// macro for cl_mc1_sram_msff_mo_{16,8,4}x flops
module n2_com_dp_64x84_cust_sram_msff_mo_macro__width_1 (
//place::generic_place($width,$stack,$left);
// any PARAMS parms go into naming of macro
module n2_com_dp_64x84_cust_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module n2_com_dp_64x84_cust_msff_ctl_macro__fs_1__width_42 (
assign fdin[41:0] = din[41:0];
module n2_com_dp_64x84_cust_inv_macro__width_1 (
// and macro for ports = 2,3,4
module n2_com_dp_64x84_cust_and_macro__width_2 (
module n2_com_dp_64x84_cust_n2_com_array_macro__rows_64__width_84__z_array (
reg [84-1:0] mem[64-1:0];
for (i=0; i<64; i=i+1) begin
always @(negedge wclk) begin
always @(rclk or rd_en or wr_en or rd_adr or wr_adr) begin
if (wr_en & (wr_adr[5:0] == rd_adr[5:0]))
local_dout[84-1:0] <= 84'hx;
local_dout[84-1:0] <= mem[rd_adr] ;
local_dout[84-1:0] <= ~(84'h0);
assign dout[84-1:0] = local_dout[84-1:0];