// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: n2_l2d_dmux78_cust.v
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module n2_l2d_dmux78_cust (
output [7:0] waysel_top_c4;
output [7:0] waysel_bot_c4;
output [8:0] set_top_c3b; // Set 8 will be inverted for top/bot
output [8:0] set_bot_c3b; // Set 8 will be inverted for top/bot
//output coloff_top_c4_l ;
//output coloff_bot_c4_l;
//output [1:0] coloff_top_c5;
//output [1:0] coloff_bot_c5;
output [3:0] worden_top_c3b;
output [3:0] worden_bot_c3b;
input [19:0] sat_lo0_bc_l; // Senseamp out from top-16kb
input [19:0] sat_hi0_bc_l; // Senseamp out from top-16kb
input [18:0] sat_lo1_bc_l; // Senseamp out from top-16kb
input [18:0] sat_hi1_bc_l; // Senseamp out from top-16kb
input [19:0] sab_lo0_bc_l; // Senseamp out from bot-16kb
input [19:0] sab_hi0_bc_l; // Senseamp out from bot-16kb
input [18:0] sab_lo1_bc_l; // Senseamp out from bot-16kb
input [18:0] sab_hi1_bc_l; // Senseamp out from bot-16kb
//input bnken_lat; // Address latch enable (1.5cycle)
output [19:0] ldout0lo_b;
output [19:0] ldout0hi_b;
output [18:0] ldout1lo_b;
output [18:0] ldout1hi_b;
output [9:0] red_d_out_00;
input [2:0] fuse_l2d_rid_00;
input fuse_l2d_reset_00_l;
output [9:0] red_d_out_01;
input [2:0] fuse_l2d_rid_01;
input fuse_l2d_reset_01_l;
output [9:0] red_addr_top;
output [9:0] red_addr_bot;
input [9:0] red_top_d_00;
input [9:0] red_top_d_01;
//output fuse_l2d_reset_00_l_buf;
//output fuse_l2d_reset_01_l_buf;
reg [3:0] worden_top_c3b;
reg [3:0] worden_bot_c3b;
reg [7:0] waysel_top_c3b;
reg [7:0] waysel_bot_c3b;
coloff_top_c3b_l <= ~coloff_c3;
coloff_bot_c3b_l <= ~coloff_c3;
worden_top_c3b[3:0] <= worden_c3[3:0];
worden_bot_c3b[3:0] <= worden_c3[3:0];
writeen_top_c3b <= ~rd_wr_c3;
writeen_bot_c3b <= ~rd_wr_c3;
//always@(l2clk or bnken_lat)
always@(l2clk or coloff_c4_l)
waysel_top_c3b[7:0] <= waysel_c3[7:0];
waysel_bot_c3b[7:0] <= waysel_c3[7:0];
set_bot_c3b[8:0] <= set_c3[8:0];
set_top_c3b[8:0] <= {~set_c3[8],set_c3[7:0]};
waysel_top_c4[7:0] <= waysel_top_c3b[7:0];
waysel_bot_c4[7:0] <= waysel_bot_c3b[7:0];
//assign readen_top_c5 = readen_c5;
//assign readen_bot_c5 = readen_c5;
//assign coloff_top_c5 = coloff_c5[1:0];
//assign coloff_bot_c5 = coloff_c5[1:0];
//assign coloff_top_c4_l = coloff_c4_l;
//assign coloff_bot_c4_l = coloff_c4_l;
assign sat_lo0_bc[19:0] = ~sat_lo0_bc_l[19:0];
assign sab_lo0_bc[19:0] = ~sab_lo0_bc_l[19:0];
assign sat_hi0_bc[19:0] = ~sat_hi0_bc_l[19:0];
assign sab_hi0_bc[19:0] = ~sab_hi0_bc_l[19:0];
assign sat_lo1_bc[18:0] = ~sat_lo1_bc_l[18:0];
assign sab_lo1_bc[18:0] = ~sab_lo1_bc_l[18:0];
assign sat_hi1_bc[18:0] = ~sat_hi1_bc_l[18:0];
assign sab_hi1_bc[18:0] = ~sab_hi1_bc_l[18:0];
n2_l2d_dmux78_cust_or_macro__ports_3__width_20 or_ldout0lo_b
.dout (ldout0lo_b[19:0]),
.din0 (sat_lo0_bc[19:0]),
.din1 (sab_lo0_bc[19:0]),
n2_l2d_dmux78_cust_or_macro__ports_3__width_20 or_ldout0hi_b
.dout (ldout0hi_b[19:0]),
.din0 (sat_hi0_bc[19:0]),
.din1 (sab_hi0_bc[19:0]),
n2_l2d_dmux78_cust_or_macro__ports_3__width_19 or_ldout1lo_b
.dout (ldout1lo_b[18:0]),
.din0 (sat_lo1_bc[18:0]),
.din1 (sab_lo1_bc[18:0]),
n2_l2d_dmux78_cust_or_macro__ports_3__width_19 or_ldout1hi_b
.dout (ldout1hi_b[18:0]),
.din0 (sat_hi1_bc[18:0]),
.din1 (sab_hi1_bc[18:0]),
cl_sc1_l1hdr_12x clk_hdr (
// Redudant row modelling
//reg [9:0] red_d_out_00;
//reg [9:0] red_d_out_01;
// Initialize the register.
assign red_reg_clk_even_0 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b000) & sel_quad_00) | ~fuse_l2d_reset_00_l);
assign red_reg_clk_even_1 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b010) & sel_quad_00) | ~fuse_l2d_reset_00_l);
assign red_reg_clk_col_0 =~((~l1clk & fuse_l2d_wren_00 & (fuse_l2d_rid_00[2:0]==3'b100) & sel_quad_00) | ~fuse_l2d_reset_00_l);
assign red_reg_clk_odd_0 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b001) & sel_quad_01) | ~fuse_l2d_reset_01_l);
assign red_reg_clk_odd_1 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b011) & sel_quad_01) | ~fuse_l2d_reset_01_l);
assign red_reg_clk_col_1 =~((~l1clk &fuse_l2d_wren_01& (fuse_l2d_rid_01[2:0]==3'b101) & sel_quad_01) | ~fuse_l2d_reset_01_l);
assign red_data_00[9:0] = red_d_in_00[9:0] & {10{fuse_l2d_reset_00_l}};
assign red_data_01[9:0] = red_d_in_01[9:0] & {10{fuse_l2d_reset_01_l}};
always @(red_reg_clk_even_0 or red_reg_clk_even_1 or red_reg_clk_col_0 or red_reg_clk_odd_0 or red_reg_clk_odd_1 or red_reg_clk_col_1 or red_d_in_00 or red_d_in_01) begin
if (~red_reg_clk_even_0) begin
red_even_0[9:0] <= red_data_00[9:0];
if (~red_reg_clk_even_1) begin
red_even_1[9:0] <= red_data_00[9:0];
if (~red_reg_clk_col_0) begin
red_col_0[7:0] <= {red_data_00[9:8],red_data_00[5:0]};
if (~red_reg_clk_odd_0) begin
red_odd_0[9:0] <= red_data_01[9:0];
if (~red_reg_clk_odd_1) begin
red_odd_1[9:0] <= red_data_01[9:0];
if (~red_reg_clk_col_1) begin
red_col_1[7:0] <= {red_data_01[9:8],red_data_01[5:0]};
//always@(fuse_l2d_wren_00 or fuse_l2d_wren_01 or fuse_l2d_rid_01 or fuse_l2d_rid_00
// or red_d_in_00 or red_d_in_01 or sel_quad_00 or sel_quad_01)
// if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & set_bot_c3b[8] & (fuse_l2d_rid_00[2:1]==2'b00) & sel_quad_00)
// red_even_0 <= red_d_in_00;
// else if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & set_top_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b01) & sel_quad_00)
// red_even_1 <= red_d_in_00;
// else if(fuse_l2d_wren_00 & ~fuse_l2d_rid_00[0] & (fuse_l2d_rid_01[2:1]==2'b10) & sel_quad_00)
// red_col_0 <= red_d_in_00[7:0];
// if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & set_top_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b00) & sel_quad_01)
// red_odd_0 <= red_d_in_01;
// else if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & set_bot_c3b[8] & (fuse_l2d_rid_01[2:1]==2'b01) & sel_quad_01)
// red_odd_1 <= red_d_in_01;
// else if(fuse_l2d_wren_01 & fuse_l2d_rid_01[0] & (fuse_l2d_rid_01[2:1]==2'b10) & sel_quad_01)
// red_col_1 <= red_d_in_01[7:0];
//assign red_addr_top = set_top_c3b[0] ? red_odd_0 : red_even_0;
//assign red_addr_bot = set_top_c3b[0] ? red_odd_1 : red_even_1;
assign red_addr_top = set_top_c3b[0] ? red_odd_1 : red_even_1;
assign red_addr_bot = set_top_c3b[0] ? red_odd_0 : red_even_0;
assign red_d_out_00[7:0] = (red_even_0[7:0] & {8{fuse_l2d_rid_00[2:0]==3'b000}}) |
(red_even_1[7:0] & {8{fuse_l2d_rid_00[2:0]==3'b010}}) |
({2'b0,(red_col_0[5:0] & {6{fuse_l2d_rid_00[2:0]==3'b100}})}) |
(red_top_d_00[7:0] & {8{~sel_quad_00}});
assign red_d_out_00[9:8] = (red_even_0[9:8] & {2{fuse_l2d_rid_00[2:0]==3'b000}}) |
(red_even_1[9:8] & {2{fuse_l2d_rid_00[2:0]==3'b010}}) |
(red_col_0[7:6] & {2{fuse_l2d_rid_00[2:0]==3'b100}}) |
(red_top_d_00[9:8] & {2{~sel_quad_00}});
assign red_d_out_01[7:0] = (red_odd_0[7:0] & {8{fuse_l2d_rid_01[2:0]==3'b001}}) |
(red_odd_1[7:0] & {8{fuse_l2d_rid_01[2:0]==3'b011}}) |
({2'b0,(red_col_1[5:0] & {6{fuse_l2d_rid_01[2:0]==3'b101}})}) |
(red_top_d_01[7:0] & {8{~sel_quad_01}});
assign red_d_out_01[9:8] = (red_odd_0[9:8] & {2{fuse_l2d_rid_01[2:0]==3'b001}}) |
(red_odd_1[9:8] & {2{fuse_l2d_rid_01[2:0]==3'b011}}) |
(red_col_1[7:6] & {2{fuse_l2d_rid_01[2:0]==3'b101}}) |
(red_top_d_01[9:8] & {2{~sel_quad_01}});
//always@(fuse_l2d_rid_00)
// red_d_out_00 = red_even_0;
// red_d_out_00 = red_even_1;
// red_d_out_00 = {2'b0,red_col_0};
// red_d_out_01 = red_odd_0;
// red_d_out_01 = red_odd_1;
// red_d_out_01 = {2'b0,red_col_1};
// red_d_out_00 = red_top_d_00;
// red_d_out_01 = red_top_d_01;
// Initialize cred0, cred1
if(red_col_0[7] & red_col_0[6] & ~red_col_0[5])
8'b11_0_00000 : cred0[18:0] = 19'b111_1111_1111_1111_1111; //0
8'b11_0_00001 : cred0[18:0] = 19'b111_1111_1111_1111_1110; //1
8'b11_0_00010 : cred0[18:0] = 19'b111_1111_1111_1111_1100; //2
8'b11_0_00011 : cred0[18:0] = 19'b111_1111_1111_1111_1000; //3
8'b11_0_00100 : cred0[18:0] = 19'b111_1111_1111_1111_0000; //4
8'b11_0_00101 : cred0[18:0] = 19'b111_1111_1111_1110_0000; //5
8'b11_0_00110 : cred0[18:0] = 19'b111_1111_1111_1100_0000; //6
8'b11_0_00111 : cred0[18:0] = 19'b111_1111_1111_1000_0000; //7
8'b11_0_01000 : cred0[18:0] = 19'b111_1111_1111_0000_0000; //8
8'b11_0_01001 : cred0[18:0] = 19'b111_1111_1110_0000_0000; //9
8'b11_0_01010 : cred0[18:0] = 19'b111_1111_1100_0000_0000; //10
8'b11_0_01011 : cred0[18:0] = 19'b111_1111_1000_0000_0000; //11
8'b11_0_01100 : cred0[18:0] = 19'b111_1111_0000_0000_0000; //12
8'b11_0_01101 : cred0[18:0] = 19'b111_1110_0000_0000_0000; //13
8'b11_0_01110 : cred0[18:0] = 19'b111_1100_0000_0000_0000; //14
8'b11_0_01111 : cred0[18:0] = 19'b111_1000_0000_0000_0000; //15
8'b11_0_10000 : cred0[18:0] = 19'b111_0000_0000_0000_0000; //16
8'b11_0_10001 : cred0[18:0] = 19'b110_0000_0000_0000_0000; //17
8'b11_0_10010 : cred0[18:0] = 19'b100_0000_0000_0000_0000; //18
default : cred0[18:0] = 19'b0;
else cred0[18:0] = 19'b0;
if(red_col_0[7] & red_col_0[6] & red_col_0[5])
8'b11_1_00000 : cred0[38:19] = 20'b1111_1111_1111_1111_1111;//0
8'b11_1_00001 : cred0[38:19] = 20'b0111_1111_1111_1111_1111;//1
8'b11_1_00010 : cred0[38:19] = 20'b0011_1111_1111_1111_1111;//2
8'b11_1_00011 : cred0[38:19] = 20'b0001_1111_1111_1111_1111;//3
8'b11_1_00100 : cred0[38:19] = 20'b0000_1111_1111_1111_1111;//4
8'b11_1_00101 : cred0[38:19] = 20'b0000_0111_1111_1111_1111;//5
8'b11_1_00110 : cred0[38:19] = 20'b0000_0011_1111_1111_1111;//6
8'b11_1_00111 : cred0[38:19] = 20'b0000_0001_1111_1111_1111;//7
8'b11_1_01000 : cred0[38:19] = 20'b0000_0000_1111_1111_1111;//8
8'b11_1_01001 : cred0[38:19] = 20'b0000_0000_0111_1111_1111;//9
8'b11_1_01010 : cred0[38:19] = 20'b0000_0000_0011_1111_1111;//10
8'b11_1_01011 : cred0[38:19] = 20'b0000_0000_0001_1111_1111;//11
8'b11_1_01100 : cred0[38:19] = 20'b0000_0000_0000_1111_1111;//12
8'b11_1_01101 : cred0[38:19] = 20'b0000_0000_0000_0111_1111;//13
8'b11_1_01110 : cred0[38:19] = 20'b0000_0000_0000_0011_1111;//14
8'b11_1_01111 : cred0[38:19] = 20'b0000_0000_0000_0001_1111;//15
8'b11_1_10000 : cred0[38:19] = 20'b0000_0000_0000_0000_1111;//16
8'b11_1_10001 : cred0[38:19] = 20'b0000_0000_0000_0000_0111;//17
8'b11_1_10010 : cred0[38:19] = 20'b0000_0000_0000_0000_0011;//18
8'b11_1_10011 : cred0[38:19] = 20'b0000_0000_0000_0000_0001;//19
default : cred0[38:19] = 20'b0;
else cred0[38:19] = 20'b0;
if(red_col_1[7] & red_col_1[6] & red_col_1[5])
8'b11_1_00000 : cred1[19:0] = 20'b1111_1111_1111_1111_1111; //0
8'b11_1_00001 : cred1[19:0] = 20'b1111_1111_1111_1111_1110; //1
8'b11_1_00010 : cred1[19:0] = 20'b1111_1111_1111_1111_1100; //2
8'b11_1_00011 : cred1[19:0] = 20'b1111_1111_1111_1111_1000; //3
8'b11_1_00100 : cred1[19:0] = 20'b1111_1111_1111_1111_0000; //4
8'b11_1_00101 : cred1[19:0] = 20'b1111_1111_1111_1110_0000; //5
8'b11_1_00110 : cred1[19:0] = 20'b1111_1111_1111_1100_0000; //6
8'b11_1_00111 : cred1[19:0] = 20'b1111_1111_1111_1000_0000; //7
8'b11_1_01000 : cred1[19:0] = 20'b1111_1111_1111_0000_0000; //8
8'b11_1_01001 : cred1[19:0] = 20'b1111_1111_1110_0000_0000; //9
8'b11_1_01010 : cred1[19:0] = 20'b1111_1111_1100_0000_0000; //10
8'b11_1_01011 : cred1[19:0] = 20'b1111_1111_1000_0000_0000; //11
8'b11_1_01100 : cred1[19:0] = 20'b1111_1111_0000_0000_0000; //12
8'b11_1_01101 : cred1[19:0] = 20'b1111_1110_0000_0000_0000; //13
8'b11_1_01110 : cred1[19:0] = 20'b1111_1100_0000_0000_0000; //14
8'b11_1_01111 : cred1[19:0] = 20'b1111_1000_0000_0000_0000; //15
8'b11_1_10000 : cred1[19:0] = 20'b1111_0000_0000_0000_0000; //16
8'b11_1_10001 : cred1[19:0] = 20'b1110_0000_0000_0000_0000; //17
8'b11_1_10010 : cred1[19:0] = 20'b1100_0000_0000_0000_0000; //18
8'b11_1_10011 : cred1[19:0] = 20'b1000_0000_0000_0000_0000; //19
default : cred1[19:0] = 20'b0;
else cred1[19:0] = 20'b0;
if(red_col_1[7] & red_col_1[6] & ~red_col_1[5])
8'b11_0_00000 : cred1[38:20] = 19'b111_1111_1111_1111_1111;//0
8'b11_0_00001 : cred1[38:20] = 19'b011_1111_1111_1111_1111;//1
8'b11_0_00010 : cred1[38:20] = 19'b001_1111_1111_1111_1111;//2
8'b11_0_00011 : cred1[38:20] = 19'b000_1111_1111_1111_1111;//3
8'b11_0_00100 : cred1[38:20] = 19'b000_0111_1111_1111_1111;//4
8'b11_0_00101 : cred1[38:20] = 19'b000_0011_1111_1111_1111;//5
8'b11_0_00110 : cred1[38:20] = 19'b000_0001_1111_1111_1111;//6
8'b11_0_00111 : cred1[38:20] = 19'b000_0000_1111_1111_1111;//7
8'b11_0_01000 : cred1[38:20] = 19'b000_0000_0111_1111_1111;//8
8'b11_0_01001 : cred1[38:20] = 19'b000_0000_0011_1111_1111;//9
8'b11_0_01010 : cred1[38:20] = 19'b000_0000_0001_1111_1111;//10
8'b11_0_01011 : cred1[38:20] = 19'b000_0000_0000_1111_1111;//11
8'b11_0_01100 : cred1[38:20] = 19'b000_0000_0000_0111_1111;//12
8'b11_0_01101 : cred1[38:20] = 19'b000_0000_0000_0011_1111;//13
8'b11_0_01110 : cred1[38:20] = 19'b000_0000_0000_0001_1111;//14
8'b11_0_01111 : cred1[38:20] = 19'b000_0000_0000_0000_1111;//15
8'b11_0_10000 : cred1[38:20] = 19'b000_0000_0000_0000_0111;//16
8'b11_0_10001 : cred1[38:20] = 19'b000_0000_0000_0000_0011;//17
8'b11_0_10010 : cred1[38:20] = 19'b000_0000_0000_0000_0001;//18
default : cred1[38:20] = 19'b0;
else cred1[38:20] = 19'b0;
assign cred[77:0] = {cred1[38:0], cred0[38:0]};
//assign cred[77:0] = 78'b0;
//assign fuse_l2d_reset_00_buf = fuse_l2d_reset_00;
//assign fuse_l2d_reset_01_buf = fuse_l2d_reset_01;
// or macro for ports = 2,3
module n2_l2d_dmux78_cust_or_macro__ports_3__width_20 (
// or macro for ports = 2,3
module n2_l2d_dmux78_cust_or_macro__ports_3__width_19 (