* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: n2_err_pio_DMUSIIDP_NcuDP.s
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* ========== Copyright Header End ============================================
#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO
#define H_HT0_Data_access_error_0x32 My_Precise_data_access_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
#define MEM64_BASE mpeval(N2_PCIE_BASE_ADDR + (MEM64_OFFSET_BASE_REG_DATA & 0x7fffffffffffffff))
#define MEM64_RD_ADDR0 MEM64_BASE
!!#define MEM64_RD_ADDR0 mpeval(MEM64_BASE + 0x0000000000000000)
!!#define MEM64_RD_ADDR1 mpeval(MEM64_BASE + 0x0000000100000000)
!!#define MEM64_RD_ADDR2 mpeval(MEM64_BASE + 0x0000000200000000)
!!#define MEM64_RD_ADDR4 mpeval(MEM64_BASE + 0x0000000400000000)
!! Keep bit 39 set so that the data section gets read into gMem by vera
#define MEM64_OFFSET 0xaabbcc8000000000
!!#define MEM64_OFFSET_PLUS_GARBAGE mpeval(MEM64_OFFSET + 0x0000000000112233, 16, 16)
#define MEM64_OFFSET_PLUS_GARBAGE 0xaabbcc8000112233
!!#define MEM64_RD_ADDR0_PLUS_OFFSET mpeval(MEM64_OFFSET | MEM64_RD_ADDR0, 16, 16)
#define MEM64_RD_ADDR0_PLUS_OFFSET 0xaabbcc8000000000
#define BNE_TEST_FAIL bne test_failed
#define BNE_TEST_FAIL nop
#define SOC_SII_SYN_REG 0x8000003030
#define SOC_NCU_SYN_REG 0x8000003038
/************************************************************************
************************************************************************/
.global My_Precise_data_access_error_trap
.global My_Recoverable_Sw_error_trap
! Load the PCIE MEM64 OFFSET Register
setx FIRE_DLC_IMU_ICS_CSR_A_MEM_64_PCIE_OFFSET_REG_ADDR, %g1, %g2
setx MEM64_OFFSET_PLUS_GARBAGE, %g1, %g3
! select a MEM address in PCI address range and
! set up the data area using stores, because Midas does not seem to
! allow a .data section to be set up with an address > 2**39
setx MEM64_RD_ADDR0, %g1, %g2
setx 0x1011121314151617, %g1, %g3
setx 0x18191a1b1c1d1e1f, %g1, %g3
setx 0x2021222324252627, %g1, %g3
setx 0x28292a2b2c2d2e2f, %g1, %g3
setx 0x3031323334353637, %g1, %g3
setx 0x38393a3b3c3d3e3f, %g1, %g3
setx 0x4041424344454647, %g1, %g3
setx 0x48494a4b4c4d4e4f, %g1, %g3
/*******************************************************
********************************************************/
sllx %g1, ERR_FIELD_DETECT, %l2
setx SOC_EIE_REG, %g7, %g3
setx SOC_EJR_REG, %g7, %g3
!$EV trig_pc_d(0,@VA(.MAIN.inj_err1)) ->IosErrInj(DMUSII_DP, 8000, 000)
! 1 byte loads, all 16 offsets
nop ! $EV trig_pc_d(1, @VA(.MAIN.byte_os0)) -> printf("\n byte_os0 \n")
My_Precise_data_access_error_trap:
mov 0x4, %l5 ! content of D-SFSR Error type field = 0x4 (SOCU)
sllx %g1, ERR_FIELD_DETECT, %g2
setx 0x8000000000000000, %g7, %g3
setx SOC_PER_REG, %g7, %g2
setx SOC_SII_SYN_REG, %g7, %g1
setx SOC_NCU_SYN_REG, %g7, %g1
setx 0xfff8000000000000, %g7, %g1
setx 0xc070000000000000, %g7, %g2
!Temporarily disabled the check until the issue resolved
My_Recoverable_Sw_error_trap:
setx 0xb300000000000000, %l0, %g3
sllx %g1, ERR_FIELD_DETECT, %g2
setx 0x8000000000000000, %g7, %g3
setx SOC_PER_REG, %g7, %g2