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* OpenSPARC T2 Processor File: n2_err_L2_LDWC_trap_pending.s
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#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define MAIN_PAGE_HV_ALSO
#define L2_ENTRY_PA 0x517590000
#define TEST_DATA 0x555555555555555
#define L2_ES_W1C_VALUE 0xc03ffff800000000
#define REG_PSTATE_IE 0x2
.global My_Corrected_ECC_error_trap
! Boot code does not provide TLB translation for IO address space
setx L2_ES_W1C_VALUE, %l0, %g4
wrpr %g1,REG_PSTATE_IE,%pstate
! Now access L2 control and status registers
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
! Write 1 to clear L2 Error status registers
set_L2_Directly_Mapped_Mode:
setx 0x202000aa00, %l0, %g1
! Read L2 Data Diag - %g2 has the "way"
! Addressing: [39:32] See PRM, [22] odd/even word, [21:18] way, [17:8] set, [7:6] bank, [5:3] D-word, [2:0] = 0
setx 0x3fff8, %l0, %l2 ! Mask for extracting [17:3]
sllx %l0, 32, %l0 ! Bits [39:32]
or %g5, %l0, %g5 ! %g5 has L2 Data Diag addressing
! Flip one bit from the data field
xor %g6, 0x80, %g6 ! save on %g6 for future reference
! Now do another store with the same index but different tag - to force a Write-Back
xor %g1, %l0, %l1 ! Flip bit 28 of previous L2 entry PA
! This should cause L2 LDWC (bit 51)
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
! Compute expected value of L2 error status register
sllx %l1, L2ES_VEC, %l3 ! VEC bit
! No RW bit or Syndrome field for LDWC - %l0 has expected value
! Error address is the physical address of the cache line (PA[5:0] 0)
! Check if a Corrected ECC Trap happened
mov TT_Corrected_ECC, %l0
My_Corrected_ECC_error_trap:
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