* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: n2_err_L2_NotData_NDDM_shadow.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* ========== Copyright Header End ============================================
#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_ERR_STAT_REG 0x8400000280
#define L2_ERR_STAT_REG 0xAB00000000
#define L2_ERR_ADDR_REG 0xAC00000000
#define L2_NDDM_REG 0xAE00000000
#define ERROR_ADDR 0x20200000
#define TEST_DATA0 0x1000100081c3e008
#define TEST_DATA1 0x2000200081c3e008
#define TEST_DATA2 0x3000300081c3e008
#define L2_ES_W1C_VALUE 0xc03ffff800000000
#define DRAM_ES_W1C_VALUE 0xfe00000000000000
#define DMA_DATA_BYP_ADDR1 0xfffc00002000aa00
#define CLK_RATIO_VAL 0x03
#define CLK_RATIO_VAL 0x02
#define CLK_RATIO_VAL 0x01
#define CLK_RATIO_VAL 0x00
! Determine thread running on
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
setx 0x20040000, %l0, %g6
! Clear DRAM Error status register (Bit[63:57] write-1-clear)
setx DRAM_ES_W1C_VALUE, %l0, %g4
setx DRAM_ERR_STAT_REG, %l3, %g5
set_DRAM_error_inject_ch0:
mov 0x602, %l1 ! ECC Mask (2-bit error)
sllx %l2, DRAM_EI_SSHOT, %l3
Or %l1, %l3, %l1 ! Set single shot ;
sllx %l2, DRAM_EI_ENB, %l3
or %l1, %l3, %l1 ! Enable error injection for the next write
setx DRAM_ERR_INJ_REG, %l3, %g5
! setx L2EE_PA0, %l0, %l1
! Write 1 to clear L2 Error status registers
setx TEST_DATA1, %l0, %g5
set_L2_Directly_Mapped_Mode:
setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way
! Storing to same L2 way0 but different tag,this will write to mcu
setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way
! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 )
! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt1) -> EnablePCIeIgCmd ("DMARD_UE", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 )
setx DRAM_ERR_STAT_REG, %l3, %g5
setx 0xffffffffffff0000, %l0,%o2
sllx %l1, DRAM_ES_DAU, %l0
setx L2_ERR_STAT_REG, %l3, %g5
setx 0xfffffffff0000000, %l3, %l0
andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits
setx L2_NDDM_REG, %l3, %g5
setx 0x900002000aa00, %l0, %l1 ! bits [21:18] select way
setx 0xfffffffffffc0, %l0,%o2
! Error address is the physical address of the cache line (PA[5:0] 0)
setx 0x2000aa00, %l0, %l1 ! bits [21:18] select way
setx 0xffffffffc0, %l0,%o2
/************************************************************************
************************************************************************/
! Sync up all the treads.
!Verify clock ratio counter value
setx 0x8000003040,%g7,%g1
setx CLK_RATIO_VAL,%g7,%g1
!Read words from the SSI interface
setx 0x000000fff0000000,%g7,%g1
/*******************************************************
*******************************************************/
/************************************************************************
************************************************************************/