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* OpenSPARC T2 Processor File: n2_err_l2_LDAU_st_uecc_trap.s
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#define MAIN_PAGE_HV_ALSO
#define L2_ENTRY_PA 0xa000000000
#define TEST_DATA1 0x5555555555555555
#define L2_ENTRY_PA0 0x2020000008
#define L2_ES_W1C_VALUE 0xc03ffff800000000
.global My_Recoverable_Sw_error_trap
! Boot code does not provide TLB translation for IO address space
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
setx L2_ES_W1C_VALUE, %l0, %l1
set_L2_Directly_Mapped_Mode:
setx TEST_DATA1, %l0, %g5
setx 0x202000aa00, %l0, %g2
setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
setx L2_ENTRY_PA, %l0, %g4
setx 0x202000aa00, %l0, %g2
stb %g0, [%g2 +1] ! Partial store
ldxa [%g0] ASI_LSU_CONTROL, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
!mov 0x46, %l1 ! 7-bit Syndrome
!sllx %l1, 21, %l3 ! Syndrome for [127:96] at [27:21]
!sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error
!or %l7, %l3, %l7 ! %l7 has expected value
! Not Checking SYND in this test
setx 0x202000aa00, %l0, %g2
! Check if a Software Recoverable Error Trap happened
My_Recoverable_Sw_error_trap:
/*******************************************************
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